U.S. patent application number 13/022875 was filed with the patent office on 2011-12-01 for scanning-line drive circuit.
This patent application is currently assigned to MITSUBISHI ELECTRIC CORPORATION. Invention is credited to Youichi TOBITA.
Application Number | 20110291712 13/022875 |
Document ID | / |
Family ID | 45021580 |
Filed Date | 2011-12-01 |
United States Patent
Application |
20110291712 |
Kind Code |
A1 |
TOBITA; Youichi |
December 1, 2011 |
SCANNING-LINE DRIVE CIRCUIT
Abstract
A gate-line drive circuit is driven by three clock signals of
different phases, and includes a plurality of cascade-connected
unit shift registers. In a normal operation, activation periods of
the three clock signals do not overlap one another. However, the
two clock signals of them are simultaneously activated at the
beginning of a frame period. A unit shift register of the first
stage is adapted to activate an output signal in accordance with
the simultaneous activation of the two clock signals.
Inventors: |
TOBITA; Youichi; (Tokyo,
JP) |
Assignee: |
MITSUBISHI ELECTRIC
CORPORATION
Chiyoda-ku
JP
|
Family ID: |
45021580 |
Appl. No.: |
13/022875 |
Filed: |
February 8, 2011 |
Current U.S.
Class: |
327/144 |
Current CPC
Class: |
H03K 5/135 20130101;
G09G 2300/0871 20130101; G11C 27/04 20130101; G09G 3/3677 20130101;
H03K 5/156 20130101; G09G 2310/08 20130101 |
Class at
Publication: |
327/144 |
International
Class: |
H03K 5/135 20060101
H03K005/135 |
Foreign Application Data
Date |
Code |
Application Number |
May 25, 2010 |
JP |
2010-119118 |
Claims
1. A scanning-line drive circuit driven by using at least three
clock signals of different phases, and including a plurality of
cascade-connected unit shift registers, wherein said plurality of
unit shift registers include a specified unit shift register which
activates an output signal when two of said three clock signals are
both set at an activation level.
2. The scanning-line drive circuit according to claim 1, wherein
said specified unit shift register is the most preceding stage of
the cascade connection.
3. The scanning-line drive circuit according to claim 2, wherein an
output signal of said specified unit shift register is supplied to
a gate line connected to a pixel.
4. The scanning-line drive circuit according to claim 1, wherein
said specified unit shift register includes: an output terminal
which outputs said output signal; a clock terminal to which a first
clock signal is supplied; a first input terminal to which second
clock signal is supplied; a second input terminal to which a third
clock signal is supplied; a first transistor which supplies said
first clock signal to said output terminal; and a charge circuit
connected to a first node to which a control electrode of said
first transistor is connected, said charge circuit charging said
first node when both of said second clock signal and said third
clock signal are brought into the activation level.
5. The scanning-line drive circuit according to claim 4, wherein
said charge circuit includes a series circuit of a second
transistor having a control electrode connected to said first input
terminal and a third transistor having a control electrode
connected to said second input terminal.
6. The scanning-line drive circuit according to claim 5, wherein
said series circuit is connected between a power source of a
constant potential and said first node.
7. The scanning-line drive circuit according to claim 5, wherein
said series circuit is connected between said first node and said
first or second input terminal.
8. The scanning-line drive circuit according to claim 4, wherein
said charge circuit is a fourth transistor having a control
electrode connected to one of said first and second input
terminals, and being connected between the other of said first and
second input terminals and said first node.
9. A scanning-line drive circuit driven by using at least three
clock signals of different phases, and including a plurality of
cascade-connected unit shift registers, said scanning-line drive
circuit being operable to perform a forward-direction shift for
shifting a signal from an immediately preceding stage toward a
subsequent stage and a reverse-direction shift for shifting a
signal from a subsequent stage toward a immediately preceding stage
in said plurality of unit shift registers, wherein said plurality
of unit shift registers include: a first unit shift register which
activates an output signal when two of said three clock signals are
both set at an activation level at a time of the forward-direction
shift; and a second unit shift register which activates an output
signal when two of said three clock signals are both set at the
activation level at a time of the reverse-direction shift.
10. The scanning-line drive circuit according to claim 9, wherein
said first unit shift register is the most preceding stage of the
cascade connection; and said second unit shift register is the last
stage of the cascade connection.
11. The scanning-line drive circuit according to claim 10, wherein
output signals of said first and second unit shift registers are
supplied to gate lines connected to pixels, respectively.
12. The scanning-line drive circuit according to claim 9, wherein
said first unit shift register comprises: an output terminal which
outputs said output signal; a clock terminal to which a first clock
signal is supplied; a first input terminal to which a second clock
signal is supplied; a second input terminal to which a third clock
signal is supplied; a first voltage signal terminal to which
supplied is a first voltage signal which is set at an activation
level at a time of the forward-direction shift and at a
deactivation level at a time of the reverse-direction shift; a
second voltage signal terminal to which supplied is a second
voltage signal which is set at an activation level at a time of the
reverse-direction shift and at a deactivation level at a time of
the forward-direction shift; a first transistor which supplies said
first clock signal to said output terminal; second and third
transistors connected in series between said first voltage signal
terminal and said first node; and a fourth transistor having a
control electrode to which an output signal of a next-stage unit
shift register is inputted, said fourth transistor being connected
between said first node and said second voltage signal terminal, a
control electrode of said second transistor is connected to said
first input terminal, a control electrode of said third transistor
is connected to said second input terminal.
13. The scanning-line drive circuit according to claim 12, wherein
said first unit shift register is the most preceding stage of the
cascade connection, at a time of the reverse-direction shift, said
second and third clock signals are both set at the activation level
for a predetermined time period after an activation period of the
output signal of said first unit shift register.
14. The scanning-line drive circuit according to claim 13, wherein
during said predetermined time period, said second voltage signal
is set at the deactivation level.
15. The scanning-line drive circuit according to claim 9, wherein
said second unit shift register comprises: an output terminal which
outputs said output signal; a clock terminal to which a first clock
signal is supplied; a first input terminal to which a second clock
signal is supplied; a second input terminal to which a third clock
signal is supplied; a first voltage signal terminal to which
supplied is a first voltage signal which is set at an activation
level at a time of the forward-direction shift and at a
deactivation level at a time of the reverse-direction shift; a
second voltage signal terminal to which supplied is a second
voltage signal which is set at an activation level at a time of the
reverse-direction shift and at a deactivation level at a time of
the forward-direction shift; a first transistor which supplies said
first clock signal to said output terminal; second and third
transistors connected in series between said second voltage signal
terminal and said first node; and a fourth transistor having a
control electrode to which an output signal of a unit shift
register of an immediately preceding stage is inputted, said fourth
transistor being connected between said first node and said first
voltage signal terminal, a control electrode of said second
transistor is connected to said first input terminal, a control
electrode of said third transistor is connected to said second
input terminal.
16. The scanning-line drive circuit according to claim 15, wherein
said second unit shift register is the last stage of the cascade
connection, at a time of the forward-direction shift, said second
and third clock signals are both set at the activation level for a
predetermined time period after an activation period of the output
signal of said second unit shift register.
17. The scanning-line drive circuit according to claim 16, wherein
during said predetermined time period, said first voltage signal is
set at the deactivation level.
18. A scanning-line drive circuit driven by using at least two
clock signals of different phases, and including a plurality of
cascade-connected unit shift registers, wherein said scanning-line
drive circuit is operable to perform a forward-direction shift for
shifting a signal from an immediately preceding stage toward a
subsequent stage and a reverse-direction shift for shifting a
signal from a subsequent stage toward a immediately preceding stage
in said plurality of unit shift registers, said scanning-line drive
circuit comprises: a first voltage signal terminal to which
supplied is a first voltage signal which is set at an activation
level at a time of the forward-direction shift and at a
deactivation level at a time of the reverse-direction shift; and a
second voltage signal terminal to which supplied is a second
voltage signal which is set at an activation level at a time of the
reverse-direction shift and at a deactivation level at a time of
the forward-direction shift, said plurality of unit shift registers
include: a first unit shift register which activates an output
signal when said first and second voltage signals are both set at
an activation level at a time of the forward-direction shift; and a
second unit shift register which activates an output signal when
said first and second voltage signals are both set at the
activation level at a time of the reverse-direction shift.
19. The scanning-line drive circuit according to claim 18, wherein
said first unit shift register is the most preceding stage of the
cascade connection, said second unit shift register is the last
stage of the cascade connection.
20. The scanning-line drive circuit according to claim 19, wherein
output signals of said first and second unit shift registers are
supplied to gate lines connected to pixels, respectively.
21. The scanning-line drive circuit according to claim 18, wherein
said first unit shift register comprises: an output terminal which
outputs said output signal; a clock terminal to which a first clock
signal is supplied; a first input terminal to which said first
voltage signal is supplied; a second input terminal to which said
second voltage signal is supplied; third input terminal to which a
second clock signal is supplied; a first transistor which supplies
said first clock signal to said output terminal; second and third
transistors connected in series between said third input terminal
and a first node to which a control electrode of said first
transistor is connected; and a fourth transistor having a control
electrode to which an output signal of a next-stage unit shift
register is inputted, said fourth transistor being connected
between said first node and said second voltage signal terminal, a
control electrode of said second transistor is connected to said
first input terminal, a control electrode of said third transistor
is connected to said second input terminal.
22. The scanning-line drive circuit according to claim 21, wherein
said first unit shift register is the most preceding stage of the
cascade connection, at a time of the reverse-direction shift, said
first and second voltage signals are both set at the activation
level and said second clock signal is set at the deactivation
level, for a predetermined time period after an activation period
of the output signal of said first unit shift register.
23. The scanning-line drive circuit according to claim 22, wherein
during said predetermined time period, said first clock signal is
set at the deactivation level.
24. The scanning-line drive circuit according to claim 18, wherein
said second unit shift register comprises: an output terminal which
outputs said output signal; a clock terminal to which a first clock
signal is supplied; a first input terminal to which said first
voltage signal is supplied; a second input terminal to which said
second voltage signal is supplied; a third input terminal to which
a second clock signal is supplied; a first transistor which
supplies said first clock signal to said output terminal; second
and third transistors connected in series between said third input
terminal and a first node to which a control electrode of said
first transistor is connected; and a fourth transistor having a
control electrode to which an output signal of a unit shift
register of an immediately preceding stage is inputted, said fourth
transistor being connected between said first node and said first
voltage signal terminal, a control electrode of said second
transistor is connected to said first input terminal, a control
electrode of said third transistor is connected to said second
input terminal.
25. The scanning-line drive circuit according to claim 24, wherein
said second unit shift register is the last stage of the cascade
connection, at a time of the forward-direction shift, said first
and second voltage signals are both set at the activation level and
said second clock signal is set at the deactivation level, for a
predetermined time period after an activation period of the output
signal of said second unit shift register.
26. The scanning-line drive circuit according to claim 25, wherein
during said predetermined time period, said first clock signal is
set at the deactivation level.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a scanning-line drive
circuit used in an electro-optical device such as an image display
device and an imaging device, and particularly to a scanning-line
drive circuit configured with only field effect transistors of the
same conductivity type.
[0003] 2. Description of the Background Art
[0004] An electro-optical device including a scanning-line drive
circuit connected to a scanning line and scanning pixels is widely
known. For example, in an image display device (hereinafter,
referred to as a "display device") such as a liquid crystal display
device, a gate line (scanning line) is provided for each of pixel
lines of a display element (display panel) having a plurality of
pixels arranged in lines and columns (in a matrix), and the gate
lines are sequentially selected and driven in the cycle of one
horizontal period of a display signal, to thereby update a display
image. As a gate-line drive circuit (scanning-line drive circuit)
for sequentially selecting and driving the pixel lines, that is,
the gate lines, there may be adopted a shift register which
performs shifting whose one-round operation is made in a one-frame
period of the display signal.
[0005] Pixels of an imaging element used in an imaging device are
also arranged in a matrix, and these pixels are scanned by a
gate-line drive circuit to thereby extract data of a captured
image. A shift register may be adopted as a gate-line drive circuit
of the imaging device, too.
[0006] A shift register serving as a gate-line drive circuit
includes a plurality of cascade-connected shift register circuits
provided for each one of the pixel lines, that is, each one of the
gate lines. In this specification, each of the plurality of shift
register circuits included in the gate-line drive circuit is called
a "unit shift register". Thus, an output terminal of each
individual unit shift register included in the gate-line drive
circuit is connected to a corresponding gate line, and moreover
connected to an input terminal of the next-stage or the
subsequent-stage unit shift register.
[0007] It is desirable that the shift register used in the
gate-line drive circuit is configured with only field effect
transistors of the same display device, in order to reduce the
number of steps of the manufacturing process for a cost
reduction.
[0008] The gate-line drive circuit is operated so as to
sequentially select the gate lines by transmitting a start pulse
inputted the unit shift register of the most preceding stage to the
subsequent-stage unit shift registers one after another. The start
pulse is a signal (external signal) supplied from the outside of
the gate-line drive circuit, and generated by a start pulse
generation circuit which is formed on a substrate different from a
substrate on which the gate-line drive circuit is formed.
[0009] However, an increase in the number of external signals
causes an increase in the number of necessary circuits such as a
circuit for generating the external signal and a level shifter for
adjusting the level of the external signal. This may be a factor in
a cost increase of the device. Accordingly, in order to reduce the
manufacturing cost of an electro-optical device, it is preferable
to reduce the number of external signals as small as possible. For
this purpose, there has been made an attempt to reduce the number
of external signals by providing the start pulse generation circuit
on the same substrate as the gate-line drive circuit is provided to
thereby eliminate the need to supply the start pulse from the
outside (for example, Japanese Patent Application Laid-Open No.
2006-269002; and Specification of United States Patent Application
Publication No. 2008/0122774).
[0010] The number of external signals can be reduced, by providing
the start pulse generation circuit and the gate-line drive circuit
on the same substrate as disclosed in Japanese Patent Application
Laid-Open No. 2006-269002 and Specification of United States Patent
Application Publication No. 2008/0122774. However, as a matter of
course, it is necessary that the area for forming the start pulse
generation circuit is ensured on the substrate. From the viewpoint
of the manufacturing cost, it is preferable that the substrate has
a small area.
SUMMARY OF THE INVENTION
[0011] An object of the present invention is to provide a
scanning-line drive circuit including only transistors of the same
conductivity type and requiring no start pulse generation
circuit.
[0012] A scanning-line drive circuit according to a first aspect of
the present invention is driven by using at least three clock
signals of different phases, and includes a plurality of
cascade-connected unit shift registers. The plurality of unit shift
registers include a specified unit shift register which activates
an output signal when two of the three clock signals are both set
at an activation level.
[0013] A scanning-line drive circuit according to a second aspect
of the present invention is driven by using at least three clock
signals of different phases, and includes a plurality of
cascade-connected unit shift registers. The scanning-line drive
circuit is operable to perform a forward-direction shift for
shifting a signal from an immediately preceding stage toward a
subsequent stage and a reverse-direction shift for shifting a
signal from a subsequent stage toward a immediately preceding stage
in the plurality of unit shift registers. The plurality of unit
shift registers include: a first unit shift register which
activates an output signal when two of the three clock signals are
both set at an activation level at a time of the forward-direction
shift; and a second unit shift register which activates an output
signal when two of the three clock signals are both set at the
activation level at a time of the reverse-direction shift.
[0014] A scanning-line drive circuit according to a third aspect of
the present invention is driven by using at least two clock signals
of different phases, and including a plurality of cascade-connected
unit shift registers. The scanning-line drive circuit is operable
to perform a forward-direction shift for shifting a signal from an
immediately preceding stage toward a subsequent stage and a
reverse-direction shift for shifting a signal from a subsequent
stage toward a immediately preceding stage in the plurality of unit
shift registers. The scanning-line drive circuit comprises: a first
voltage signal terminal to which supplied is a first voltage signal
which is set at an activation level at a time of the
forward-direction shift and at a deactivation level at a time of
the reverse-direction shift; and a second voltage signal terminal
to which supplied is a second voltage signal which is set at an
activation level at a time of the reverse-direction shift and at a
deactivation level at a time of the forward-direction shift. The
plurality of unit shift registers include: a first unit shift
register which activates an output signal when the first and second
voltage signals are both set at an activation level at a time of
the forward-direction shift; and a second unit shift register which
activates an output signal when the first and second voltage
signals are both set at the activation level at a time of the
reverse-direction shift.
[0015] The scanning-line drive circuit according to the present
invention requires no start pulse generation circuit. Therefore,
the area of a substrate can be reduced, to contribute to a
reduction in the manufacturing cost.
[0016] These and other objects, features, aspects and advantages of
the present invention will become more apparent from the following
detailed description of the present invention when taken in
conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] FIG. 1 is a block diagram schematically showing a
configuration of a display device which is an example of
application of the present invention;
[0018] FIG. 2 is a block diagram of a gate-line drive circuit
according to a preferred embodiment 1;
[0019] FIG. 3 is a circuit diagram showing an example of a unit
shift register;
[0020] FIG. 4 is a circuit diagram of a first-stage unit shift
register according to the preferred embodiment 1;
[0021] FIG. 5 is a diagram showing a circuit configuration of the
gate-line drive circuit according to the preferred embodiment
1;
[0022] FIG. 6 is a diagram showing the circuit configuration of the
gate-line drive circuit according to the preferred embodiment
1;
[0023] FIG. 7 is a timing chart showing an operation of the unit
shift register of FIG. 3;
[0024] FIG. 8 is a timing chart showing an operation of a unit
shift register according to the preferred embodiment 1;
[0025] FIG. 9 is a timing chart showing an operation of the
gate-line drive circuit according to the preferred embodiment
1;
[0026] FIGS. 10A, 10B, and 10C are diagrams for explaining a
modification of the preferred embodiment 1;
[0027] FIG. 11 is a block diagram of a gate-line drive circuit
according to the preferred embodiment 2;
[0028] FIG. 12 is a circuit diagram of an example of a
bi-directional unit shift register;
[0029] FIG. 13 is a circuit diagram of a first-stage unit shift
register according to the preferred embodiment 2;
[0030] FIG. 14 is a circuit diagram of a last-stage unit shift
register according to the preferred embodiment 2;
[0031] FIG. 15 is a circuit diagram of a dummy unit shift register
provided in the next stage of the last stage;
[0032] FIG. 16 is a circuit diagram of a dummy unit shift register
provided in the immediately preceding stage of the first stage;
[0033] FIG. 17 is a diagram showing a circuit configuration of the
gate-line drive circuit according to the preferred embodiment
2;
[0034] FIG. 18 is a diagram showing the circuit configuration of
the gate-line drive circuit according to the preferred embodiment
2;
[0035] FIG. 19 is a timing chart showing an operation of the
gate-line drive circuit according to the preferred embodiment 2 at
a time of a forward-direction shift;
[0036] FIG. 20 is a timing chart showing an operation of the
gate-line drive circuit according to the preferred embodiment 2 at
a time a reverse-direction shift;
[0037] FIG. 21 is a block diagram of a gate-line drive circuit
according to a modification of the preferred embodiment 2;
[0038] FIG. 22 is a circuit diagram of a first-stage unit shift
register according to the modification of the preferred embodiment
2;
[0039] FIG. 23 is a circuit diagram of a last-stage unit shift
register according to the modification of the preferred embodiment
2;
[0040] FIG. 24 is a diagram showing a circuit configuration of the
gate-line drive circuit according to the modification of the
preferred embodiment 2;
[0041] FIG. 25 is a diagram showing a circuit configuration of the
gate-line drive circuit according to the modification of the
preferred embodiment 2;
[0042] FIG. 26 is a timing chart showing an operation of the
gate-line drive circuit according to the modification of the
preferred embodiment 2 at a time of the forward-direction
shift;
[0043] FIG. 27 is a timing chart showing an operation of the
gate-line drive circuit according to the modification of the
preferred embodiment 2 at a time of the reverse-direction
shift;
[0044] FIG. 28 is a block diagram of a gate-line drive circuit
according to a preferred embodiment 3;
[0045] FIG. 29 is a circuit diagram of a first-stage
(most-preceding stage) unit shift register according to the
preferred embodiment 3;
[0046] FIG. 30 is a circuit diagram of an n-th stage (last-stage)
unit shift register according to the preferred embodiment 3;
[0047] FIG. 31 is a circuit diagram of a dummy unit shift register
provided in the next stage of a last-stage;
[0048] FIG. 32 is a circuit diagram of a dummy unit shift register
provided in the immediately preceding stage of the first-stage;
[0049] FIG. 33 is a diagram showing a circuit configuration of the
gate-line drive circuit according to the preferred embodiment
3;
[0050] FIG. 34 is a diagram showing a circuit configuration of the
gate-line drive circuit according to the preferred embodiment
3;
[0051] FIG. 35 is a timing chart showing an operation of the
gate-line drive circuit according to the preferred embodiment 3 at
a time of the forward-direction shift;
[0052] FIG. 36 is a timing chart showing an operation of the
gate-line drive circuit according to the preferred embodiment 3 at
a time of the reverse-direction shift;
[0053] FIG. 37 is a block diagram of a gate-line drive circuit
according to a modification of the preferred embodiment 3;
[0054] FIG. 38 is a circuit diagram of a first-stage unit shift
register according to the modification of the preferred embodiment
3;
[0055] FIG. 39 is a circuit diagram of a last-stage unit shift
register according to the modification of the preferred embodiment
3;
[0056] FIG. 40 is a diagram showing a circuit configuration of the
gate-line drive circuit according to the modification of the
preferred embodiment 3
[0057] FIG. 41 is a diagram showing a circuit configuration of the
gate-line drive circuit according to the modification of the
preferred embodiment 3;
[0058] FIG. 42 is a timing chart showing an operation of the
gate-line drive circuit according to the modification of the
preferred embodiment 3 at a time of the forward-direction
shift;
[0059] FIG. 43 is a timing chart showing an operation of the
gate-line drive circuit according to the modification of the
preferred embodiment 3 at a time of the reverse-direction shift;
and
[0060] FIG. 44 is a block diagram of a gate-line drive circuit
according to a preferred embodiment 4.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0061] Hereinafter, a preferred embodiment of the present invention
will be described with reference to the accompanying drawings. In
order to avoid duplicative and thus redundant descriptions,
elements having the same or equivalent function are denoted by the
same reference sign in the drawings.
[0062] A transistor used in each preferred embodiment is an
insulated gate type field effect transistor. In the insulated gate
type field effect transistor, the electrical conductivity between a
drain region and a source region in the semiconductor layer is
controlled by an electric field in a gate insulating film. As a
material of the semiconductor layer in which the drain region and
the source region are formed, an organic semiconductor of
polysilicon, amorphous silicon, pentacene or the like, or an oxide
semiconductor of single-crystal silicon, IGZO (In--Ga--Zn--O) or
the like, can be adopted, for example.
[0063] As well known, a transistor is an element having at least
three electrodes including a control electrode (a gate (electrode)
in a limited sense), one current electrode (a drain (electrode) or
a source (electrode) in a limited sense), and the other current
electrode (a source (electrode) or a drain (electrode) in a limited
sense). The transistor functions as a switching element in which a
channel is formed between a drain and a source by application of a
predetermined voltage to a gate. The drain and the source of the
transistor basically have identical structures, and their nominal
designations are exchanged depending on the conditions of a voltage
applied. For example, in an N-type transistor, an electrode having
a relatively high potential (hereinafter also referred to as a
"level") is called a drain while an electrode having relatively low
potential is called a source (in a P-type transistor, the reverse
applies).
[0064] If not otherwise specified, the transistor may be formed on
a semiconductor substrate, or may be a thin-film transistor (TFT)
formed on an insulating substrate of glass or the like. As a
substrate on which the transistor is formed, there may be adopted a
single-crystal substrate, or an insulating substrate of SOI, glass,
a resin, or the like.
[0065] A gate-line drive circuit of the present invention is formed
using only transistors of a single conductivity type. For example,
an N-type transistor is activated (an ON state, a conducting state)
when the voltage between the gate and the source thereof is at the
H (high) level which is higher than a threshold voltage of this
transistor, and deactivated (an OFF state, a non-conducting state)
when the voltage is at the L (low) level which is lower than the
threshold voltage. Accordingly, in a circuit using an N-type
transistor, the H level of a signal corresponds to an "activation
level", and the L level thereof corresponds to a "deactivation
level". In the circuit using the N-type transistor, when each node
is charged and brought into the H level, a shift from the
deactivation level to the activation level occurs, and when the
node is discharged and brought into the L level, a shift from the
activation level to the deactivation level occurs.
[0066] On the other hand, a P-type transistor is activated (an ON
state, a conducting state) when the voltage between the gate and
the source thereof is at the L level which is lower than a
threshold voltage (a negative value based on the source) of the
transistor, and deactivated (an OFF state, a non-conducting state)
when the voltage is at the H level which is higher than the
threshold voltage. Accordingly, in a circuit using a P-type
transistor, the L level of a signal corresponds to an "activation
level", and the H level thereof corresponds to a "deactivation
level". In the circuit using the P-type transistor, the
relationship of charging and discharging of each node is opposite
to that of the N-type transistor. Thus, when each node is charged
and brought into the L level, a shift from the deactivation level
to the activation level occurs, and when the node is discharged and
brought into the H level, a shift from the activation level to the
deactivation level occurs.
[0067] In this specification, the shift from the deactivation level
to the activation level is defined as a "pull-up", and the shift
from the activation level to the deactivation level is defined as
"pull-down". That is, in the circuit using the N-type transistor,
the shift from the L level to the H level is defined as "pull-up"
and the shift from the H level to the L level is defined as
"pull-down", whereas in the circuit using the P-type transistor,
the shift from the H level to the L level is defined as "pull-up"
and the shift from the L level to the H level is defined as
"pull-down".
[0068] Moreover, in this specification, a description is based on
the assumption that "connection" between two elements, between two
nodes, or between one element and one node includes a state
equivalent to substantially direct connection, though the
connection is made through another component (such as an element or
a switch). For example, even in a case where two elements are
connected via a switch, the relationship between the two elements
is described as "connection" if they can function in the same
manner as when they are directly connected to each other.
[0069] In the present invention, clock signals (multi-phase clock
signals) having different phases are used. In the following, for
easy description, a certain interval is provided between an
activation period of one clock signal and an activation period of a
clock signal which is activated next to the one clock signal (for
example, from the time t.sub.1 to the time t.sub.2 in FIG. 8).
However, in the present invention, it suffices that the activation
periods of the respective clock signals do substantially not
overlap one another, and thus the interval may not necessarily be
provided. For example, when the H level corresponds to the
activation level, a fall timing (a shift from the H level to the L
level) of one clock signal may be concurrent with a rise timing (a
shift from the L level to the H level).
Preferred Embodiment 1
[0070] FIG. 1 is a block diagram schematically showing a
configuration of a display device according to the present
invention. FIG. 1 shows an overall configuration of a liquid
crystal display device as a typical example of the display device.
Application of the present invention is not limited to the liquid
crystal display device, and the present invention can be widely
applied to electro-optical devices including a display device which
converts an electrical signal into a light brightness, as
exemplified by an electro-luminescence (EL), an organic EL, a
plasma display, and an electronic paper, and an imaging device
(image sensor) which converts a light intensity into an electrical
signal.
[0071] A liquid crystal display device 100 includes a liquid
crystal array section 10, a gate-line drive circuit (scanning-line
drive circuit) 30, and a source driver 40. A shift register
according to a preferred embodiment of the present invention is
mounted in the gate-line drive circuit 30, which will be clearly
described later.
[0072] The liquid crystal array section 10 includes a plurality of
pixels 15 arranged in lines and columns. Gate lines GL.sub.1,
GL.sub.2 . . . (collectively called "gate lines GL") are arranged
in the respective lines of pixels (hereinafter also referred to as
"pixel lines"). Data lines DL.sub.1, DL.sub.2 . . . (collectively
called "data lines DL") are arranged in the respective columns of
pixels (hereinafter also referred to as "pixel columns"). In FIG.
1, the pixel 15 in the first line and the first column, the pixel
15 in the first line and the second column, and the gate line
GL.sub.1 and the data lines DL.sub.1, DL.sub.2 corresponding to
these pixels 15 are shown as a representative.
[0073] Each pixel 15 has a pixel switching element 16 provided
between the corresponding data line DL and a pixel node Np, and a
capacitor 17 and a liquid crystal display element 18 connected in
parallel with each other between the pixel node Np and a common
electrode node Nc. The liquid crystal orientation in the liquid
crystal display element 18 changes depending on a voltage
difference between the pixel node Np and the common electrode node
Nc. In response to this change, the display brightness of the
liquid crystal display element 18 changes. Thereby, the brightness
of each pixel can be controlled by a display voltage transmitted to
the pixel node Np via the data line DL and the pixel switching
element 16. That is, an intermediate voltage difference located
between the voltage difference corresponding to the maximum
brightness and the voltage difference corresponding to the minimum
brightness is applied to between the pixel node Np and the common
electrode node Nc, thereby obtaining an intermediate brightness.
Accordingly, gradational brightnesses can be obtained by setting
the display voltage in stages.
[0074] The gate-line drive circuit 30 sequentially selects and
drives the gate lines GL, based on a predetermined scanning cycle.
A gate electrode of the pixel switching element 16 is connected to
the corresponding gate line GL. While a particular gate line GL is
selected, the pixel switching element 16 of each of the pixels
connected to this gate line GL is in the conducting state, so that
the pixel node Np is connected to the corresponding data line DL.
Thus, the display voltage transmitted to the pixel node Np is held
by the capacitor 17. In general, the pixel switching element 16 is
configured as a TFT formed on the same insulation substrate (such
as a glass substrate and a resin substrate) as the liquid crystal
display element 18 is formed on.
[0075] The source driver 40 serves to output the display voltage to
the data line DL. The display voltage is set in stages by a display
signal SIG which is an N-bit digital signal. Here, in an example,
it is assumed that the display signal SIG is a 6-bit signal, and
includes display signal bits DB0 to DB5. Based on the 6-bit display
signal SIG, a gradation display in 2.sup.6=64 stages is allowed in
each pixel. Moreover, if one color display unit is formed with
three pixels of R (Red), G (Green), and B (Blue), about 260,000
colors can be displayed.
[0076] As shown in FIG. 1, the source driver 40 includes a shift
register 50, a data latch circuits 52, 54, a gradation voltage
generation circuit 60, a decode circuit 70, and an analog amplifier
80.
[0077] In the display signal SIG, the display signal bits DB0 to
DB5 corresponding to the display brightness of each pixel 15 are
serially generated. That is, the display signal bits DB0 to DB5 at
each timing indicate the display brightness of any one of the
pixels 15 in the liquid crystal array section 10.
[0078] The shift register 50 instructs the data latch circuit 52 to
load the display signal bits DB0 to DB5 at a timing synchronized
with a cycle of switching the setting of the display signal SIG.
The data latch circuit 52 sequentially loads the display signals
SIG which are serially generated, and holds the display signals SIG
for one pixel line.
[0079] A latch signal LT inputted to the data latch circuit 54 is
activated at a timing when the display signals SIG for one pixel
line are loaded in the data latch circuit 52. In response thereto,
the data latch circuit 54 loads the display signals SIG for one
pixel line which are held in the data latch circuit 52.
[0080] The gradation voltage generation circuit 60 includes
sixty-three voltage dividing resistors connected in series with one
another between a high voltage VDH and a low voltage VDL. The
gradation voltage generation circuit 60 generates 64-stage
gradation voltages V1 to V64.
[0081] The decode circuit 70 decodes the display signal SIG held in
the data latch circuit 54, and based on a result of the decoding,
selects a voltage from the gradation voltages V1 to V64 and outputs
the selected voltage to each of decode output nodes Nd.sub.1,
Nd.sub.2 . . . (collectively called "decode output nodes Nd").
[0082] As a result, a display voltage (one of the gradation
voltages V1 to V64) corresponding to each of the display signals
SIG for one pixel line held in the data latch circuit 54 are
outputted to the decode output nodes Nd simultaneously (in
parallel). In FIG. 1, the decode output nodes Nd.sub.1, Nd.sub.2
corresponding to the data lines DL.sub.1, DL.sub.2 of the first and
second columns are shown as a representative.
[0083] The analog amplifier 80 amplifies a current of an analog
voltage corresponding to the display voltage outputted from the
decode circuit 70 to each of the decode output nodes Nd.sub.1,
Nd.sub.2 . . . and outputs it to each of the data lines DL.sub.1,
DL.sub.2 . . . .
[0084] Based on the predetermined scanning cycle, the source driver
40 repeatedly outputs, to the data lines DL, the display voltages
corresponding to a series of display signals SIG on one-pixel-line
basis. The gate-line drive circuit 30 sequentially drives the gate
lines GL.sub.1, GL.sub.2 . . . in synchronization with the scanning
cycle. Thereby, an image display based on the display signals SIG
is made in the liquid crystal array section 10.
[0085] Although in the liquid crystal display device 100
illustrated in FIG. 1, the gate-line drive circuit 30 and the
source driver 40 are integrally configured with the liquid crystal
array section 10, it may also be acceptable that the gate-line
drive circuit 30 and the liquid crystal array section 10 are
integrally configured while the source driver 40 is provided as an
external circuit of the liquid crystal array section 10, or that
the gate-line drive circuit 30 and the source driver 40 are
provided as external circuits of the liquid crystal array section
10.
[0086] FIG. 2 is a block diagram showing a configuration of the
gate-line drive circuit 30. The gate-line drive circuit 30 is
configured as a multi-stage shift register including a plurality of
(n) unit shift registers SR.sub.1, SR.sub.2, SR.sub.3, SR.sub.4, .
. . , SR.sub.n which are cascade-connected with one another (for
convenience of the description, the cascade-connected shift
register circuits SR.sub.1, SR.sub.2 . . . are collectively
referred to as "unit shift registers SR"). Each of the unit shift
registers SR is provided for one pixel line, that is, for one gate
line GL.
[0087] In the gate-line drive circuit 30 according to this
preferred embodiment, all of the unit shift registers SR.sub.2 to
SR.sub.n of the second to n-th (last) stages have the identical
configurations each having an input terminal IN, an output terminal
OUT, a clock terminal CK, and a reset terminal RST. The unit shift
register SR.sub.1 of the first stage (most preceding stage) has two
input terminals, unlike the other stages. That is, the unit shift
register SR.sub.1 has first and second input terminals IN1, IN2,
the output terminal OUT, the clock terminal CK, and the reset
terminal RST.
[0088] The output terminal OUT of each unit shift register SR is
connected to each corresponding gate line GL. Thus, an output
signal G of each unit shift register SR is, as a vertical (or
horizontal) scanning pulse, outputted to the gate line GL.
[0089] A clock generator 31 inputs three-phase clock signals CLK1,
CLK2, CLK3 having different phases (having their activation periods
not overlapping one another), to the unit shift register SR of the
gate-line drive circuit 30. The clock signals CLK1, CLK2, CLK3 are
controlled so as to be sequentially and repeatedly activated (in
the order of CLK1, CLK2, CLK3, CLK1, . . . ) at timings
synchronized with the scanning cycle of the display device (see
FIG. 7).
[0090] As shown in FIG. 2, any one of the clock signals CLK1 to
CLK3 is supplied to the clock terminal CK of each unit shift
register SR.
[0091] More specifically, the clock signal CLK1 is supplied to the
unit shift registers SR.sub.1, SR.sub.4, SR.sub.7 . . . which drive
the gate lines GL.sub.3m-2 of the (3m-2)th line (m is a natural
number; hereinafter the same is true). The clock signal CLK2 is
supplied to the unit shift registers SR.sub.2, SR.sub.S, SR.sub.8 .
. . which drive the gate lines GL.sub.3m-1 of the (3m-1)th line.
The clock signal CLK3 is supplied to the unit shift registers
SR.sub.3, SR.sub.6, SR.sub.9 . . . which drive the gate lines
GL.sub.3m of the (3m)th line. Since the clock signals CLK1, CLK2,
CLK3 are repeatedly activated in this order, the clock terminals CK
of the shift registers SR.sub.1, SR.sub.2, SR.sub.3 . . . are
activated in this order.
[0092] Here, in general, the number of scanning lines of the
display device is not a factor of three. Therefore, in the shift
register controlled by the three-phase clock signals CLK1 to CLK3,
the clock signal supplied to the clock terminal CK of the unit
shift register SR.sub.n of the n-th stage which is the last line is
changed depending on the number of scanning lines of the display
device. In an example shown in FIG. 2, the clock signal CLK1 is
supplied to the clock terminal CK of the unit shift register
SR.sub.n.
[0093] Clock signals inputted respectively to the first and second
input terminals IN1, IN2 of the unit shift register SR.sub.1 of the
first stage have their phases different from each other and also
different from the clock signal CLK1 which is inputted to the clock
terminal CK. Here, the clock signal CLK2 is inputted to the first
input terminal IN1, and the clock signal CLK3 is inputted to the
second input terminal IN2. In the unit shift registers SR of the
second and subsequent stages, inputted to the input terminal IN is
the output signal G of the immediately preceding stage.
[0094] Inputted to the reset terminal RST of each unit shift
register SR is the output signal G of the next stage. However, in
the unit shift register SR.sub.n of the last stage, inputted to the
reset terminal RST is the clock signal CLK2 which will be activated
next to the clock signal CLK1 inputted to the clock terminal
CK.
[0095] In synchronization with the clock signals CLK1 to CLK3, each
unit shift register SR of the gate-line drive circuit 30
time-shifts the output signal G of the immediately preceding stage,
and transmits the resultant signal to the corresponding gate line
GL and the next-stage unit shift register SR. Consequently, the
output signals G of the respective unit shift registers SR are
sequentially activated in the order of G.sub.1, G.sub.2, G.sub.3 .
. . (details of the operation of the unit shift register SR will be
described later). Thus, a series of the unit shift registers SR
functions as a so-called gate line drive unit which sequentially
activates the gate lines GL at timings based on the predetermined
scanning cycle.
[0096] In the conventional gate-line drive circuit 30, in order to
activate the output signal G.sub.1 of the unit shift register
SR.sub.1 of the first stage, a start pulse is supplied from the
outside to the input terminal IN of the unit shift register
SR.sub.1. However, as seen from FIG. 2, no start pulse is supplied
to the unit shift register SR.sub.1 of this preferred
embodiment.
[0097] In the following, a circuit configuration of each unit shift
register SR will be described. Firstly, a configuration of each of
the unit shift registers SR of the second and subsequent stages
will be described. FIG. 3 is a circuit diagram thereof. In the
gate-line drive circuit 30, all the unit shift registers SR.sub.2
to SR.sub.n have substantially identical configurations. Thus, a
configuration of the unit shift register SR.sub.k of the k-th stage
(2.ltoreq.k.ltoreq.n) will be described as a representative. All of
transistors included in this unit shift register SR.sub.k are field
effect transistors of the same conductivity type, and N-type TFTs
are adopted here.
[0098] As shown in FIG. 3, the unit shift register SR.sub.k has not
only the input terminal IN, the output terminal OUT, the clock
terminal CK, and the reset terminal RST which are shown in FIG. 2,
but also a first power supply terminal 51 and a second power supply
terminal S2 to which a low-potential-side power supply potential
(low-side power supply potential) VSS and a high-potential-side
power supply potential (high-side power supply potential) VDD are
supplied, respectively. In the following description, the low-side
power supply potential VSS serves as a reference potential of the
circuit (VSS=0), but in an actual use, the reference potential is
set based on the voltage of data written into a pixel. For example,
the high-side power supply potential VDD is set to 17V, and the
low-side power supply potential VSS is set to -12V.
[0099] An output stage of the unit shift register SR.sub.k includes
a transistor Q1 (output pull-up transistor) which brings the output
signal G.sub.k into the activation level (H level) while the gate
line GL.sub.k is selected, and a transistor Q2 (output pull-down
transistor) which keeps the output signal G.sub.k at the
deactivation level (L level) while the gate line GL.sub.k is not
selected.
[0100] The transistor Q1 is connected between the output terminal
OUT and the clock terminal CK, and activates the output signal
G.sub.k by supplying the clock signal inputted to the clock
terminal CK, to the output terminal OUT. The transistor Q2 is
connected between the output terminal OUT and the first power
supply terminal S1, and keeps the output signal G.sub.k at the
deactivation level by discharging the output terminal OUT into the
potential VSS. Here, a node connected to the gate (control
electrode) of the transistor Q1 is defined as a "node N1", and a
node connected to the gate of the transistor Q2 is defined as a
"node N2".
[0101] A capacitance element C1 (boost capacitance) is connected
between the gate and the source of the transistor Q1 (that is,
between the output terminal OUT and the node N1). This capacitor
element C1 capacitively couples the output terminal OUT with the
node N1 to enhance a boost effect of the node N1 which is involved
in the rise in level of the output terminal OUT.
[0102] A transistor Q3 is connected between the node N1 and the
second power supply terminal S2, and the gate of the transistor Q3
is connected to the input terminal IN. The transistor Q3 functions
so as to charge the node N1 in accordance with the activation of a
signal (input signal) supplied to the input terminal IN.
[0103] A transistor Q4 having its gate connected to the reset
terminal RST is connected between the node N1 and the first power
supply terminal S1. The transistor Q4 functions so as to discharge
the node N1 in accordance with the activation of a signal (reset
signal) supplied to the reset terminal RST. A transistor Q5 having
its gate connected to the node N2 is also connected between the
node N1 and the first power supply terminal S1. The transistor Q5
functions so as to discharge the node N1 to keep the node N1 at the
deactivation level (L level) while the node N2 is at the activation
level (H level).
[0104] A circuit including these transistors Q3, Q4, Q5 forms a
"pull-up drive circuit" which drives the transistor Q1 (output
pull-up transistor) by charging and discharging the node N1.
[0105] A transistor Q6 having its gate connected to the second
power supply terminal S2 is connected between the node N2 and the
second power supply terminal S2 (that is, the transistor Q6 is
diode-connected). A transistor Q7 having its gate connected to the
node N1 is connected between the node N2 and the first power supply
terminal S1.
[0106] The transistor Q7 is set such that its on-resistance can be
sufficiently small (that is, its drive capability can be high) as
compared with the transistor Q6. Therefore, when the gate (node N1)
of the transistor Q7 is brought into the H level so that the
transistor Q7 is turned on, the node N2 is discharged to the L
level, whereas when the node N1 is brought into the L level so that
the transistor Q7 is turned off, the node N2 is brought into the H
level. That is, the transistors Q6, Q7 form a ratio-type inverter
whose input and output ends are the nodes N1 and N2, respectively.
In this inverter, the transistor Q6 functions as a load element,
and the transistor Q7 functions as a drive element.
[0107] This inverter forms a "pull-down drive circuit" which drives
the transistor Q2 (output pull-down transistor) by charging and
discharging the node N2.
[0108] Next, a configuration of the unit shift register SR) will be
described. FIG. 4 is a circuit diagram thereof. As shown in FIG. 4,
the unit shift register SR.sub.1 is obtained by replacing the
transistor Q3 included in the circuit of FIG. 3 with two
transistors Q31, Q32 (charge circuit) connected in series with each
other. A node connected between the transistors Q31, Q32 is defined
as a "node N3".
[0109] The transistor Q31 is connected between the second power
supply terminal S2 and the node N3, and the gate thereof is
connected to the first input terminal IN1. The transistor Q32 is
connected between the node N1 and the node N3, and the gate thereof
is connected to the second input terminal IN2. The other parts of
the circuit configuration of the unit shift register SR.sub.1 are
the same as those of the unit shift register SR.sub.k of FIG.
3.
[0110] FIGS. 5 and 6 are diagrams showing a specific circuit
configuration of the gate-line drive circuit 30. FIG. 5 shows the
relationship of connection of the unit shift registers SR.sub.1,
SR.sub.2 of the most preceding two stages. FIG. 6 shows the
relationship of connection of the unit shift registers SR.sub.n-1,
SR.sub.n of the last two stages.
[0111] Next, an operation of the unit shift register SR.sub.k of
FIG. 3 will be described. FIG. 7 is a signal waveform diagram
showing the operation. Here, the description will be given based on
the assumption that the clock signal CLK1 is inputted to the clock
terminal CK of the unit shift register SR.sub.k (for example, the
unit shift register SR.sub.4 of FIG. 2 correspond thereto).
[0112] For an easy description, if not otherwise specified, the
following description is based on the assumption that: the H-level
potentials of the clock signals CLK1 to CLK3 are equal to the
high-side power supply potential VDD; the L-level potentials of the
clock signals CLK1 to CLK3 are equal to the low-side power supply
potential VSS, and this potential is 0V (VSS=0); and all of the
threshold voltages of the respective transistors are equal, and the
value thereof is Vth. The clock signals CLK1 to CLK3 are repetitive
signals phase-shifted from one another by one horizontal period
(1H).
[0113] Firstly, it is assumed that in an initial state of the unit
shift register SR.sub.k, the node N1 is at the L level and the node
N2 is at the H level. At this time, the transistor Q1 is OFF (in a
blocked state), and the transistor Q2 is ON (in the conducting
state). Therefore, the output terminal OUT (output signal G.sub.k)
is kept at the L level, irrespective of the level of the clock
terminal CK (clock signal CLK1) (hereinafter, this state will be
referred to as a "reset state"). That is, the gate line GLk to
which the unit shift register SR.sub.k is connected is in an
unselected state. It is assumed that in the initial state, the
clock signals CLK1 to CLK3, and the output signal G.sub.k-1 of its
immediately preceding stage (unit shift register SR.sub.k-1) are
all at the L level.
[0114] When, from this state, the output signal G.sub.k-1 of the
immediately preceding stage is brought into the H level along with
the rise of the clock signal CLK3 at the time t.sub.100, the
transistor Q3 of this unit shift register SR.sub.k is turned ON. At
this time, the node N2 is at the H level, and thus the transistor
Q5 is ON. Since the transistor Q3 has its on-resistance
sufficiently small (the drive capability is sufficiently high) as
compared with the transistor Q5, the level of the node N1
rises.
[0115] Thereby, the transistor Q7 starts conducting, and the level
of the node N2 drops. This increases a resistance value of the
transistor Q5, and therefore the level of the node N1 rapidly
rises, so that the transistor Q7 becomes sufficiently ON. As a
result, the node N2 becomes the L level (VSS). Accordingly, the
transistor Q5 is turned OFF, to bring the node N1 into the H level
(VDD-Vth).
[0116] When the node N1 becomes the H level and the node N2 becomes
the L level in this manner, the transistor Q1 is turned ON and the
transistor Q2 is turned OFF (hereinafter, this state will be
referred to as a "set state". However, at this time point, the
clock signal CLK1 is at the L level, and therefore the output
signal G.sub.k is kept at the L level.
[0117] When, at the time t.sub.101, the output signal G.sub.k-1 of
the immediately preceding stage returns to the L level along with
the fall of the clock signal CLK3, the transistor Q3 is turned OFF.
However, the transistors Q4, Q5 are also in the OFF state, and
therefore the node N1 is kept at the H level in a high impedance
state (floating state).
[0118] Then, when the clock signal CLK1 rises to the H level at the
time t.sub.102, the rise of the level is transmitted to the output
terminal OUT through the ON-state transistor Q1, so that the level
of the output signal G.sub.k rises. At this time, because of the
coupling through the capacitance element C1 and a gate capacitance
(a capacitance between the gate and the source, a capacitance
between the gate and the drain, and a capacitance between the gate
and the channel) of the transistor Q1, the potential of the node N1
is boosted in accordance with the rise of the level of the output
signal G.sub.k. Therefore, even when the level of the output
terminal OUT rises, the voltage between the gate and the source of
the transistor Q1 is kept higher than the threshold voltage (Vth),
and the transistor Q1 is kept at a low impedance.
[0119] Accordingly, the output signal G.sub.k quickly becomes the H
level following the rise of the clock signal CLK. At this time, the
transistor Q1 is operated in a non-saturated region to charge the
output terminal OUT. Therefore, the level of the output signal
G.sub.k rises to the same potential VDD as that of the clock signal
CLK1, not involving a loss corresponding to the threshold voltage
of the transistor Q1.
[0120] In this manner, when the output signal G.sub.k becomes the H
level, the gate line GLk is in a selected state. Since the output
signal G.sub.k is supplied also to the input terminal IN of the
next-stage unit shift register SR.sub.k+1, the next-stage unit
shift register SR.sub.k+1 is brought into the set state.
[0121] Then, when the clock signal CLK1 falls and returns to the L
level at the time t.sub.103, the output terminal OUT is discharged
by the ON-state transistor Q1. Thus, the output signal G.sub.k
becomes the L level (VSS) and the gate line GL.sub.k returns to the
unselected state. At this time, the node N1 returns to the
pre-boosting potential (VDD-Vth).
[0122] Then, when the clock signal CLK2 rises to the H level at the
time t.sub.104, the next-stage output signal G.sub.k+1 becomes the
H level. Thus, in the unit shift register SR.sub.k, the transistor
Q4 is turned ON to bring the node N1 into the L level. Accordingly,
the transistor Q7 is turned OFF, to bring the node N2 into the H
level. That is, the unit shift register SR.sub.k returns to the
reset state in which the transistor Q1 is OFF and the transistor Q2
is ON. At this time, the transistor Q5 is turned ON.
[0123] When the next-stage output signal G.sub.k+1 falls at the
time t.sub.105, the transistor Q4 is turned OFF. However, the
transistor Q5 is kept ON, and therefore the node N1 is kept at the
L level with a low impedance.
[0124] After the time t.sub.105, until the output signal G.sub.k-1
of the immediately preceding stage is activated in the next frame
period, a half latch circuit including the transistors Q5 to Q7
keeps the node N1 at the L level and the node N2 at the H level, so
that the unit shift register SR.sub.k is kept in the reset state.
Therefore, while the gate line GL.sub.k is not selected, the output
signal G.sub.k is kept at the L level with a low impedance.
[0125] As described above, the second or subsequent unit shift
register SR.sub.k is brought into the set state in accordance with
activation of the signal (the output signal G.sub.k-1 of the
immediately preceding stage) of the input terminal IN, and
activates the output signal G.sub.k in an activation period of the
signal (clock signal CLK1) of the next clock terminal CK. Then, the
unit shift register SR.sub.k returns to the reset state in
accordance with activation of the signal (the next-stage output
signal G.sub.k+1 (the clock signal CLK2 in the unit shift register
SR.sub.n)) of the reset terminal RST, and subsequently keeps the
output signal G.sub.k at the L level.
[0126] Next, an operation of the unit shift register SR.sub.1 of
the first stage shown in FIG. 4 will be described. FIG. 8 is a
signal waveform diagram showing the operation. As described above,
in the unit shift register SR.sub.1, the clock signal CLK1 is
inputted to the clock terminal CK, the clock signal CLK2 is
inputted to the first input terminal IN1, and the clock signal CLK3
is inputted to the input terminal IN3.
[0127] During a normal operation of the gate-line drive circuit 30,
the clock signal generator 31 makes such a control that the
activation periods of the clock signals CLK1 to CLK3 cannot overlap
each other. However, at a timing when a shift operation is started
on a signal of the gate-line drive circuit 30, in other words, at a
timing corresponding to the beginning of a frame period, the clock
signals CLK2, CLK3 are exceptionally activated simultaneously.
[0128] Firstly, the reset state in which the node N1 is at the L
level and the node N2 is at the H level is assumed as an initial
state of the unit shift register SR.sub.1. At this time, the
transistor Q1 is OFF and the transistor Q2 is ON. Therefore, the
output terminal OUT (output signal G.sub.1) is kept at the L level
irrespective of the level of the clock terminal CK (clock signal
CLK1). It is also assumed that the clock signals CLK1 to CLK3 are
all at the L level in the initial state. Thus, both of the
transistors Q31, Q32 are OFF, and the level of the node N3 is not
steady.
[0129] At the time t.sub.0 corresponding to the beginning of the
frame period, both of the clock signals CLK2, CLK3 are activated.
This causes both of the transistors Q31, Q32 to be turned ON. At
this time, the node N2 is at the H level, and therefore the
transistor Q5 is also ON. Here, since the total on-resistance of
the transistors Q31, Q32 is set sufficiently smaller than the
on-resistance of the transistor Q5. Therefore, the node N1 is at
the H level. Accordingly, the transistor Q7 is turned ON, and the
node N2 is at the L level (VSS). At this time, the transistor Q5 is
OFF, to cause the potential of the node N1 to rise to VDD-Vth.
[0130] As a result, the unit shift register SR.sub.1 is brought
into the set state in which the node N1 is at the H level and the
node N2 is at the L level, so that the transistor Q1 is turned ON
and the transistor Q2 is turned OFF. However, at this time point,
the clock signal CLK1 is at the L level, and therefore the output
signal G.sub.1 is kept at the L level.
[0131] Subsequently, at the time t.sub.1, the clock signals CLK2,
CLK3 return to the L level. Accordingly, the transistors Q31, Q32
are turned OFF. Here, the transistors Q4, Q5 are also in the OFF
state, and thus the node N1 is kept at the H level with a high
impedance. The node N3 is also at the H level (VDD-Vth) with a high
impedance.
[0132] When the clock signal CLK1 becomes the H level at the time
t.sub.2, the rise of the level is transmitted to the output
terminal OUT through the ON-state transistor Q1, so that to bring
the output signal G.sub.1 into the H level. At this time, because
of the coupling through the capacitance element C1 and a gate
capacitance (a capacitance between the gate and the source, a
capacitance between the gate and the drain, and a capacitance
between the gate and the channel) of the transistor Q1, the
potential of the node N1 is boosted, and the transistor Q1 is kept
at a low impedance. Accordingly, following the rise of the clock
signal CLK, the output signal G.sub.1 is quickly brought into the H
level. At this time, the transistor Q1 is operated in a
non-saturated region, so that the H-level potential of the output
signal G.sub.1 is VDD.
[0133] In this manner, when the output signal G.sub.1 becomes the H
level, the gate line GL.sub.1 is selected. Since the output signal
G.sub.1 is supplied to the input terminal IN of the second-stage
unit shift register SR.sub.2, the unit shift register SR.sub.2 is
brought into the set state. Then, when the clock signal CLK1
returns to the L level at the time t.sub.3, the output terminal OUT
is discharged by the ON-state transistor Q1. This brings the output
signal G.sub.1 into the L level (VSS), and the gate line GL.sub.1
returns to the unselected state. At this time, the node N1 returns
to the pre-boosting potential (VDD-Vth).
[0134] When the clock signal CLK2 becomes the H level at the time
t.sub.4, the second-stage output signal G.sub.2 is brought into the
H level. This causes the transistor Q4 to be turned ON in the unit
shift register SR.sub.1. At this time, the gate of the transistor
Q31 becomes the H level (VDD). However, the transistor Q32 is OFF,
and therefore a current does not flow to the node N1 through the
transistors Q31, Q32. Thus, the node N1 is at the L level.
Accordingly, the transistor Q7 is turned OFF, to bring the node N2
into the H level. That is, the unit shift register SR.sub.1 returns
to the reset state in which the transistor Q1 is OFF and the
transistor Q2 is ON. At this time, the transistor Q5 is turned
ON.
[0135] When the second-stage output signal G.sub.2 falls with the
clock signal CLK2 at the time t.sub.5, the transistor Q4 is turned
OFF. However, the transistor Q5 is kept ON, and therefore the node
N1 is kept at the L level with a low impedance. The node N3 remains
at the H level (VDD-Vth) with a high impedance at the time t.sub.5,
but when the clock signal CLK3 becomes the H level at the time
t.sub.6, the node N3 is discharged through the transistors Q32, Q5
into the L level (VSS).
[0136] After the time t.sub.6, until both of the clock signals
CLK2, CLK3 are activated at the beginning of the next frame period,
the half latch circuit including the transistors Q5 to Q7 keeps the
node N1 at the L level and the node N2 at the H level, so that the
unit shift register SR.sub.1 is kept in the reset state. Therefore,
while the gate line GL.sub.1; is not selected, the output signal
G.sub.k is kept at the L level with a low impedance. Thus, while
the gate line GL.sub.1 is not selected, the output signal G.sub.1
is kept at the L level with a low impedance.
[0137] As described above, except the operation at a time of
shifting to the set state, the operation of the unit shift register
SR.sub.1 is the same as the operation of the second or subsequent
unit shift register SR.sub.k described above. That is, the unit
shift register SR.sub.1 is brought into the set state in accordance
with simultaneous activation of the signals (clock signals CLK2,
CLK3) of the first and second input terminals IN1, 1N2, and
activates the output signal G.sub.1 in the activation period of the
signal (clock signal CLK1) of the next clock terminal CK. Then, the
unit shift register SR.sub.1 returns to the reset state in
accordance with activation of the signal (the second-stage output
signal G.sub.2) of the reset terminal RST, and subsequently keeps
the output signal G.sub.1 at the L level.
[0138] In this manner, the unit shift register SR.sub.1 can
activate the output signal G.sub.1 by overlapping the activation
periods of the clock signals CLK2, CLK3, without using a start
pulse.
[0139] Accordingly, in the gate-line drive circuit 30 in which the
unit shift registers SR.sub.1 to SR.sub.n are cascade-connected
with one another, as shown in FIG. 9, triggered by simultaneous
activation of the clock signals CLK2, CLK3, the output signals
G.sub.1, G.sub.2, G.sub.3, . . . G.sub.n are sequentially activated
at timings synchronized with the clock signals CLK1 to CLK3.
Thereby, the gate-line drive circuit 30 can sequentially drive the
gate lines GL.sub.1, GL.sub.2, GL.sub.3, . . . in a predetermined
scanning cycle. In the gate-line drive circuit 30 of this preferred
embodiment, since a start pulse generation circuit is not required,
the area of the substrate can be reduced, which contributes to a
reduction in the manufacturing cost.
[0140] The times t.sub.0 to t.sub.6 of FIG. 9 correspond to those
shown in FIG. 8, respectively. The time t.sub.7 of FIG. 9 indicates
the time of expiration of the activation period of the output
signal G.sub.n of the last stage (unit shift register SR.sub.n). A
time period from the time t.sub.7 to the time t.sub.0 of the next
frame is a "blanking period". A time period from the time t.sub.8
to the time t.sub.9 indicates the activation period of the clock
signal CLK2 following the time t.sub.7. In this preferred
embodiment, the clock signal CLK2 is inputted to the reset terminal
RST of the unit shift register SR.sub.n. Therefore, at the time
t.sub.8, the unit shift register SR.sub.n shifts from the set state
to the reset state.
[0141] In this manner, in this preferred embodiment, the unit shift
register SR.sub.n is brought into the reset state by using the
clock signal CLK2. However, for example, a dummy unit shift
register may be provided in the further next-stage of the unit
shift register SR.sub.n, and its output signal (whose activation
period is from the time t.sub.8 to the time t.sub.9) may be
supplied to the reset terminal RST of the unit shift register
SR.sub.n.
[0142] In an example shown in this preferred embodiment, the unit
shift register SR.sub.k is operated by using the three-phase clock
signals CLK1 to CLK3. However, the unit shift register SR.sub.k can
also be operated by using clock signals of four or more phases.
[0143] [Modification]
[0144] Here, a modification of the unit shift register SR.sub.1 of
the first stage will be shown.
[0145] In the unit shift register SR.sub.1 of FIG. 3, the clock
signal CLK2 and the clock signal CLK3 are inputted to the first
input terminal IN1 (the gate of the transistor Q31) and the second
input terminal IN2 (the gate of the transistor Q32), respectively.
However, as shown in FIG. 10A, they may be exchanged so that the
clock signal CLK3 and the clock signal CLK2 are inputted to the
first input terminal IN1 and the second input terminal IN2,
respectively. In this case, a timing of discharging the node N3 is
the time t.sub.4 of FIG. 8. This difference does not influence the
operation of the unit shift register SR.sub.1 activating the output
signal G.sub.1.
[0146] In the unit shift register SR.sub.1 of FIG. 4, the drain of
the transistor Q31 is connected to the second power supply terminal
S2. However, as shown in FIG. 10B, the drain of the transistor Q31
may be connected to the first input terminal IN1 (that is, the
transistor Q31 may be diode-connected). The drain of the transistor
Q31 may be connected to the second input terminal IN2, though not
shown.
[0147] The transistors Q31, Q32 of the unit shift register SR.sub.1
of FIG. 4 may be replaced with a single transistor Q3 shown in FIG.
10C. The transistor Q3 is connected between the node N1 and the
second input terminal IN2 (clock signal CLK3), and the gate thereof
is connected to the first input terminal IN1 (clock signal
CLK2).
[0148] In this case, however, it is necessary that, after both of
the clock signals CLK2, CLK3 are activated to charge the node N1 of
the unit shift register SR.sub.1, the clock signal CLK3 is
deactivated simultaneously with or later than the clock signal
CLK2. This is because if the clock signal CLK3 reaches the
deactivation level earlier than the clock signal CLK2, the node N1
is discharged through the transistor Q3.
[0149] In the transistor Q3 of FIG. 10C, the clock signals CLK2,
CLK3 may be exchanged. In this case, after both of the clock
signals CLK2, CLK3 are activated to charge the node N1 of the unit
shift register SR.sub.1, the clock signal CLK2 is deactivated
simultaneously or later than the clock signal CLK3.
Preferred Embodiment 2
[0150] In a preferred embodiment 2, the present invention is
applied to a shift register in which a signal shift direction is
changeable. The gate-line drive circuit 30 configured with such a
shift register is capable of bi-directional scanning. Here, an
operation for shifting a signal in a direction from the immediately
preceding stage to the subsequent stage (in the order of unit shift
registers SR.sub.1, SR.sub.2, SR.sub.3, . . . ) is defined as a
"forward-direction shift", and an operation for shifting a signal
in a direction from the subsequent stage to the immediately
preceding stage (in the order of unit shift registers SR.sub.n,
SR.sub.n-1, SR.sub.n-2, . . . ) is defined as a "reverse-direction
shift".
[0151] FIG. 11 is a block diagram showing a configuration of the
gate-line drive circuit 30 according to the preferred embodiment 2.
This gate-line drive circuit 30 includes the unit shift registers
(bi-directional unit shift registers) SR.sub.1, SR.sub.2, SR.sub.3,
. . . SR.sub.n capable of bi-directional shifting, a dummy unit
shift register SRDn (hereinafter referred to as a
"forward-direction dummy stage") provided in the further next stage
of the last stage (unit shift register SR.sub.n), and a dummy unit
shift register SRDr (hereinafter referred to as a
"reverse-direction dummy stage") provided in the further
immediately preceding stage of the most preceding stage (unit shift
register SR.sub.1).
[0152] A voltage signal generator 32 generates a first voltage
signal Vn and a second voltage signal Vr which define a signal
shift direction (scanning direction of the gate line GL) in the
gate-line drive circuit 30. The first voltage signal Vn and the
second voltage signal Vr are signals complementary to each other.
When the gate-line drive circuit 30 performs the forward-direction
shift (hereinafter simply referred to as a "time of the
forward-direction shift"), the first voltage signal Vn and the
second voltage signal Vr are set at the H level and the L level,
respectively. When the gate-line drive circuit 30 performs the
reverse-direction shift (hereinafter simply referred to as a "time
of the reverse-direction shift"), the second voltage signal Vr and
the first voltage signal Vn are set at the H level and the L level,
respectively.
[0153] The clock signal generator 31 outputs the clock signals
CLK1, CLK2, CLK3 which are three-phase clock signals having
different phases, and changes the order of bringing the clock
signals CLK1, CLK2, CLK3 into the H level, in accordance with the
signal shift direction. For example, the clock signals are brought
into the H level in the order of CLK1, CLK2, CLK3, CLK1, . . . at
the time of the forward-direction shift, and brought into the H
level in the order of CLK3, CLK2, CLK1, CLK3, . . . at the time of
the reverse-direction shift.
[0154] The signal supplied to the clock terminal CK of each unit
shift register SR is basically the same as shown in FIG. 2. More
specifically, the clock signal CLK1 is supplied to the unit shift
registers SR.sub.1, SR.sub.4, SR.sub.7 . . . which drive the gate
lines GL.sub.3m-2 of the (3m-2)th stage. The clock signal CLK2 is
supplied to the unit shift registers SR.sub.2, SR.sub.5, SR.sub.8 .
. . which drive the gate lines GL.sub.3m-1 of the (3m-1)th stage.
The clock signal CLK3 is supplied to the unit shift registers
SR.sub.3, SR.sub.6, SR.sub.9 . . . which drive the gate lines
GL.sub.3m of the (3m)th stage.
[0155] In this preferred embodiment, all the unit shift registers
SR of the second to the (n-1)th stages have identical circuit
configurations. However, the unit shift register SR.sub.1 of the
most preceding stage, the unit shift register SR.sub.n of the last
stage, the forward-direction dummy stage SRDn, and the
reverse-direction dummy stage SRDr have circuit configurations
different from one another.
[0156] FIG. 12 is a circuit diagram of the unit shift registers
SR.sub.k of the second to the (n-1)th stages. The configuration of
this unit shift register SR.sub.k is almost the same as shown in
FIG. 3, but different therefrom in terms of the following
points.
[0157] That is, the unit shift register SR.sub.k of FIG. 12
includes a forward direction input terminal INn which receives the
output signal G.sub.k-1 of the immediately preceding stage, a
reverse-direction input terminal INr which receives the output
signal G.sub.k+1 of the next stage, and first and second voltage
signal terminals T1, T2 to which the first and second voltage
signals Vn, Vr are supplied, respectively. Additionally, the
transistor Q3 and the transistor Q4 are replaced with a transistor
Q3n and a transistor Q3r, respectively. The transistor Q3n has its
gate connected to the forward direction input terminal INn, and is
connected between the node N1 and the first voltage signal terminal
T1. The transistor Q3r has its gate connected to the
reverse-direction input terminal INr, and is connected between the
node N1 and the second voltage signal terminal T2.
[0158] FIG. 13 is a circuit diagram of the unit shift register
SR.sub.1 of the first stage. The unit shift register SR.sub.1 is
different from the circuit of FIG. 12, in terms of the following
points.
[0159] First, in the unit shift register SR.sub.1 of FIG. 13, the
transistor Q3n of FIG. 12 is replaced with two transistors Q31n,
Q32n connected in series with each other. When a connection node
between the transistors Q31n, Q32n is defined as a "node N3n", the
transistor Q31n has its gate connected to a first forward direction
input terminal IN1n, and is connected between the node N3n and the
first voltage signal terminal T1. The transistor Q32n has its gate
connected to a second forward direction input terminal IN2n, and is
connected between the node N3n and the node N1. Similarly to FIG.
3, the unit shift register SR.sub.1 of FIG. 13 includes the
transistor Q4 having its gate connected to the reset terminal RST
and being connected between the node N1 and the first power supply
terminal S1.
[0160] In the unit shift register SR.sub.1, the clock signals CLK2,
CLK3 whose phases are different from each other and also different
of the phase of the clock signal CLK1 inputted to the clock
terminal CK are inputted to the first forward direction input
terminal IN1n and the second forward direction input terminal IN2n,
respectively. Here, the clock signal CLK2 is supplied to the first
forward direction input terminal IN1n, and the clock signal CLK3 is
supplied to the second forward direction input terminal IN2n.
However, they may be exchanged.
[0161] In the unit shift register SR.sub.1, the output signal
G.sub.2 of the unit shift register SR.sub.2 is inputted to the
reverse-direction input terminal INr, and an output signal GDr
(hereinafter referred to as a "reverse-direction dummy signal") of
the reverse-direction dummy stage SRDr is inputted to the reset
terminal RST.
[0162] FIG. 14 is a circuit diagram of the n-th stage unit shift
register SR.sub.n. The unit shift register SR.sub.n is different
from that of FIG. 12, in terms of the following points.
[0163] Firstly, in the unit shift register SR.sub.n of FIG. 14, the
transistor Q3r of FIG. 12 is replaced with two transistors Q31r,
Q32r connected in series with each other. When a connection node
between the transistors Q31r, Q32r is defined as a "node N3r", the
transistor Q31r has its gate connected to the first
reverse-direction input terminal IN1r, and is connected between the
node N3r and the second voltage signal terminal T2. The transistor
Q32r has its gate connected to the second reverse-direction input
terminal IN2r, and is connected between the node N3r and the node
N1. Similarly to FIG. 3, the unit shift register SR.sub.n of FIG.
14 includes the transistor Q4 having its gate connected to the
reset terminal RST and being connected between the node N1 and the
first power supply terminal S1.
[0164] In the unit shift register SR.sub.n, the clock signals CLK2,
CLK3 whose phases are different from each other and also different
from the phase of the clock signal CLK1 inputted to the clock
terminal CK is inputted to the first reverse-direction input
terminal IN1r and the second reverse-direction input terminal IN2r.
Here, the clock signal CLK2 is supplied to the first
reverse-direction input terminal IN1r, and the clock signal CLK3 is
supplied to the second reverse-direction input terminal IN2r.
However, they may be exchanged.
[0165] In the unit shift register SR.sub.n, the output signal
G.sub.n-1 of the unit shift register SR.sub.n-1 is inputted to the
forward direction input terminal INn, and an output signal GDn
(hereinafter referred to as a "forward-direction dummy signal") of
the forward-direction dummy stage SRDn is inputted to the reset
terminal RST.
[0166] FIG. 15 is a circuit diagram of the forward-direction dummy
stage SRDn. The forward-direction dummy stage SRDn is different
from the circuit of FIG. 12, in that the transistor Q3r is removed
and that the transistor Q4 having its gate connected to the reset
terminal RST and being connected between the node N1 and the first
power supply terminal S1 is provided. In the forward-direction
dummy stage SRDn, the output signal G.sub.n of the unit shift
register SR.sub.n is inputted to the forward direction input
terminal INn, the clock signal CLK2 is inputted to the clock
terminal CK, and the clock signal CLK3 is inputted to the reset
terminal RST.
[0167] FIG. 16 is a circuit diagram of the reverse-direction dummy
stage SRDr. The reverse-direction dummy stage SRDr is different
from the circuit of FIG. 12, in that the transistor Q3n is removed
and that the transistor Q4 having its gate connected to the reset
terminal RST and being connected between the node N1 and the first
power supply terminal S1 is provided. In the reverse-direction
dummy stage SRDr, the output signal G.sub.1 of the unit shift
register SR.sub.1 is inputted to the reverse-direction input
terminal INr, the clock signal CLK3 is inputted to the clock
terminal CK, and the clock signal CLK2 is inputted to the reset
terminal RST.
[0168] FIGS. 17 and 18 show a specific circuit configuration of the
gate-line drive circuit 30. FIG. 17 shows the relationship of
connection among the reverse-direction dummy stage SRDr and the
unit shift registers SR.sub.1, SR.sub.2 which are the most
preceding two stages. FIG. 18 shows the relationship of connection
among the unit shift registers SR.sub.n-1, SR.sub.n which are last
two stages and the forward-direction dummy stage SRDn.
[0169] An operation of the gate-line drive circuit 30 according to
this preferred embodiment at the time of the forward-direction
shift will be described. In a case where the gate-line drive
circuit 30 performs the forward-direction shift, the voltage signal
generator 32 sets the first voltage signal Vn at the H level and
the second voltage signal Vr at the L level, respectively.
[0170] Thus, in the unit shift register SR.sub.k
(2.ltoreq.k.ltoreq.n-1) of FIG. 12, the transistor Q3n is
equivalent to the transistor Q3 of FIG. 3, and the transistor Q3r
is equivalent to the transistor Q4 of FIG. 3. Therefore, the unit
shift register SR.sub.k of FIG. 12 is equivalent to the circuit of
FIG. 3.
[0171] In the unit shift register SR.sub.1 of FIG. 13, the
transistors Q31n, Q32n are equivalent to the transistors Q31, Q32
of FIG. 4, and the transistor Q3r is equivalent to the transistor
Q4 of FIG. 4. As will be described later, the reverse-direction
dummy signal GDr is not activated at the time of the
forward-direction shift, the transistor Q4 of FIG. 12 is kept OFF.
Therefore, the unit shift register SR.sub.1 of FIG. 13 is
equivalent to the circuit of FIG. 4.
[0172] In the unit shift register SR.sub.n of FIG. 14, the
transistor Q3n is equivalent to the transistor Q3 of FIG. 3, and
the transistor Q4 is equivalent to the transistor Q4 of FIG. 3.
Since the clock signals CLK2, CLK3 have different phases, the
transistors Q31r, Q32r are not simultaneously turned ON, so that no
conducting occurs between the node N1 and the second voltage signal
terminal T2. As will be described later, the clock signals CLK2,
CLK3 are simultaneously brought into the H level at the beginning
of the frame period, and at that time, the transistors Q31r, Q32r
are exceptionally turned ON simultaneously, which however does not
influence the operation of the unit shift register SR.sub.n at the
time of the forward-direction shift. Accordingly, the unit shift
register SR.sub.n of FIG. 14 is equivalent to the circuit of FIG.
3.
[0173] In the forward-direction dummy stage SRDn of FIG. 15, the
transistor Q3n is equivalent to the transistor Q3 of FIG. 3, and
the transistor Q4 is equivalent to the transistor Q4 of FIG. 3.
Therefore, the forward-direction dummy stage SRDn of FIG. 15 is
equivalent to the circuit of FIG. 3.
[0174] In the reverse-direction dummy stage SRDr of FIG. 16, each
of the transistors Q3r, Q4 corresponds to the transistor Q4 of FIG.
3, but nothing corresponds to the transistor Q3 of FIG. 3.
Accordingly, the reverse-direction dummy stage SRDr is always in
the reset state, and the reverse-direction dummy signal GDr is kept
at the deactivation level. Therefore, the reverse-direction dummy
stage SRDr of FIG. 16 is substantially in a resting state.
[0175] In the above-described manner, when the first voltage signal
Vn and the second voltage signal Vr are at the H level and the L
level, respectively, the gate-line drive circuit 30 (FIGS. 11, 17,
and 18) according to this preferred embodiment is equivalent to the
gate-line drive circuit 30 (FIGS. 2, 5, and 6) of the preferred
embodiment 1, and the forward-direction shift operation is
allowed.
[0176] In this preferred embodiment, similarly to the preferred
embodiment 1, no start pulse is used, and instead both of the clock
signals CLK2, CLK3 are activated at the beginning of the frame
period. In the gate-line drive circuit 30, as shown in FIG. 19,
triggered by the simultaneous activation of the clock signals CLK2,
CLK3, the output signals G.sub.1, G.sub.2, G.sub.3, . . . , G.sub.n
are sequentially activated at timings synchronized with the clock
signals CLK1 to CLK3 (since the operation at the time of the
forward-direction shift is the same as in the preferred embodiment
1, a detailed description thereof is omitted). Thereby, the
gate-line drive circuit 30 can sequentially drive the gate lines
GL.sub.1, GL.sub.2, GL.sub.3, GL.sub.n in a predetermined scanning
cycle.
[0177] The times t.sub.0 to t.sub.9 of FIG. 19 correspond to those
shown in FIG. 9, respectively. In this preferred embodiment, the
unit shift register SR.sub.n shifts from the set state to the reset
state in accordance with activation of the forward-direction dummy
signal GDn which is activated next to its output signal G.sub.n
(time t.sub.8).
[0178] Next, an operation of the gate-line drive circuit 30 at the
time of the reverse-direction shift will be described. In a case
where the gate-line drive circuit 30 performs the reverse-direction
shift, the voltage signal generator 32 sets the first voltage
signal Vn and the second voltage signal Vr at the L level and the H
level, respectively.
[0179] In the unit shift register SR.sub.k (2.ltoreq.k.ltoreq.n-1)
of FIG. 12, the functions of the transistors Q3n, Q3r are exchanged
as compared with at the time of the forward-direction shift. In
other words, the transistor Q3r functions so as to charge the node
N1, and the transistor Q3n functions so as to discharge the node
N1. Thus, the unit shift register SR.sub.k of FIG. 12 is brought
into the set state in accordance with activation of the next-stage
output signal G.sub.k+1, and into the reset state in accordance
with activation of the output signal G.sub.k-1 of the immediately
preceding stage.
[0180] In the unit shift register SR.sub.1 of FIG. 13, the
transistor Q3r functions so as to charge the node N1, and the
transistor Q4 functions so as to discharge the node N1. Since the
clock signals CLK2, CLK3 have different phases, the transistors
Q31n, Q32n are not simultaneously turned ON, so that no conducting
occurs between the node N1 and the first voltage signal terminal
T1. As will be described later, the clock signals CLK2, CLK3 are
simultaneously brought into the H level at the beginning of the
frame period, and at that time, the transistors Q31n, Q32n are
exceptionally turned ON simultaneously, which however does not
influence the operation of the unit shift register SR.sub.1 at the
time of reverse-direction shift. Accordingly, the unit shift
register SR.sub.1 of FIG. 13 is brought into the set state in
accordance with activation of the second-stage output signal
G.sub.2, and into the reset state in accordance with activation of
the reverse-direction dummy signal GDr.
[0181] In the unit shift register SR.sub.n of FIG. 14, the
transistors Q31r, Q32r function so as to charge the node N1, and
the transistor Q3n functions so as to discharge the node N1. As
will be described later, since the forward-direction dummy signal
GDn is not activated at the time of reverse-direction shift, the
transistor Q4 of FIG. 14 is kept OFF. Therefore, the unit shift
register SR.sub.n of FIG. 14 is brought into the set state in
accordance with simultaneous activation of the clock signals CLK2,
CLK3, and into the reset state in accordance with activation of the
output signal G.sub.n-1 of the (n-1)th stage.
[0182] In the forward-direction dummy stage SRDn of FIG. 15, each
of the transistors Q3n, Q4 functions so as to discharge the node
N1, but there is no transistor which charges the node N1.
Accordingly, the forward-direction dummy stage SRDn is always in
the reset state, and the forward-direction dummy signal GDn is kept
at the deactivation level. Thus, the forward-direction dummy stage
SRDn of FIG. 15 is substantially in the resting state.
[0183] In the reverse-direction dummy stage SRDr of FIG. 16, the
transistor Q3r functions so as to charge the node N1, and the
transistor Q4 functions so as to discharge the node N1.
Accordingly, the reverse-direction dummy stage SRDr of FIG. 16 is
brought into the set state in accordance with activation of the
output signal G.sub.1 of the first stage, and into the reset state
in accordance with activation of the clock signal CLK2.
[0184] As a result, the gate-line drive circuit 30 (FIGS. 11, 17,
and 18) according to this preferred embodiment is allowed to
perform the reverse-direction shift operation. An operation of the
gate-line drive circuit 30 at the time of the reverse-direction
shift will be described with reference to FIG. 20.
[0185] At the time of the reverse-direction shift as well, both of
the clock signals CLK2, CLK3 are activated at the beginning of each
frame period (times t.sub.10 to t.sub.11). Thereby, the unit shift
register SR.sub.n of the last stage is brought into the set state.
Accordingly, next time the clock signal CLK1 is activated, the
output signal G.sub.n of the last stage is activated (times
t.sub.12 to t.sub.13). At this time, the unit shift register
SR.sub.n-1 is brought into the set state. Therefore, next time the
clock signal CLK3 is activated, the output signal G.sub.n-1 of the
unit shift register SR.sub.-1 is activated (times t.sub.14 to
t.sub.15). Subsequently, the output signals G.sub.n-2, G.sub.n-3, .
. . , G.sub.1 are sequentially activated at timings synchronized
with the clock signals CLK1 to CLK3.
[0186] That is, at the time of the reverse-direction shift, as
shown in FIG. 20, triggered by the simultaneous activation of the
clock signals CLK2, CLK3, the gate-line drive circuit 30
sequentially activates the output signals G.sub.n, G.sub.n-1,
G.sub.n-2, G.sub.1 at timings synchronized with the clock signals
CLK1 to CLK3. Thereby, the gate-line drive circuit 30 can
sequentially drive the gate lines GL.sub.n, GL.sub.n-1, GL.sub.n-2,
. . . , GL.sub.1 in a predetermined scanning cycle.
[0187] The time t.sub.17 of FIG. 20 indicates a time at which the
activation period of the output signal G.sub.1 of the most
preceding stage (unit shift register SR.sub.1) expires, and a
period from the time t.sub.17 to the time t.sub.10 of the next
frame is a "blanking period". The reverse-direction dummy signal
GDr outputted by the reverse-direction dummy stage SRDr is
activated when the clock signal CLK3 is activated next to the time
t.sub.17 (times t.sub.18 to t.sub.19), and in accordance therewith,
the unit shift register SR.sub.1 shifts from the set state to the
reset state.
[0188] In this preferred embodiment, in the gate-line drive circuit
30 capable of bi-directional shifting, no start pulse generation
circuit is required. Therefore, the area of the substrate can be
reduced, which can contribute to a reduction in the manufacturing
cost.
[0189] In an example shown in this preferred embodiment, the unit
shift register SR.sub.k is operated by using the three-phase clock
signals CLK1 to CLK3. However, the unit shift register SR.sub.k may
be operated by using clock signals of four or more phases.
[0190] [Modification]
[0191] FIG. 11 shows the gate-line drive circuit 30 including the
dummy unit shift register (the forward-direction dummy stage SRDn
and the reverse-direction dummy stage SRDr). In this modification,
a method in which the dummy unit shift register is not necessary is
shown.
[0192] FIG. 21 is a block diagram of a gate-line drive circuit 30
according to this modification. FIG. 21 is the same as FIG. 11,
except that the forward-direction dummy stage SRDn and the
reverse-direction dummy stage SRDr are removed. Along with the
removal of the forward-direction dummy stage SRDn and the
reverse-direction dummy stage SRDr, the reset terminals RST
included in the unit shift registers SR.sub.1, SR.sub.n of FIG. 11
are also unnecessary.
[0193] In the gate-line drive circuit 30 of this modification, each
of the unit shift registers SR.sub.k of the second to the (n-1)th
stages is the same as the circuit of FIG. 12. A circuit diagram of
the unit shift register SR.sub.1 of the first stage is shown in
FIG. 22. The unit shift register SR.sub.1 is the same as the
circuit of FIG. 13, except that the transistor Q4 is removed. A
circuit diagram of the unit shift register SR.sub.n of the last
stage is shown in FIG. 23. The unit shift register SR.sub.n is the
same as the circuit of FIG. 14, except that the transistor Q4 is
removed.
[0194] FIGS. 24 and 25 show a specific circuit configuration of the
gate-line drive circuit 30. FIG. 24 shows the relationship of
connection between the unit shift registers SR.sub.1, SR.sub.2
which are the most preceding two stages. FIG. 25 show the
relationship of connection between the unit shift registers
SR.sub.n-1, SR.sub.n which are the last two stages.
[0195] FIG. 26 is a timing chart showing an operation of the
gate-line drive circuit 30 according to this modification at the
time of the forward-direction shift. The times t.sub.0 to t.sub.9
of FIG. 26 correspond to those shown in FIG. 19, respectively.
[0196] At the time of the forward-direction shift, the first
voltage signal Vn is set at the H level, and the second voltage
signal Vr is set at the L level. In this case, in the unit shift
register SR.sub.1 (FIG. 22) of the most preceding stage, the
transistors Q3n, Q3r are equivalent to the transistor Q3 of FIG. 4,
and the transistor Q3r is equivalent to the transistor Q4 of FIG.
4. Therefore, this unit shift register SR.sub.1 is equivalent to
the circuit of FIG. 4. The unit shift registers SR.sub.k (FIG. 12)
of the second to the (n-1)th stages are equivalent to the circuit
of FIG. 3. In the unit shift register SR.sub.n (FIG. 23) of the
last stage, the transistor Q3n functions so as to charge the node
N1, and the transistors Q31r, Q32r function so as to discharge the
node N1.
[0197] In this modification as well, both of the clock signals
CLK2, CLK3 are activated at the beginning (times t.sub.0 to
t.sub.1) of the frame period. Triggered by the simultaneous
activation of the clock signals CLK2, CLK3, the gate-line drive
circuit 30 sequentially activates the output signals G.sub.1,
G.sub.2, G.sub.3, . . . , G.sub.n at timings synchronized with the
clock signals CLK1 to CLK3, as shown in FIG. 26. Thereby, the
gate-line drive circuit 30 can sequentially drive the gate lines
GL.sub.1, GL.sub.2, GL.sub.3 . . . in a predetermined scanning
cycle.
[0198] However, in this modification, at the time t.sub.8 after the
activation period of the unit shift register SR.sub.n of the last
stage expires, both of the clock signals CLK2, CLK3 are set at the
H level, and additionally the first voltage signal Vn is set at the
L level.
[0199] When both of the clock signals CLK2, CLK3 are set at the H
level, the transistors Q31r, Q32r are turned ON to discharge the
node N1 in the unit shift register SR.sub.n. Thus, the unit shift
register SR.sub.n shifts from the set state to the reset state.
[0200] On the other hand, in the unit shift register SR.sub.1, the
transistors Q31n, 32n are also turned ON, but the first voltage
signal Vn is set at the L level and therefore the unit shift
register SR.sub.1 is kept in the reset state. When the unit shift
register SR.sub.1 is brought into the set state at the time
t.sub.8, the output signal G.sub.1 is erroneously activated in the
blanking period. In order to prevent this, the first voltage signal
Vn is set at the L level at the time t.sub.8.
[0201] Then, at the time t.sub.9, the clock signals CLK2, CLK3 are
set at the L level, and the first voltage signal Vn is returned to
the H level. At this time, a timing of returning the first voltage
signal Vn to the H level is simultaneous with, or preferably later
than, a timing of bringing the clock signals CLK2, CLK3 into the L
level. If the first voltage signal Vn becomes the H level before
the clock signals CLK2, CLK3 become the L level, the node N1 of the
unit shift register SR.sub.1 is charged by the transistors Q31n,
Q32n and an erroneous operation may be caused. The first voltage
signal Vn may be kept at the L level until the beginning (time
t.sub.0) of the next frame period.
[0202] FIG. 27 is a timing chart showing an operation of the
gate-line drive circuit 30 at the time of reverse-direction shift.
The times t.sub.10 to t.sub.19 of FIG. 27 correspond to those shown
in FIG. 20, respectively.
[0203] At the time of the reverse-direction shift, the first
voltage signal Vn is set at the L level, and the second voltage
signal Vr is set at the H level. In this case, in the unit shift
register SR.sub.1 (FIG. 22) of the most preceding stage, the
transistors Q31n, Q32n function so as to discharge the node N1, and
the transistor Q3r functions so as to charge the node N1. The unit
shift registers SR.sub.k (FIG. 12) of the second to the (n-1)th
stages can perform the reverse-direction shift operation. In the
unit shift register SR.sub.n (FIG. 23) of the last stage, the
transistor Q3n functions so as to discharge the node N1, and the
transistors Q31r, Q32r function so as to charge the node N1.
[0204] In this modification as well, both of the clock signals
CLK2, CLK3 are activated at the beginning (times t.sub.10 to
t.sub.11) of the frame period. Triggered by this, the gate-line
drive circuit 30 sequentially activates the output signals G.sub.n,
G.sub.n-1, G.sub.n-2, . . . , G.sub.1 at timings synchronized with
the clock signals CLK1 to CLK3, as shown in FIG. 27. Thereby, the
gate-line drive circuit 30 can sequentially drive the gate lines
GL.sub.n, GL.sub.n-1, GL.sub.n-1, . . . , GL.sub.1 in a
predetermined scanning cycle.
[0205] At the time of the reverse-direction shift, both of the
clock signals CLK2, CLK3 are set at the H level and the second
voltage signal Vr is set at the L level, at the time t.sub.18 after
the activation period of the unit shift register SR.sub.1 of the
most preceding stage expires.
[0206] Thereby, in the unit shift register SR.sub.1, the
transistors Q31n, Q32n are turned ON to discharge the node N1.
Thus, the unit shift register SR.sub.1 shifts from the set state to
the reset state. At this time, the transistors Q31r, 32r are also
turned ON in the unit shift register SR.sub.n, too. However, the
second voltage signal Vr is set at the L level, and therefore the
unit shift register SR.sub.n is kept at the reset state, so that
occurrence of an erroneous operation is prevented.
[0207] Then, at the time t.sub.19, the clock signals CLK2, CLK3 are
set at the L level, and the second voltage signal Vr is returned to
the H level. A timing of returning the second voltage signal Vr to
the H level is simultaneous with, or preferably later than, a
timing when the clock signals CLK2, CLK3 become the L level. If the
second voltage signal Vr becomes the H level before the clock
signals CLK2, CLK3 become L level, node N1 of the unit shift
register SR.sub.n may be charged by the transistors Q31r, Q32r and
the unit shift register SR.sub.n cannot be kept in the set state.
The second voltage signal Vr may be kept at the L level until the
beginning (time t.sub.10) of the next frame period.
[0208] According to this modification, since it is not necessary to
provide a dummy unit shift register (the forward-direction dummy
stage SRDn and the reverse-direction dummy stage SRDr) in the
gate-line drive circuit 30, the area where the circuit is formed
can be reduced.
Preferred Embodiment 3
[0209] The bi-directional unit shift register shown in FIG. 12 can
also be driven by using two-phase clock signals. However, in the
preferred embodiment 2, the gate-line drive circuit 30 is driven by
using the three-phase clock signals CLK1 to CLK3, because at least
three-phase clock signals are required for controlling the unit
shift register SR.sub.1 of the most preceding stage and the unit
shift register SR.sub.n of the last stage. In this preferred
embodiment, proposed is a gate-line drive circuit 30 capable of
bi-directional shifting which requires no start pulse and can be
operated by using two-phase clock signals.
[0210] FIG. 28 is a block diagram of a gate-line drive circuit
according to a preferred embodiment 3. The clock signal generator
31 of this preferred embodiment generates two-phase clock signals
CLK, /CLK having different phases, and one of them is inputted to
the clock terminal CK of each unit shift register SR. In an example
shown in FIG. 28, the clock signal CLK is inputted to the clock
terminal CK of each of the unit shift registers SR.sub.1, SR.sub.3,
SR.sub.5, . . . , SR.sub.n-1 of the odd-numbered stages, and the
clock signal /CLK is inputted to the clock terminal CK of each of
the unit shift registers SR.sub.2, SR.sub.4, SR.sub.6, . . . ,
SR.sub.n of the even-numbered stages.
[0211] The reverse-direction dummy stage SRDr is provided in the
immediately preceding stage of the unit shift register SR.sub.1,
and the forward-direction dummy stage SRDn is provided in the next
stage of the unit shift register SR.sub.n.
[0212] In the gate-line drive circuit 30 of this modification, each
of the unit shift registers SR.sub.k of the second to the (n-1)th
stages is the same as the circuit of FIG. 12.
[0213] FIG. 29 shows a circuit diagram of the unit shift register
SR.sub.1 of the first stage. The circuit configuration of the unit
shift register SR.sub.1 is almost the same as that of the circuit
of FIG. 13, except that the current electrode of the transistor
Q31n is connected to a third forward direction input terminal IN3n
instead of the first voltage signal terminal T1. The first voltage
signal Vn is inputted to the first forward direction input terminal
IN1n (the gate of the transistor Q31n), and the second voltage
signal Vr is inputted to the second forward direction input
terminal IN2n (the gate of the transistor Q32n). The clock signal
/CLK whose phase is different from the phase of the clock signal
CLK inputted to the clock terminal CK is inputted to the third
forward direction input terminal IN3n.
[0214] The signals inputted to the first forward direction input
terminal IN1n and the second forward direction input terminal IN2n
may be exchanged. In other words, the second voltage signal Vr may
be inputted to the first forward direction input terminal IN1n, and
the first voltage signal Vn may be inputted to the second forward
direction input terminal IN2n.
[0215] FIG. 30 shows a circuit diagram of the unit shift register
SR.sub.n of the last stage. The circuit configuration of this unit
shift register SR.sub.n is almost the same as that of the circuit
of FIG. 14, except that the current electrode of the transistor
Q31r is connected to a third reverse-direction input terminal IN3r
instead of the second voltage signal terminal T2. The first voltage
signal Vn is inputted to the first reverse-direction input terminal
IN1r (the gate of the transistor Q31r), and the second voltage
signal Vr is inputted to the second reverse-direction input
terminal IN2r (the gate of the transistor Q32r). The clock signal
CLK whose phase is different from the phase of the clock signal
/CLK inputted to the clock terminal CK is inputted to the third
reverse-direction input terminal IN3r.
[0216] The signals inputted to the first reverse-direction input
terminal IN1r and the second reverse-direction input terminal IN2r
may be exchanged. In other words, the second voltage signal Vr may
be inputted to the first reverse-direction input terminal IN1r, and
the first voltage signal Vn may be inputted to the second
reverse-direction input terminal IN2r.
[0217] FIG. 31 shows a circuit diagram of the forward-direction
dummy stage SRDn. The circuit configuration of this
forward-direction dummy stage SRDn is almost the same as that of
the circuit of FIG. 15, except that the source of the transistor Q4
is connected to the forward direction input terminal INn. The clock
signal CLK and the clock signal /CLK are inputted to the clock
terminal CK and the reset terminal RST of the forward-direction
dummy stage SRDn, respectively.
[0218] FIG. 32 shows a circuit diagram of the reverse-direction
dummy stage SRDr. The circuit configuration of this
reverse-direction dummy stage SRDr is almost the same as that of
the circuit of FIG. 15, except that the source of the transistor Q4
is connected to the reverse-direction input terminal INr. The clock
signal /CLK and the clock signal CLK are inputted to the clock
terminal CK and the reset terminal RST of the reverse-direction
dummy stage SRDr, respectively.
[0219] FIGS. 33 and 34 show a specific circuit configuration of the
gate-line drive circuit 30. FIG. 33 shows the relationship of
connection among the reverse-direction dummy stage SRDr and the
unit shift registers SR.sub.1, SR.sub.2 which are the most
preceding two stages. FIG. 34 shows the relationship of connection
among the forward-direction dummy stage SRDn and the unit shift
registers SR.sub.n-1, SR.sub.n which are the last two stages.
[0220] FIG. 35 is a timing chart showing an operation at the time
of the forward-direction shift of the gate-line drive circuit 30
according to this modification. The times t.sub.0 to t.sub.9 of
FIG. 35 correspond to those shown in FIG. 19, respectively.
[0221] At the time of the forward-direction shift, the first
voltage signal Vn is set at the H level and the second voltage
signal Vr is set at the L level. When the clock signal /CLK is
activated at the beginning of each frame, both of the first and
second voltage signals Vn, Vr are set at the H level (times t.sub.0
to t.sub.1). Thus, in the unit shift register SR.sub.1, the
transistors Q31n, Q32n are turned ON and the third forward
direction input terminal IN3n is at the H level, and therefore the
node N1 is charged. Accordingly, the unit shift register SR.sub.1
is brought into the set state.
[0222] If the second voltage signal Vr becomes the H level at the
times t.sub.0 to t.sub.1, the second voltage signal terminal T2 of
each of the unit shift registers SR and the reverse-direction dummy
stage SRDr also becomes H level. However, all of the transistors
(Q3r, Q31r) connected thereto are turned OFF. Thus, an operation of
the gate-line drive circuit 30 is not influenced.
[0223] Then, at the time t.sub.1, the second voltage signal Vr is
returned to the L level while the first voltage signal Vn is kept
at the H level. At this time, a timing of returning the second
voltage signal Vr to the L level is simultaneous with, or
preferably later than, a timing when the clock signal /CLK becomes
the L level. This is because if both of the first and second
voltage signals Vn, Vr are at the H level even after the clock
signal /CLK becomes the L level, the node N1 of the unit shift
register SR.sub.1 may be discharged by the transistors Q31n, Q32n
and the unit shift register SR.sub.1 may return to the reset state
before activating the output signal G.sub.1.
[0224] Then, when the clock signal CLK becomes the H level, the
output signal G.sub.1 of the unit shift register SR.sub.1 becomes
the H level (times t.sub.2 to t.sub.3). Subsequently, as shown in
FIG. 35, the output signals G.sub.2, G.sub.3, . . . , G.sub.n are
sequentially activated at timings synchronized with the clock
signals CLK, /CLK. Thereby, the gate-line drive circuit 30 can
sequentially drive the gate lines GL.sub.1, GL.sub.2, GL.sub.3, . .
. , G.sub.n in a predetermined scanning cycle.
[0225] When the output signal G.sub.n of the last stage becomes the
H level, the forward-direction dummy stage SRDn (FIG. 31) is
brought into the set state. Therefore, when the clock signal CLK
becomes the H level next time, the forward-direction dummy signal
GDn becomes the H level (time t.sub.8), thus bringing the unit
shift register SR.sub.n into the reset state.
[0226] In this preferred embodiment, the source of the transistor
Q4 of the forward-direction dummy stage SRDn is connected to the
forward direction input terminal INn. This is for the purpose of
preventing the transistor Q4 from discharging the node N1 when the
transistor Q3n charges the node N1 in accordance with activation of
the output signal G.sub.n of the last stage.
[0227] FIG. 36 is a timing chart showing an operation of the
gate-line drive circuit 30 according to this modification at the
time of the reverse-direction shift. The times t.sub.10 to t.sub.19
of FIG. 36 correspond to those shown in FIG. 20, respectively.
[0228] At the time of the reverse-direction shift, the first
voltage signal Vn is set at the L level, and the second voltage
signal Vr is set at the H level. When the clock signal CLK is
activated at the beginning of each frame, both of the first and
second voltage signals Vn, Vr are set at the H level (times
t.sub.10 to t.sub.11). Thus, in the unit shift register SR.sub.n,
the transistors Q31r, Q32r are turned ON and the third
reverse-direction input terminal IN3r is at the H level, and
therefore the node N1 is charged. Accordingly, the unit shift
register SR.sub.n is brought into the set state.
[0229] If the first voltage signal Vn becomes the H level at the
times t.sub.in to t.sub.11, the first voltage signal terminal T1 of
each of the unit shift registers SR and the forward-direction dummy
stage SRDn also becomes H level. However, all of the transistors
(Q3n, Q31n) connected thereto are turned OFF. Thus, an operation of
the gate-line drive circuit 30 is not influenced.
[0230] Then, at the time t.sub.11, the first voltage signal Vn is
returned to the L level while the second voltage signal Vr is kept
at the H level. At this time, a timing of returning the first
voltage signal Vn to the L level is simultaneous with, or
preferably later than, a timing when the clock signal CLK becomes
the L level. This is because if both of the first and second
voltage signals Vn, Vr are at the H level even after the clock
signal CLK becomes the L level, the node N1 of the unit shift
register SR.sub.n may be discharged by the transistors Q31r, Q32r
and the unit shift register SR.sub.n may return to the reset state
before activating the output signal G.
[0231] Then, when the clock signal /CLK becomes the H level, the
output signal G.sub.n of the unit shift register SR.sub.n becomes
the H level (times t.sub.12 to t.sub.13). Subsequently, as shown in
FIG. 36, the output signals G.sub.n-1, G.sub.n-2, . . . , G.sub.1
are sequentially activated at timings synchronized with the clock
signals CLK, /CLK. Thereby, the gate-line drive circuit 30 can
sequentially drive the gate lines GL.sub.n, GL.sub.n-1, G.sub.n-2,
. . . , GL.sub.1 in a predetermined scanning cycle.
[0232] When the output signal G.sub.1 of the most preceding stage
becomes the H level, the reverse-direction dummy stage SRDr (FIG.
32) is brought into the set state. Therefore, when the clock signal
/CLK becomes the H level next time, the reverse-direction dummy
signal GDr becomes the H level (time t.sub.18), thus bringing the
unit shift register SR.sub.1 into the reset state.
[0233] In this preferred embodiment, the source of the transistor
Q4 of the reverse-direction dummy stage SRDr is connected to the
reverse-direction input terminal INr. This is for the purpose of
preventing the transistor Q4 from discharging the node N1 when the
transistor Q3r charges the node N1 in accordance with activation of
the output signal G.sub.1 of the most preceding stage.
[0234] [Modification]
[0235] In this modification, a method for eliminating the need for
the dummy unit shift register will be shown.
[0236] FIG. 37 is a block diagram of the gate-line drive circuit 30
according to this modification. FIG. 37 is the same as FIG. 28,
except that the forward-direction dummy stage SRDn and the
reverse-direction dummy stage SRDr are not provided. Since the
forward-direction dummy stage SRDn and the reverse-direction dummy
stage SRDr are not provided, the reset terminals RST included in
the unit shift registers SR.sub.1, SR.sub.n of FIG. 28 are no
longer necessary.
[0237] In the gate-line drive circuit 30 of this modification, each
of the unit shift registers SR.sub.k of the second to the (n-1)th
stages is the same as the circuit of FIG. 12. FIG. 38 shows a
circuit diagram of the unit shift register SR.sub.1 of the first
stage. This unit shift register SR.sub.1 is different from the
circuit of FIG. 29 only in that the transistor Q4 is not provided.
FIG. 39 shows a circuit diagram of the unit shift register SR.sub.n
of the last stage. This unit shift register SR.sub.n is different
from the circuit of FIG. 30 only that the transistor Q4 is not
provided.
[0238] FIGS. 40 and 41 show a specific circuit configuration of the
gate-line drive circuit 30. FIG. 40 shows the relationship of
connection between the unit shift registers SR.sub.1, SR.sub.2
which are the most preceding two stages. FIG. 41 show the
relationship of connection between the unit shift registers
SR.sub.n-1, SR.sub.n which are the last two stages.
[0239] FIG. 42 is a timing chart showing an operation of the
gate-line drive circuit 30 according to this modification at the
time of the forward-direction shift. The times t.sub.0 to t.sub.9
of FIG. 42 correspond to those shown in FIG. 35, respectively.
[0240] An operation of the gate-line drive circuit 30 from the time
t.sub.0 to the time t.sub.7 is the same as FIG. 35. That is, in
this modification, too, when the clock signal /CLK is activated at
the beginning (times t.sub.0 to t.sub.1) of the frame period, both
of the first and second voltage signals Vn, Vr are set at the H
level. Triggered by this, the gate-line drive circuit 30
sequentially activates the output signals G.sub.1, G.sub.2,
G.sub.3, . . . , G.sub.n at timings synchronized with the clock
signals CLK, /CLK as shown in FIG. 42. Thereby, the gate-line drive
circuit 30 can sequentially drive the gate lines GL.sub.1,
GL.sub.2, GL.sub.3, . . . , GL.sub.n in a predetermined scanning
cycle.
[0241] However, in this modification, at the time t.sub.8 after the
activation period of the unit shift register SR.sub.n of the last
stage expires, both of the first and second voltage signals Vn, Vr
are set at the H level, and additionally both of the clock signals
CLK, /CLK are set at the L level.
[0242] Thereby, in the unit shift register SR.sub.n, the
transistors Q31r, Q32r are turned ON to discharge the node N1.
Thus, the unit shift register SR.sub.n shifts from the set state to
the reset state. At this time, the transistor Q31n, 32n of the unit
shift register SR.sub.1 are also turned ON, but the third forward
direction input terminal IN3n is set at the L level, and therefore
the unit shift register SR.sub.1 is kept in the reset state.
[0243] FIG. 43 is a timing chart showing an operation of the
gate-line drive circuit 30 according to this modification at the
time of the reverse-direction shift. The times t.sub.10 to t.sub.19
of FIG. 43 correspond to those shown in FIG. 36, respectively.
[0244] An operation of the gate-line drive circuit 30 from the time
t.sub.10 to the time t.sub.17 is the same as FIG. 36. That is, in
this modification, too, when the clock signal CLK is activated at
the beginning (times t.sub.10 to t.sub.11) of the frame period,
both of the first and second voltage signals Vn, Vr are set at the
H level. Triggered by this, the gate-line drive circuit 30
sequentially activates the output signals G.sub.n, G.sub.n-1,
G.sub.n-2, . . . , G.sub.1 at timings synchronized with the clock
signals CLK, /CLK, as shown in FIG. 43. Thereby, the gate-line
drive circuit 30 can sequentially drive the gate lines GL.sub.n,
GL.sub.n-1, GL.sub.n-2, . . . , GL.sub.1 in a predetermined
scanning cycle.
[0245] However, in this modification, at the time t.sub.18 after
the activation period of the unit shift register SR.sub.1 of the
most preceding stage expires, both of the first and second voltage
signals Vn, Vr are set at the H level, and additionally both of the
clock signals CLK, /CLK are set at the L level.
[0246] Thereby, in the unit shift register SR.sub.1, the
transistors Q31n, Q32n are turned ON to discharge the node N1.
Thus, the unit shift register SR.sub.1 shifts from the set state to
the reset state. At this time, the transistors Q31r, 32r of the
unit shift register SR.sub.n are also turned ON, but the third
reverse-direction input terminal IN3r is set at the L level, and
therefore the unit shift register SR.sub.n is kept in the reset
state.
[0247] According to this modification, it is not necessary to
provide the dummy unit shift register (the forward-direction dummy
stage SRDn and the reverse-direction dummy stage SRDr) in the
gate-line drive circuit 30. Therefore, the area where the circuit
is formed can be reduced.
Preferred Embodiment 4
[0248] The preferred embodiments 1 to 3 aim at eliminating the need
for a start pulse generation circuit. However, the circuit of FIG.
4 according to the present invention can also be used as a start
pulse generation circuit. This is because a signal having the same
waveform as that of the output signal G of the unit shift register
SR can be normally used as a start pulse.
[0249] FIG. 44 shows a configuration of the gate-line drive circuit
30 in a case where the circuit of FIG. 4 is used as a start pulse
generation circuit. In FIG. 44, each of the unit shift registers
SR.sub.1 to SR.sub.n which drive the gate lines GL.sub.1 to
GL.sub.n is configured as the circuit of FIG. 3. A start pulse
generation circuit 33 which supplies a start pulse SP to the input
terminal IN of the unit shift register SR.sub.1 is configured as
the circuit of FIG. 4.
[0250] The gate-line drive circuit 30 of FIG. 44 form a multi-stage
shift register including the start pulse generation circuit 33.
That is, in the gate-line drive circuit 30, a unit shift register
serving as the start pulse generation circuit 33 and the unit shift
registers SR1 to SRn which drive the gate lines GL1 to GLn are
dependently connected to one another, thereby forming a multi-stage
shift register. It is not used for driving an output signal (start
pulse SP) gate line GL of the start pulse generation circuit
33.
[0251] The output signal of the circuit of FIG. 4 is, at both of
the H level and the L level, outputted with a low impedance.
Therefore, the start pulse SP with a stable output level can be
obtained.
[0252] This preferred embodiment is effective in using a start
pulse for other applications. For example, when a signal (initial
reset signal) for initializing each unit shift register SR into the
reset state before a normal operation (such as when powered on), a
start pulse can be used as a signal for ending an output of the
initial reset signal in an initial reset signal generation circuit.
Such an initial reset signal generation circuit is described in,
for example, Japanese Patent Application No. 2009-025449 which is a
patent application filed by the present inventor.
[0253] While the invention has been shown and described in detail,
the foregoing description is in all aspects illustrative and not
restrictive. It is therefore understood that numerous modifications
and variations can be devised without departing from the scope of
the invention.
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