U.S. patent application number 13/080948 was filed with the patent office on 2011-11-24 for approximation of stroked higher-order curved segments by quadratic b zier curve segments.
Invention is credited to Mark J. KILGARD, Henry Packard MORETON.
Application Number | 20110285719 13/080948 |
Document ID | / |
Family ID | 44972149 |
Filed Date | 2011-11-24 |
United States Patent
Application |
20110285719 |
Kind Code |
A1 |
KILGARD; Mark J. ; et
al. |
November 24, 2011 |
APPROXIMATION OF STROKED HIGHER-ORDER CURVED SEGMENTS BY QUADRATIC
B ZIER CURVE SEGMENTS
Abstract
One embodiment of the present invention sets forth a technique
for subdividing stroked higher-order curved segments into quadratic
Bezier curve segments. Path stroking may be accelerated when a GPU
or other processor is configured to perform the subdivision
operations. Cubic Bezier path segments are subdivided into
quadratic Bezier curve segments and other lower-order segments at
key features. The quadratic Bezier curve segments approximate the
cubic Bezier path segments. A variance metric is computed for each
quadratic Bezier curve segment, and when the variance metric
indicates that the quadratic Bezier curve segment deviates by more
than a threshold from the corresponding portion of the cubic Bezier
path segment, the quadratic Bezier curve segment is further
subdivided. The path composed of the quadratic Bezier curve
segments is then stroked by rendering hull geometry that encloses
the path.
Inventors: |
KILGARD; Mark J.; (Austin,
TX) ; MORETON; Henry Packard; (Woodside, CA) |
Family ID: |
44972149 |
Appl. No.: |
13/080948 |
Filed: |
April 6, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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61347359 |
May 21, 2010 |
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Current U.S.
Class: |
345/442 |
Current CPC
Class: |
G06T 15/005 20130101;
G06T 11/203 20130101 |
Class at
Publication: |
345/442 |
International
Class: |
G06T 11/20 20060101
G06T011/20 |
Claims
1. A method of approximating cubic Bezier path segments, the method
comprising: receiving a stroke width and a path including a cubic
Bezier path segment; computing a first endpoint position, a second
endpoint position, a first tangent at the first endpoint, and a
second tangent at the second endpoint for the cubic Bezier path
segment fitting an approximating quadratic Bezier curve segment to
the endpoint positions and tangents computed for the cubic Bezier
path segment; determining whether the approximating quadratic
Bezier curve segment is an accurate approximation of the cubic
Bezier path segment based on a variance metric; and stroking an
approximated path including the approximating quadratic Bezier
curve segment to fill a stroke region specified by the stroke width
and the approximated path.
2. The method of claim 1, wherein the stroking of the approximated
path further comprises constructing a bounding hull geometry that
encloses the approximating quadratic Bezier curve segment.
3. The method of claim 2, wherein the stroking of the approximated
path further comprises: rendering the bounding hull geometry;
identifying sample points within the bounding hull geometry that
are inside of a portion of the stroke region of the approximating
quadratic Bezier curve segment; and writing a color buffer to fill
pixels that are inside of the portion of the stroke region of the
approximating quadratic Bezier curve segment.
4. The method of claim 3, wherein the step of identifying sample
points within the bounding hull geometry that are inside of the
portion of the stroke region of the approximating quadratic Bezier
curve segment comprises writing a stencil buffer.
5. The method of claim 1, wherein the variance metric is based on
the deviation between the cubic Bezier path segment and the
approximating quadratic Bezier curve segment.
6. The method of claim 1, further comprising the steps of:
identifying key features of the path; and subdividing the path at
each key feature.
7. The method of claim 6, wherein the key features include one or
more of a cusp point, a point of self-intersection, and a point of
maximum curvature of the path.
8. The method of claim 1, further comprising subdividing the cubic
Bezier path segment into two or more quadratic Bezier curve
segments when the variance metric is not within a tolerance
threshold.
9. The method of claim 1, further comprising the step of fitting a
second approximating quadratic Bezier curve segment to the first
endpoint and a third endpoint while maintaining geometric tangent
continuity with the first tangent.
10. The method of claim 1, further comprising replacing a collinear
cubic Bezier path segment of the path with a line segment.
11. A non-transitory computer-readable storage medium storing
instructions that, when executed by a processor, cause the
processor to approximate cubic Bezier path segments, by performing
the steps of: receiving a stroke width and a path including a cubic
Bezier path segment; computing a first endpoint position, a second
endpoint position, a first tangent at the first endpoint, and a
second tangent at the second endpoint for the cubic Bezier path
segment fitting an approximating quadratic Bezier curve segment to
the endpoint positions and tangents computed for the cubic Bezier
path segment; determining whether the approximating quadratic
Bezier curve segment is an accurate approximation of the cubic
Bezier path segment based on a variance metric; and stroking an
approximated path including the approximating quadratic Bezier
curve segment to fill a stroke region specified by the stroke width
and the approximated path.
12. The non-transitory computer-readable storage medium of claim
11, wherein the stroking of the approximated path further comprises
constructing a bounding hull geometry that encloses the
approximating quadratic Bezier curve segment.
13. The non-transitory computer-readable storage medium of claim
12, wherein the stroking of the approximated path further
comprises: rendering the bounding hull geometry; identifying sample
points within the bounding hull geometry that are inside of a
portion of the stroke region of the approximating quadratic Bezier
curve segment; and writing a color buffer to fill pixels that are
inside of the portion of the stroke region of the approximating
quadratic Bezier curve segment.
14. The non-transitory computer-readable storage medium of claim
13, wherein the step of identifying sample points within the
bounding hull geometry that are inside of the portion of the stroke
region of the approximating quadratic Bezier curve segment
comprises writing a stencil buffer.
15. The non-transitory computer-readable storage medium of claim
11, wherein the variance metric is based on the deviation between
the cubic Bezier path segment and the approximating quadratic
Bezier curve segment.
16. The non-transitory computer-readable storage medium of claim
11, further comprising the steps of: identifying key features of
the path; and subdividing the path at each key feature.
17. The non-transitory computer-readable storage medium of claim
16, wherein the key features include one or more of a cusp point, a
point of self-intersection, and a point of maximum curvature of the
path.
18. The non-transitory computer-readable storage medium of claim
11, further comprising subdividing the cubic Bezier path segment
into two or more quadratic Bezier curve segments when the variance
metric is not within a tolerance threshold.
19. The non-transitory computer-readable storage medium of claim
11, further comprising the step of fitting a second approximating
quadratic Bezier curve segment to the first endpoint and a third
endpoint while maintaining geometric tangent continuity with the
first tangent.
20. A system for approximate cubic Bezier path segments, the system
comprising: a memory that is configured to store a stroke width and
a path including a cubic Bezier path segment; and a processor that
is coupled to the memory and configured to: receive the stroke
width and the path including the cubic Bezier path segment; compute
a first endpoint position, a second endpoint position, a first
tangent at the first endpoint, and a second tangent at the second
endpoint for the cubic Bezier path segment fit an approximating
quadratic Bezier curve segment to the endpoint positions and
tangents computed for the cubic Bezier path segment; determine
whether the approximating quadratic Bezier curve segment is an
accurate approximation of the cubic Bezier path segment based on a
variance metric; and stroke an approximated path including the
approximating quadratic Bezier curve segment to fill a stroke
region specified by the stroke width and the approximated path.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority benefit to United States
provisional patent application titled, "Path Rendering," filed on
May 21, 2010 and having Ser. No. 61/347,359 (Attorney Docket Number
NVDA/SC-10-0110-US0). This related application is also hereby
incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention generally relates to graphics
processing and more specifically to approximation of stroked
higher-order curved segments by quadratic segments.
[0004] 2. Description of the Related Art
[0005] Path rendering is a style of resolution-independent
two-dimensional (2D) rendering, often called "vector graphics,"
that is the basis for a number of important rendering standards
such as PostScript, Java 2D, Apple's Quartz 2D, OpenVG, PDF,
TrueType fonts, OpenType fonts, PostScript fonts, Scalable Vector
Graphics (SVG) web format, Microsoft's Silverlight and Adobe Flash
for interactive web experiences, Open XML Paper Specification
(OpenXPS), drawings in Office file formats including PowerPoint,
Adobe Illustrator illustrations, and more.
[0006] Path rendering is resolution-independent meaning that a
scene is described by paths without regard to the pixel resolution
of the framebuffer. This is in contrast to the resolution-dependent
nature of so-called bitmapped graphics. Whereas bitmapped images
exhibit blurred or pixilated appearance when zoomed or otherwise
transformed, scenes specified with path rendering can be rendered
at different resolutions or otherwise transformed without blurring
the boundaries of filled or stroked paths.
[0007] Sometimes the term vector graphics is used to mean path
rendering, but path rendering is a more specific approach to
computer graphics. While vector graphics could be any computer
graphics approach that represents objects (typically 2D) in a
resolution-independent way, path rendering is a much more specific
rendering model with salient features that include path filling,
path stroking, path masking, compositing, and path segments
specified as Bezier curves.
[0008] FIG. 1A is a prior art scene composed of a sequence of
paths. In path rendering, a 2D picture or scene such as that shown
in FIG. 1A is specified as a sequence of paths. Each path is
specified by a sequence of path commands and a corresponding set of
scalar coordinates. Path rendering is analogous to how an artist
draws with pens and brushes. A path is a collection of sub-paths.
Each sub-path (also called a trajectory) is a connected sequence of
line segments and/or curved segments. Each sub-path may be closed,
meaning the sub-path's start and terminal points are the same
location so the stroke forms a loop; alternatively, a sub-path can
be open, meaning the sub-path's start and terminal points are
distinct.
[0009] When rendering a particular path, the path may be filled,
stroked, or both. As shown in FIG. 1A, the paths constituting the
scene are stroked. When a path is both filled and stroked,
typically the stroking operation is done immediately subsequent to
the filling operation so the stroking outlines the filled region.
Artists tend to use stroking and filling together in this way to
help highlight or offset the filled region so typically the
stroking is done with a different color than the filling.
[0010] FIG. 1B is the sequence of paths shown in FIG. 1A with only
filling. Filling is the process of coloring or painting the set of
pixels "inside" the closed sub-paths of a path. Filling is similar
to the way a child would "color in between the lines" of a coloring
book. If a sub-path within a path is not closed when such a
sub-path is filled, the standard practice is to force the sub-path
closed by connecting its end and start points with an implicit line
segment, thereby closing the sub-path, and then filling that
resulting closed path.
[0011] While the meaning of "inside a path" generally matches the
intuitive meaning of this phrase, path rendering formalizes this
notion with what is called a fill-rule. The intuitive sense of
"inside" is sufficient as long as a closed sub-path does not
self-intersect itself. However if a sub-path intersects itself or
another sub-path or some sub-paths are fully contained within other
sub-paths, what it means to be inside or outside the path needs to
be better specified.
[0012] Stroking is distinct from filling and is more analogous to
tracing or outlining each sub-path in a path as if with a pen or
marker. Stroking operates on the perimeter or boundary defined by
the path whereas filling operates on the path's interior. Unlike
filling, there is no requirement for the sub-paths within a path to
be closed for stroking. For example, the curve of a letter "S"
could be stroked without having to be closed though the curve of
the letter "O" could also be stroked.
[0013] FIG. 1C is a prior art scene composed of the sequence of
paths from FIG. 1A with the stroking from FIG. 1A and the filling
from FIG. 1B. FIG. 1C shows how filling and stroking are typically
combined in a path rendering scene for a complete the scene. Both
stroking and filling are integral to the scene's appearance.
[0014] Traditionally, graphics processing units (GPUs) have
included features to accelerate 2D bitmapped graphics and
three-dimensional (3D) graphics. In today's systems, nearly all
path rendering is performed by a central processing unit (CPU)
performing scan-line rendering with no acceleration by a GPU. GPUs
do not directly render curved primitives so path rendering
primitives such as Bezier segments and partial elliptical arcs must
be approximated by lots of tiny triangles when a GPU is used to
render the paths. Constructing the required tessellations of a path
that is approximated by many short connected line segments can
create a substantial CPU burden. The triangles or other polygons
resulting from tessellation are then rendered by the GPU. Because
GPUs are so fast at rasterizing triangles, tessellating paths into
polygons that can then be rendered by GPUs is an obvious approach
to GPU-accelerating path rendering.
[0015] Tessellation is a fragile, often quite sequential, process
that requires global inspection of the entire path. Tessellation
depends on dynamic data structures to sort, search, and otherwise
juggle the incremental steps involved in generating a tessellation.
Path rendering makes this process considerably harder by permitting
curved path segments as well as allowing path segments to
self-intersect, form high genus topologies, and be unbounded in
size.
[0016] A general problem with using a GPU to render paths is
unacceptably poor antialiasing quality when compared to standard
CPU-based methods. The problem is that GPUs rely on point sampling
for rasterization of triangular primitives with only 1 to 8 samples
(often 4) per pixel. CPU-based scan-line methods typically rely on
16 or more samples per pixel and can accumulate coverage over
horizontal spans.
[0017] Animating or editing paths is costly because it requires
re-tessellating the entire path since the tessellation is
resolution dependent, and in general it is very difficult to prove
a local edit to a path will not cause a global change in the
tessellation of the path. Furthermore, when curved path segments
are present and the scaling of the path with respect to pixel space
changes appreciably (zooming in say), the curved path segments may
need to be re-subdivided and re-tessellation is likely to be
necessary.
[0018] Additionally, compositing in path rendering systems
typically requires that pixels rasterized by a filled or stroked
path are updated once-and-only-once per rasterization of the path.
This requirement means non-overlapping tessellations are required.
So for example, a cross cannot be tessellated as two overlapping
rectangles but rather must be rendered by the outline of the cross,
introducing additional vertices and primitives. In particular, this
means the sub-paths of a path cannot be processed separately
without first determining that no two sub-paths overlap. These
requirements, combined with the generally fragile and sequential
nature of tessellation algorithms make path tessellation
particularly expensive. Because of the expense required in
generating tessellations, it is very tempting and pragmatic to
cache tessellations. Unfortunately such tessellations are much less
compact than the original path representations, particularly when
curved path segments are involved. Consequently, a greater amount
of data must be stored to cache paths after tessellation compared
with storing the paths prior to tessellation.
[0019] Conventional stroking has been performed by approximating
paths into sub-pixel linear segments and then tracing the segments
with a circle having a diameter equal to a stroke width. Offset
curves are generated at the boundary of the stroked path. These
offset curves are typically of much higher degree of complexity
compared with the linear segments that are traced to generate the
stroked path. Determining whether or not each pixel is inside or
outside of a stroked path to generate the stroking is
mathematically complex. Identification of the pixels to be stroked
is equivalent to identifying pixels that are within half of the
stroke width of any point along the path to be stroked. More
specifically, the pixels to be stroked are within half of the
stroke width measured along a line that is perpendicular to the
tangent of the path segment being stroked.
[0020] The tangent of a sub-path is not necessarily well-defined at
junctions between path segments. So additional rules are needed to
determine what happens at and in the vicinity of such junctions as
well as what happens at the terminal (start and end) points of
sub-paths. Therefore stroking specifies further stroking rules to
handle these situations.
[0021] In standard path rendering systems, paths are specified as a
sequence of cubic and quadratic (non-rational) Bezier curve
segments, partial elliptical arcs, and line segments. While more
mathematically complex path segments representations could be used
to specify paths, in practice, existing standards limit themselves
to the aforementioned path segment types.
[0022] Path filling and stroking use the same underlying path
specification. For filling, this means the resulting piece-wise
boundaries to be filled may be up to third-order (in the case of
cubic Bezier segments) or rational second-order (in the case of
partial elliptical arcs). Filling these curved boundaries of Bezier
curves and arcs is clearly harder than filling the standard
polygonal primitives in conventional polygonal 2D or 3D rendering
where the boundaries (edges) of the polygonal primitives (usually
triangles) are all first-order, being linear segments, and often
required to be convex. Filling (and stroking) are also harder than
conventional line and convex polygon rasterization because paths
are unbounded in their complexity whereas line segments and
triangles are defined by just 2 or 3 points respectively. A path
may contain just a single path segment or it could contain
thousands or more.
[0023] The boundaries of stroked paths are actually substantially
higher order than the third-order segments. The offset curve of
non-rational (second-order) quadratic and (third-order) cubic
Bezier curves are eighth- and tenth-order curves respectively. This
high order makes exact determination and evaluation of the
resulting offset curves for such Bezier segments intractable for
use in direct rendering. In other words, it is quite unreasonable
to try to determine exactly the boundary representation of such
offset curves and then simply fill them. For this reason, various
techniques have been developed to approximate offset curves with
sequences of Bezier, arc, or line segments. These approximate
stroke boundaries may then be filled.
[0024] FIG. 1D illustrates prior art exterior stroke offset curves
for various stroke widths of a generating path 200. Observe in FIG.
1D how as the stroke width radius increases, the respective offset
curves 207 for each different stroke width exhibit
self-intersections 222 and cusps 223. The exterior stroke offset
curves are higher-order curves compared with the generating path
200. FIG. 1E illustrates interior stroke offset curves for various
stroke widths of a generating path 221. The interior stroke
bounding curves are higher-order curves compared with the
generating path 221. Observe in FIG. 1E how offset curves with a
small radius leave a topological hole inside the generating path
221. As the radius increases with each wider radius, the hole
splits into two holes. The largest radius shown fills in the hole
completely. These changes in the genus of the region bounded by
offset curves and the emergence of tangent discontinuities on the
boundary of wide offset curves illustrate some of the difficulties
associated with exact rasterization of stroked paths.
[0025] The idea that stroking is "harder" than filling is a bit
unintuitive when filling and stroking are considered on an
intuitive, artistic level. An artist typically thinks of stroking
as a form of sketching or outlining whereas filling requires
"coloring in between the lines." In typical rasterized path
rendering scenes, most of pixels tend to be painted by filling
rather than stroking so there is a sense that more effort is
expended to perform the filling simply because more pixels were
painted by filling.
[0026] This intuition seems to be further validated when one
appreciates that evaluating the fill-rule required for proper
filling requires a global view of the entire path. Just because a
pixel appears to be inscribed within a particular loop of a path
does not mean the pixel should be painted because the path might
contain another loop with the opposite winding order that all
inscribes that pixel. Certainly there are very intricate paths
where determining whether a pixel filled by such an intricate path
is quite involved; however most paths, in practice, are often
reasonably simple (meaning non-self-intersecting and topologically
genus zero).
[0027] However this naive intuition that filling might be easier is
misleading; proper stroking is hard because of the mathematical
complexity of the boundary of a path's stroke compared to a path's
fill. While approximations to the actual stroke boundary can reduce
this complexity, such approximations have associated costs due to
inaccuracy and the resulting expansion in the number of primitives
that must be both stored and processed to render such approximated
strokes. For example, the stroke of a quadratic Bezier segment can
be represented with just the segment's 3 control points (along with
the per-path stroke width) whereas an approximation of this stroked
boundary with line segments might require dozens or even hundreds
of triangles to tessellate approximately the stroked region. Indeed
the quality of such tessellations depends on the projection of the
curved segment to screen-space; this means rendering the same
stroked curve at different resolutions would necessitate different
tessellations.
[0028] Accordingly, what is needed in the art is an improved system
and method for approximating stroked higher-order curved segments
using quadratic segments.
SUMMARY OF THE INVENTION
[0029] One embodiment of the present invention sets forth a
technique for approximating higher-order curved segments with
quadratic Bezier curve segments. Cubic Bezier path segments are
approximated with quadratic Bezier curve segments and other
lower-order segments. A variance metric is computed for each
quadratic Bezier curve segment, and when the variance metric
indicates that the quadratic Bezier curve segment deviates by more
than a threshold from the corresponding portion of the cubic Bezier
path segment, the cubic Bezier curve segment is subdivided into
multiple quadratic Bezier curve segments. The path composed of the
quadratic Bezier curve segments may then be stroked by rendering
hull geometry that encloses the path. A technique for rasterizing
stroked quadratic Bezier segments is described in patent
application titled, "Point Containment for Quadratic Bezier
Strokes," filed on Mar. 25, 2011 and having Ser. No. 13/071,904
(Attorney Docket No. NVDA/SC-10-0112-US0-US1).
[0030] Various embodiments of a method of the invention for
approximating stroked higher-order curved segments with quadratic
Bezier curve segments include receiving a path including a cubic
Bezier path segment and computing endpoint positions and tangents
for the cubic Bezier path segment. An approximating quadratic
Bezier curve segment is fitted to the endpoint positions and
tangents computed for the cubic Bezier path segment and the method
determines whether the approximating quadratic Bezier curve segment
is accurate based on a variance metric. Other embodiments may apply
a similar approximating approach to partial elliptical arcs. An
approximated path that includes the approximating quadratic Bezier
curve segment is stroked.
BRIEF DESCRIPTION OF THE DRAWINGS
[0031] So that the manner in which the above recited features of
the present invention can be understood in detail, a more
particular description of the invention, briefly summarized above,
may be had by reference to embodiments, some of which are
illustrated in the appended drawings. It is to be noted, however,
that the appended drawings illustrate only typical embodiments of
this invention and are therefore not to be considered limiting of
its scope, for the invention may admit to other equally effective
embodiments.
[0032] FIG. 1A is a prior art scene composed of a sequence of
stroked paths;
[0033] FIG. 1B is the fill for the prior art scene shown in FIG.
1A;
[0034] FIG. 1C is the prior art scene of FIG. 1A with the fill of
FIG. 1B and the stroked sequence of paths;
[0035] FIG. 1D illustrates prior art exterior stroke bounding
curves for various stroke widths of a generating path;
[0036] FIG. 1E illustrates prior art interior stroke bounding
curves for various stroke widths of a generating path;
[0037] FIG. 2A is a block diagram illustrating a computer system
configured to implement one or more aspects of the present
invention;
[0038] FIG. 2B is a block diagram of a parallel processing
subsystem for the computer system of FIG. 2A, according to one
embodiment of the present invention;
[0039] FIG. 3A is a block diagram of a GPC within one of the PPUs
of FIG. 2B, according to one embodiment of the present
invention;
[0040] FIG. 3B is a block diagram of a partition unit within one of
the PPUs of FIG. 2B, according to one embodiment of the present
invention;
[0041] FIG. 3C is a block diagram of a portion of the SPM of FIG.
3A, according to one embodiment of the present invention;
[0042] FIG. 4 is a conceptual diagram of a graphics processing
pipeline that one or more of the PPUs of FIG. 2B can be configured
to implement, according to one embodiment of the present
invention;
[0043] FIG. 5A illustrates a path that may be represented as a
sequence of quadratic Bezier path segments and stroked, according
to one embodiment of the invention;
[0044] FIG. 5B illustrates a generating cubic Bezier curve, control
points, and corresponding inside and outside edges of the stroked
generating cubic Bezier curve, according to one embodiment of the
invention;
[0045] FIG. 5C illustrates a quadratic Bezier curve segment that is
approximates a generating cubic Bezier curve, according to one
embodiment of the invention;
[0046] FIG. 5D illustrates the quadratic Bezier curve segments of
FIG. 5C and conservative bounding hull geometry, according to one
embodiment of the invention;
[0047] FIG. 6A is a flow diagram of method steps for stroking a
path including cubic Bezier segments, according to one embodiment
of the present invention; and
[0048] FIG. 6B is a flow diagram of method steps for processing
cubic path segment parameters as performed in a method step shown
in FIG. 8A, according to one embodiment of the present
invention.
DETAILED DESCRIPTION
[0049] In the following description, numerous specific details are
set forth to provide a more thorough understanding of the present
invention. However, it will be apparent to one of skill in the art
that the present invention may be practiced without one or more of
these specific details. In other instances, well-known features
have not been described in order to avoid obscuring the present
invention.
System Overview
[0050] FIG. 2A is a block diagram illustrating a computer system
100 configured to implement one or more aspects of the present
invention. Computer system 100 includes a central processing unit
(CPU) 102 and a system memory 104 communicating via an
interconnection path that may include a memory bridge 105. Memory
bridge 105, which may be, e.g., a Northbridge chip, is connected
via a bus or other communication path 106 (e.g., a HyperTransport
link) to an I/O (input/output) bridge 107. I/O bridge 107, which
may be, e.g., a Southbridge chip, receives user input from one or
more user input devices 108 (e.g., keyboard, mouse) and forwards
the input to CPU 102 via path 106 and memory bridge 105. A parallel
processing subsystem 112 is coupled to memory bridge 105 via a bus
or other communication path 113 (e.g., a PCI Express, Accelerated
Graphics Port, or HyperTransport link); in one embodiment parallel
processing subsystem 112 is a graphics subsystem that delivers
pixels to a display device 110 (e.g., a conventional CRT or LCD
based monitor). A system disk 114 is also connected to I/O bridge
107. A switch 116 provides connections between I/O bridge 107 and
other components such as a network adapter 118 and various add-in
cards 120 and 121. Other components (not explicitly shown),
including USB or other port connections, CD drives, DVD drives,
film recording devices, and the like, may also be connected to I/O
bridge 107. Communication paths interconnecting the various
components in FIG. 2A may be implemented using any suitable
protocols, such as PCI (Peripheral Component Interconnect),
PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or
any other bus or point-to-point communication protocol(s), and
connections between different devices may use different protocols
as is known in the art.
[0051] In one embodiment, the parallel processing subsystem 112
incorporates circuitry optimized for graphics and video processing,
including, for example, video output circuitry, and constitutes a
graphics processing unit (GPU). In another embodiment, the parallel
processing subsystem 112 incorporates circuitry optimized for
general purpose processing, while preserving the underlying
computational architecture, described in greater detail herein. In
yet another embodiment, the parallel processing subsystem 112 may
be integrated with one or more other system elements, such as the
memory bridge 105, CPU 102, and I/O bridge 107 to form a system on
chip (SoC).
[0052] It will be appreciated that the system shown herein is
illustrative and that variations and modifications are possible.
The connection topology, including the number and arrangement of
bridges, the number of CPUs 102, and the number of parallel
processing subsystems 112, may be modified as desired. For
instance, in some embodiments, system memory 104 is connected to
CPU 102 directly rather than through a bridge, and other devices
communicate with system memory 104 via memory bridge 105 and CPU
102. In other alternative topologies, parallel processing subsystem
112 is connected to I/O bridge 107 or directly to CPU 102, rather
than to memory bridge 105. In still other embodiments, I/O bridge
107 and memory bridge 105 might be integrated into a single chip.
Large embodiments may include two or more CPUs 102 and two or more
parallel processing systems 112. The particular components shown
herein are optional; for instance, any number of add-in cards or
peripheral devices might be supported. In some embodiments, switch
116 is eliminated, and network adapter 118 and add-in cards 120,
121 connect directly to I/O bridge 107.
[0053] FIG. 2B illustrates a parallel processing subsystem 112,
according to one embodiment of the present invention. As shown,
parallel processing subsystem 112 includes one or more parallel
processing units (PPUs) 202, each of which is coupled to a local
parallel processing (PP) memory 204. In general, a parallel
processing subsystem includes a number U of PPUs, where U.gtoreq.1.
(Herein, multiple instances of like objects are denoted with
reference numbers identifying the object and parenthetical numbers
identifying the instance where needed.) PPUs 202 and parallel
processing memories 204 may be implemented using one or more
integrated circuit devices, such as programmable processors,
application specific integrated circuits (ASICs), or memory
devices, or in any other technically feasible fashion.
[0054] Referring again to FIG. 2A, in some embodiments, some or all
of PPUs 202 in parallel processing subsystem 112 are graphics
processors with rendering pipelines that can be configured to
perform various tasks related to generating pixel data from
graphics data supplied by CPU 102 and/or system memory 104 via
memory bridge 105 and bus 113, interacting with local parallel
processing memory 204 (which can be used as graphics memory
including, e.g., a conventional frame buffer) to store and update
pixel data, delivering pixel data to display device 110, and the
like. In some embodiments, parallel processing subsystem 112 may
include one or more PPUs 202 that operate as graphics processors
and one or more other PPUs 202 that are used for general-purpose
computations. The PPUs may be identical or different, and each PPU
may have its own dedicated parallel processing memory device(s) or
no dedicated parallel processing memory device(s). One or more PPUs
202 may output data to display device 110 or each PPU 202 may
output data to one or more display devices 110.
[0055] In operation, CPU 102 is the master processor of computer
system 100, controlling and coordinating operations of other system
components. In particular, CPU 102 issues commands that control the
operation of PPUs 202. In some embodiments, CPU 102 writes a stream
of commands for each PPU 202 to a pushbuffer (not explicitly shown
in either FIG. 2A or FIG. 2B) that may be located in system memory
104, parallel processing memory 204, or another storage location
accessible to both CPU 102 and PPU 202. PPU 202 reads the command
stream from the pushbuffer and then executes commands
asynchronously relative to the operation of CPU 102.
[0056] Referring back now to FIG. 2B, each PPU 202 includes an I/O
(input/output) unit 205 that communicates with the rest of computer
system 100 via communication path 113, which connects to memory
bridge 105 (or, in one alternative embodiment, directly to CPU
102). The connection of PPU 202 to the rest of computer system 100
may also be varied. In some embodiments, parallel processing
subsystem 112 is implemented as an add-in card that can be inserted
into an expansion slot of computer system 100. In other
embodiments, a PPU 202 can be integrated on a single chip with a
bus bridge, such as memory bridge 105 or I/O bridge 107. In still
other embodiments, some or all elements of PPU 202 may be
integrated on a single chip with CPU 102.
[0057] In one embodiment, communication path 113 is a PCI-EXPRESS
link, in which dedicated lanes are allocated to each PPU 202, as is
known in the art. Other communication paths may also be used. An
I/O unit 205 generates packets (or other signals) for transmission
on communication path 113 and also receives all incoming packets
(or other signals) from communication path 113, directing the
incoming packets to appropriate components of PPU 202. For example,
commands related to processing tasks may be directed to a host
interface 206, while commands related to memory operations (e.g.,
reading from or writing to parallel processing memory 204) may be
directed to a memory crossbar unit 210. Host interface 206 reads
each pushbuffer and outputs the work specified by the pushbuffer to
a front end 212.
[0058] Each PPU 202 advantageously implements a highly parallel
processing architecture. As shown in detail, PPU 202(0) includes a
processing cluster array 230 that includes a number C of general
processing clusters (GPCs) 208, where C.gtoreq.1. Each GPC 208 is
capable of executing a large number (e.g., hundreds or thousands)
of threads concurrently, where each thread is an instance of a
program. In various applications, different GPCs 208 may be
allocated for processing different types of programs or for
performing different types of computations. For example, in a
graphics application, a first set of GPCs 208 may be allocated to
perform patch tessellation operations and to produce primitive
topologies for patches, and a second set of GPCs 208 may be
allocated to perform tessellation shading to evaluate patch
parameters for the primitive topologies and to determine vertex
positions and other per-vertex attributes. The allocation of GPCs
208 may vary dependent on the workload arising for each type of
program or computation.
[0059] GPCs 208 receive processing tasks to be executed via a work
distribution unit 200, which receives commands defining processing
tasks from front end unit 212. Processing tasks include indices of
data to be processed, e.g., surface (patch) data, primitive data,
vertex data, and/or pixel data, as well as state parameters and
commands defining how the data is to be processed (e.g., what
program is to be executed). Work distribution unit 200 may be
configured to fetch the indices corresponding to the tasks, or work
distribution unit 200 may receive the indices from front end 212.
Front end 212 ensures that GPCs 208 are configured to a valid state
before the processing specified by the pushbuffers is
initiated.
[0060] When PPU 202 is used for graphics processing, for example,
the processing workload for each patch is divided into
approximately equal sized tasks to enable distribution of the
tessellation processing to multiple GPCs 208. A work distribution
unit 200 may be configured to produce tasks at a frequency capable
of providing tasks to multiple GPCs 208 for processing. By
contrast, in conventional systems, processing is typically
performed by a single processing engine, while the other processing
engines remain idle, waiting for the single processing engine to
complete its tasks before beginning their processing tasks. In some
embodiments of the present invention, portions of GPCs 208 are
configured to perform different types of processing. For example a
first portion may be configured to perform vertex shading and
topology generation, a second portion may be configured to perform
tessellation and geometry shading, and a third portion may be
configured to perform pixel shading in screen space to produce a
rendered image. Intermediate data produced by GPCs 208 may be
stored in buffers to allow the intermediate data to be transmitted
between GPCs 208 for further processing.
[0061] Memory interface 214 includes a number D of partition units
215 that are each directly coupled to a portion of parallel
processing memory 204, where D.gtoreq.1. As shown, the number of
partition units 215 generally equals the number of DRAM 220. In
other embodiments, the number of partition units 215 may not equal
the number of memory devices. Persons skilled in the art will
appreciate that DRAM 220 may be replaced with other suitable
storage devices and can be of generally conventional design. A
detailed description is therefore omitted. Render targets, such as
frame buffers or texture maps may be stored across DRAMs 220,
allowing partition units 215 to write portions of each render
target in parallel to efficiently use the available bandwidth of
parallel processing memory 204.
[0062] Any one of GPCs 208 may process data to be written to any of
the DRAMs 220 within parallel processing memory 204. Crossbar unit
210 is configured to route the output of each GPC 208 to the input
of any partition unit 215 or to another GPC 208 for further
processing. GPCs 208 communicate with memory interface 214 through
crossbar unit 210 to read from or write to various external memory
devices. In one embodiment, crossbar unit 210 has a connection to
memory interface 214 to communicate with I/O unit 205, as well as a
connection to local parallel processing memory 204, thereby
enabling the processing cores within the different GPCs 208 to
communicate with system memory 104 or other memory that is not
local to PPU 202. In the embodiment shown in FIG. 2B, crossbar unit
210 is directly connected with I/O unit 205. Crossbar unit 210 may
use virtual channels to separate traffic streams between the GPCs
208 and partition units 215.
[0063] Again, GPCs 208 can be programmed to execute processing
tasks relating to a wide variety of applications, including but not
limited to, linear and nonlinear data transforms, filtering of
video and/or audio data, modeling operations (e.g., applying laws
of physics to determine position, velocity and other attributes of
objects), image rendering operations (e.g., tessellation shader,
vertex shader, geometry shader, and/or pixel shader programs), and
so on. PPUs 202 may transfer data from system memory 104 and/or
local parallel processing memories 204 into internal (on-chip)
memory, process the data, and write result data back to system
memory 104 and/or local parallel processing memories 204, where
such data can be accessed by other system components, including CPU
102 or another parallel processing subsystem 112.
[0064] A PPU 202 may be provided with any amount of local parallel
processing memory 204, including no local memory, and may use local
memory and system memory in any combination. For instance, a PPU
202 can be a graphics processor in a unified memory architecture
(UMA) embodiment. In such embodiments, little or no dedicated
graphics (parallel processing) memory would be provided, and PPU
202 would use system memory exclusively or almost exclusively. In
UMA embodiments, a PPU 202 may be integrated into a bridge chip or
processor chip or provided as a discrete chip with a high-speed
link (e.g., PCI-EXPRESS) connecting the PPU 202 to system memory
via a bridge chip or other communication means.
[0065] As noted above, any number of PPUs 202 can be included in a
parallel processing subsystem 112. For instance, multiple PPUs 202
can be provided on a single add-in card, or multiple add-in cards
can be connected to communication path 113, or one or more of PPUs
202 can be integrated into a bridge chip. PPUs 202 in a multi-PPU
system may be identical to or different from one another. For
instance, different PPUs 202 might have different numbers of
processing cores, different amounts of local parallel processing
memory, and so on. Where multiple PPUs 202 are present, those PPUs
may be operated in parallel to process data at a higher throughput
than is possible with a single PPU 202. Systems incorporating one
or more PPUs 202 may be implemented in a variety of configurations
and form factors, including desktop, laptop, or handheld personal
computers, servers, workstations, game consoles, embedded systems,
and the like.
Processing Cluster Array Overview
[0066] FIG. 3A is a block diagram of a GPC 208 within one of the
PPUs 202 of FIG. 2B, according to one embodiment of the present
invention. Each GPC 208 may be configured to execute a large number
of threads in parallel, where the term "thread" refers to an
instance of a particular program executing on a particular set of
input data. In some embodiments, single-instruction, multiple-data
(SIMD) instruction issue techniques are used to support parallel
execution of a large number of threads without providing multiple
independent instruction units. In other embodiments,
single-instruction, multiple-thread (SIMT) techniques are used to
support parallel execution of a large number of generally
synchronized threads, using a common instruction unit configured to
issue instructions to a set of processing engines within each one
of the GPCs 208. Unlike a SIMD execution regime, where all
processing engines typically execute identical instructions, SIMT
execution allows different threads to more readily follow divergent
execution paths through a given thread program. Persons skilled in
the art will understand that a SIMD processing regime represents a
functional subset of a SIMT processing regime.
[0067] Operation of GPC 208 is advantageously controlled via a
pipeline manager 305 that distributes processing tasks to streaming
multiprocessors (SPMs) 310. Pipeline manager 305 may also be
configured to control a work distribution crossbar 330 by
specifying destinations for processed data output by SPMs 310.
[0068] In one embodiment, each GPC 208 includes a number M of SPMs
310, where M.gtoreq.1, each SPM 310 configured to process one or
more thread groups. Also, each SPM 310 advantageously includes an
identical set of functional execution units (e.g., execution and
load-store units--shown as Exec units 302 and LSUs 303 in FIG. 3C)
that may be pipelined, allowing a new instruction to be issued
before a previous instruction has finished, as is known in the art.
Any combination of functional execution units may be provided. In
one embodiment, the functional units support a variety of
operations including integer and floating point arithmetic (e.g.,
addition and multiplication), comparison operations, Boolean
operations (AND, OR, XOR), bit-shifting, and computation of various
algebraic functions (e.g., planar interpolation, trigonometric,
exponential, and logarithmic functions, etc.); and the same
functional-unit hardware can be leveraged to perform different
operations.
[0069] The series of instructions transmitted to a particular GPC
208 constitutes a thread, as previously defined herein, and the
collection of a certain number of concurrently executing threads
across the parallel processing engines (not shown) within an SPM
310 is referred to herein as a "warp" or "thread group." As used
herein, a "thread group" refers to a group of threads concurrently
executing the same program on different input data, with one thread
of the group being assigned to a different processing engine within
an SPM 310. A thread group may include fewer threads than the
number of processing engines within the SPM 310, in which case some
processing engines will be idle during cycles when that thread
group is being processed. A thread group may also include more
threads than the number of processing engines within the SPM 310,
in which case processing will take place over consecutive clock
cycles. Since each SPM 310 can support up to G thread groups
concurrently, it follows that up to G*M thread groups can be
executing in GPC 208 at any given time.
[0070] Additionally, a plurality of related thread groups may be
active (in different phases of execution) at the same time within
an SPM 310. This collection of thread groups is referred to herein
as a "cooperative thread array" ("CTA") or "thread array." The size
of a particular CTA is equal to m*k, where k is the number of
concurrently executing threads in a thread group and is typically
an integer multiple of the number of parallel processing engines
within the SPM 310, and m is the number of thread groups
simultaneously active within the SPM 310. The size of a CTA is
generally determined by the programmer and the amount of hardware
resources, such as memory or registers, available to the CTA.
[0071] Each SPM 310 contains an L1 cache (not shown) or uses space
in a corresponding L1 cache outside of the SPM 310 that is used to
perform load and store operations. Each SPM 310 also has access to
L2 caches within the partition units 215 that are shared among all
GPCs 208 and may be used to transfer data between threads. Finally,
SPMs 310 also have access to off-chip "global" memory, which can
include, e.g., parallel processing memory 204 and/or system memory
104. It is to be understood that any memory external to PPU 202 may
be used as global memory. Additionally, an L1.5 cache 335 may be
included within the GPC 208, configured to receive and hold data
fetched from memory via memory interface 214 requested by SPM 310,
including instructions, uniform data, and constant data, and
provide the requested data to SPM 310. Embodiments having multiple
SPMs 310 in GPC 208 beneficially share common instructions and data
cached in L1.5 cache 335.
[0072] Each GPC 208 may include a memory management unit (MMU) 328
that is configured to map virtual addresses into physical
addresses. In other embodiments, MMU(s) 328 may reside within the
memory interface 214. The MMU 328 includes a set of page table
entries (PTEs) used to map a virtual address to a physical address
of a tile and optionally a cache line index. The MMU 328 may
include address translation lookaside buffers (TLB) or caches which
may reside within multiprocessor SPM 310 or the L1 cache or GPC
208. The physical address is processed to distribute surface data
access locality to allow efficient request interleaving among
partition units. The cache line index may be used to determine
whether of not a request for a cache line is a hit or miss.
[0073] In graphics and computing applications, a GPC 208 may be
configured such that each SPM 310 is coupled to a texture unit 315
for performing texture mapping operations, e.g., determining
texture sample positions, reading texture data, and filtering the
texture data. Texture data is read from an internal texture L1
cache (not shown) or in some embodiments from the L1 cache within
SPM 310 and is fetched from an L2 cache, parallel processing memory
204, or system memory 104, as needed. Each SPM 310 outputs
processed tasks to work distribution crossbar 330 in order to
provide the processed task to another GPC 208 for further
processing or to store the processed task in an L2 cache, parallel
processing memory 204, or system memory 104 via crossbar unit 210.
A preROP (pre-raster operations) 325 is configured to receive data
from SPM 310, direct data to ROP units within partition units 215,
and perform optimizations for color blending, organize pixel color
data, and perform address translations.
[0074] It will be appreciated that the core architecture described
herein is illustrative and that variations and modifications are
possible. Any number of processing units, e.g., SPMs 310 or texture
units 315, preROPs 325 may be included within a GPC 208. Further,
while only one GPC 208 is shown, a PPU 202 may include any number
of GPCs 208 that are advantageously functionally similar to one
another so that execution behavior does not depend on which GPC 208
receives a particular processing task. Further, each GPC 208
advantageously operates independently of other GPCs 208 using
separate and distinct processing units, L1 caches, and so on.
[0075] FIG. 3B is a block diagram of a partition unit 215 within
one of the PPUs 202 of FIG. 2B, according to one embodiment of the
present invention. As shown, partition unit 215 includes a L2 cache
350, a frame buffer (FB) DRAM interface 355, and a raster
operations unit (ROP) 360. L2 cache 350 is a read/write cache that
is configured to perform load and store operations received from
crossbar unit 210 and ROP 360. Read misses and urgent writeback
requests are output by L2 cache 350 to FB DRAM interface 355 for
processing. Dirty updates are also sent to FB 355 for opportunistic
processing. FB 355 interfaces directly with DRAM 220, outputting
read and write requests and receiving data read from DRAM 220.
[0076] In graphics applications, ROP 360 is a processing unit that
performs raster operations, such as stencil, z test, blending, and
the like, and outputs pixel data as processed graphics data for
storage in graphics memory. In some embodiments of the present
invention, ROP 360 is included within each GPC 208 instead of
partition unit 215, and pixel read and write requests are
transmitted over crossbar unit 210 instead of pixel fragment
data.
[0077] The processed graphics data may be displayed on display
device 110 or routed for further processing by CPU 102 or by one of
the processing entities within parallel processing subsystem 112.
Each partition unit 215 includes a ROP 360 in order to distribute
processing of the raster operations. In some embodiments, ROP 360
may be configured to compress z or color data that is written to
memory and decompress z or color data that is read from memory.
[0078] Persons skilled in the art will understand that the
architecture described in FIGS. 2A, 2B, 3A, and 3B in no way limits
the scope of the present invention and that the techniques taught
herein may be implemented on any properly configured processing
unit, including, without limitation, one or more CPUs, one or more
multi-core CPUs, one or more PPUs 202, one or more GPCs 208, one or
more graphics or special purpose processing units, or the like,
without departing the scope of the present invention.
[0079] In embodiments of the present invention, it is desirable to
use PPU 202 or other processor(s) of a computing system to execute
general-purpose computations using thread arrays. Each thread in
the thread array is assigned a unique thread identifier ("thread
ID") that is accessible to the thread during its execution. The
thread ID, which can be defined as a one-dimensional or
multi-dimensional numerical value controls various aspects of the
thread's processing behavior. For instance, a thread ID may be used
to determine which portion of the input data set a thread is to
process and/or to determine which portion of an output data set a
thread is to produce or write.
[0080] A sequence of per-thread instructions may include at least
one instruction that defines a cooperative behavior between the
representative thread and one or more other threads of the thread
array. For example, the sequence of per-thread instructions might
include an instruction to suspend execution of operations for the
representative thread at a particular point in the sequence until
such time as one or more of the other threads reach that particular
point, an instruction for the representative thread to store data
in a shared memory to which one or more of the other threads have
access, an instruction for the representative thread to atomically
read and update data stored in a shared memory to which one or more
of the other threads have access based on their thread IDs, or the
like. The CTA program can also include an instruction to compute an
address in the shared memory from which data is to be read, with
the address being a function of thread ID. By defining suitable
functions and providing synchronization techniques, data can be
written to a given location in shared memory by one thread of a CTA
and read from that location by a different thread of the same CTA
in a predictable manner. Consequently, any desired pattern of data
sharing among threads can be supported, and any thread in a CTA can
share data with any other thread in the same CTA. The extent, if
any, of data sharing among threads of a CTA is determined by the
CTA program; thus, it is to be understood that in a particular
application that uses CTAs, the threads of a CTA might or might not
actually share data with each other, depending on the CTA program,
and the terms "CIA" and "thread array" are used synonymously
herein.
[0081] FIG. 3C is a block diagram of the SPM 310 of FIG. 3A,
according to one embodiment of the present invention. The SPM 310
includes an instruction L1 cache 370 that is configured to receive
instructions and constants from memory via L1.5 cache 335. A warp
scheduler and instruction unit 312 receives instructions and
constants from the instruction L1 cache 370 and controls local
register file 304 and SPM 310 functional units according to the
instructions and constants. The SPM 310 functional units include N
exec (execution or processing) units 302 and P load-store units
(LSU) 303.
[0082] SPM 310 provides on-chip (internal) data storage with
different levels of accessibility. Special registers (not shown)
are readable but not writeable by LSU 303 and are used to store
parameters defining each CTA thread's "position." In one
embodiment, special registers include one register per CTA thread
(or per exec unit 302 within SPM 310) that stores a thread ID; each
thread ID register is accessible only by a respective one of the
exec unit 302. Special registers may also include additional
registers, readable by all CTA threads (or by all LSUs 303) that
store a CTA identifier, the CTA dimensions, the dimensions of a
grid to which the CTA belongs, and an identifier of a grid to which
the CTA belongs. Special registers are written during
initialization in response to commands received via front end 212
from device driver 103 and do not change during CTA execution.
[0083] A parameter memory (not shown) stores runtime parameters
(constants) that can be read but not written by any CTA thread (or
any LSU 303). In one embodiment, device driver 103 provides
parameters to the parameter memory before directing SPM 310 to
begin execution of a CTA that uses these parameters. Any CTA thread
within any CTA (or any exec unit 302 within SPM 310) can access
global memory through a memory interface 214. Portions of global
memory may be stored in the L1 cache 320.
[0084] Local register file 304 is used by each CTA thread as
scratch space; each register is allocated for the exclusive use of
one thread, and data in any of local register file 304 is
accessible only to the CTA thread to which it is allocated. Local
register file 304 can be implemented as a register file that is
physically or logically divided into P lanes, each having some
number of entries (where each entry might store, e.g., a 32-bit
word). One lane is assigned to each of the N exec units 302 and P
load-store units LSU 303, and corresponding entries in different
lanes can be populated with data for different threads executing
the same program to facilitate SIMD execution. Different portions
of the lanes can be allocated to different ones of the G concurrent
thread groups, so that a given entry in the local register file 304
is accessible only to a particular thread. In one embodiment,
certain entries within the local register file 304 are reserved for
storing thread identifiers, implementing one of the special
registers.
[0085] Shared memory 306 is accessible to all CTA threads (within a
single CTA); any location in shared memory 306 is accessible to any
CTA thread within the same CTA (or to any processing engine within
SPM 310). Shared memory 306 can be implemented as a shared register
file or shared on-chip cache memory with an interconnect that
allows any processing engine to read from or write to any location
in the shared memory. In other embodiments, shared state space
might map onto a per-CTA region of off-chip memory, and be cached
in L1 cache 320. The parameter memory can be implemented as a
designated section within the same shared register file or shared
cache memory that implements shared memory 306, or as a separate
shared register file or on-chip cache memory to which the LSUs 303
have read-only access. In one embodiment, the area that implements
the parameter memory is also used to store the CTA ID and grid ID,
as well as CTA and grid dimensions, implementing portions of the
special registers. Each LSU 303 in SPM 310 is coupled to a unified
address mapping unit 352 that converts an address provided for load
and store instructions that are specified in a unified memory space
into an address in each distinct memory space. Consequently, an
instruction may be used to access any of the local, shared, or
global memory spaces by specifying an address in the unified memory
space.
[0086] The L1 Cache 320 in each SPM 310 can be used to cache
private per-thread local data and also per-application global data.
In some embodiments, the per-CTA shared data may be cached in the
L1 cache 320. The LSUs 303 are coupled to a uniform L1 cache 375,
the shared memory 306, and the L1 cache 320 via a memory and cache
interconnect 380. The uniform L1 cache 375 is configured to receive
read-only data and constants from memory via the L1.5 Cache
335.
Approximating Stroked Curved Segments
[0087] Path stroking has an associated "stroke width" that defines
the region that is included in the stroke when a circle having a
diameter of the stroke width is moved along the path segment. The
path segment is considered a generating curve and the circle
generates an inside offset curve and an outside offset curve as the
circle moves along the path segment. Mathematical computation of
the inside and the outside offset curves is difficult. Because
stroking is an important operation for many application programs
that produce 2D images, it is desirable to accelerate stroking
operations. In one embodiment, a GPU, such as the PPU 202, may be
used to perform functions to accelerate stroking operations.
Importantly, tessellation of the path segments is avoided. Instead,
a path is approximated by quadratic Bezier curve segments or
segments of lower complexity, e.g., arcs, line segments, and the
like.
[0088] The GPU-accelerated stroking technique for rasterizing
stroked quadratic Bezier segments described in patent application
titled, "Point Containment for Quadratic Bezier Strokes," filed on
Mar. 25, 2011 and having Ser. No. 13/071,904 (Attorney Docket No.
NVDA/SC-10-0112-US0-US1) typically perform approximately 1 to 2
orders of magnitude more fragment processing operations per sample
than comparable GPU-accelerated techniques for filling paths. This
relative expense is justified because it results in fewer
approximations and a more compact and resolution-independent
representation from which to render stroked paths. The observation
that more rendered pixels are filled than stroked in typical path
rendering scenes with both types of path rendering also helps
balance the relatively higher per-sample cost of stroking to
filling.
[0089] FIG. 5A illustrates a generating curve 500 that may be
approximated by a sequence of quadratic Bezier path segments and
stroked, according to one embodiment of the invention. A stroke
width having a constant stroke radius 543 defines a corresponding
inside offset curve 542 and a corresponding outside offset curve
546 of the stroked generating curve 500 that are separated from the
generating curve 500 by the constant distance of the stroke radius
543. First, the generating curve 500 is approximated by quadratic
Bezier path segments, partial circles, and line segments.
Approximating a path with quadratic Bezier curve segments, partial
circles, and/or line segments produces a geometry set that is
suitable for stroking rendered paths containing higher-order curved
segments, such as cubic Bezier and partial elliptical arc path
segments, without tessellating the path.
[0090] More specifically, a stroking engine approximates the
higher-order curved segments into quadratic Bezier curves so that
the initial and terminal tangents are matched by the resulting
sequence of quadratic Bezier segments, partial circles, and line
segments and the continuity of the tangents is also preserved at
each shared endpoint. When an approximating quadratic Bezier curve
does not accurately represent the originating higher-order curve
segment of the path, the stroke engine divides the higher-order
curve segment into multiple quadratic Bezier path segments. The
stroke engine limits the subdivision into path segments based on
the stroke width, so that the stroke boundary does not expose the
boundary of the generating curve. In order to maintain
geometrically important features of the curve and continuity of the
tangents, key features such as the self-intersection that occurs at
the key feature location 520 of the generating curve 500 are
identified during the subdivision process. The generating curve 500
is subdivided into two or more quadratic Bezier curve segments at
the key feature location 520. Other key features include cusps and
points of maximum curvature. When the key feature is a cusp within
some segment of the generating curve, generating a partial circle
centered at the cusp location ensures the curve's stroke contains
all the points within a stroke radius of this cusp.
[0091] The quadratic Bezier curve segments, partial circles, and
line segments generated during the subdivision process to
approximate the generating curve 500 are processed to determine
whether or not points lie within the stroke region of each
quadratic Bezier curve segment, arc, or line segment. Rather than
computing the inside and outside offset curves, a function is
evaluated for each point that may be within the stroke region that
is bounded by the inside offset curve 542 and the outside offset
curve 546. The function is specific to the point, so that each
point has a respective function. Points that lie within the stroke
region are then stroked to produce a stroked path. In the case of a
path consisting of multiple segments, a point belongs to the path's
stroke if the point is within the stroke of any segment belonging
to the path.
[0092] Bezier curves are defined by control points. In the 2D
content of path rendering, each control point is a 2D position.
Curved path segments for a path may be generated by path commands
for quadratic Bezier curves, cubic Bezier curves, and partial
elliptical arcs.
[0093] A quadratic Bezier curve is specified by 3 control points
and a cubic Bezier curve is specified by 4 control points. The
QUADRATICTO command uses the terminal position of the prior command
as its initial control point (x0,y0) and then 4 associated
coordinates form the two new (x1,y1) and (x2,y2) control points.
The quadratic Bezier curve starts at (x0,y0) heading towards
(x1,y1) and ends at (x2,y2) as if coming from (x1,y1). Despite
(x1,y1) providing the initial tangent direction when starting from
(x0,y0) and terminating at (x2,y2), the resulting curve does not
pass through (x1,y1); for this reason, (x1,y1) is known as an
extrapolating control point while (x0,y0) and (x2,y2) are known as
interpolating control points.
[0094] The CUBICTO command is similar to the QUADRATICTO command
but generates a cubic Bezier curve. Such a curve is specified by 4
control points. The CUBICTO command uses the terminal position of
the prior command as its initial control point (x0,y0) and then 6
associated coordinates form the 3 new (x1,y1), (x2,y2), and (x3,y3)
control points. The cubic Bezier curve starts at (x0,y0) heading
towards (x1,y1) and ends at (x3,y3) as if coming from (x2,y2).
While a quadratic Bezier curve has a single extrapolating control
point, cubic Bezier curves have two extrapolating control points,
(x1,y1) and (x2,y2). A cubic Bezier curve has the freedom, unlike a
quadratic Bezier curve, to specify arbitrary initial and terminal
tangent directions for its end-points. This control makes cubic
Bezier curves popular with artists. This additional control comes
from the curve being described by a third-order bivariate
polynomial equation instead of a second-order equation in the case
of a quadratic Bezier curve (and first-order in the case of line
segments).
[0095] FIG. 5B illustrates a generating cubic Bezier curve 540,
control points C.sub.0, C.sub.1, C.sub.2, and C.sub.3, and
corresponding inside and outside edges of the stroked generating
cubic Bezier curve, according to one embodiment of the
invention.
[0096] The cubic Bezier curve 540 with control points C.sub.0,
C.sub.1, C.sub.2, and C.sub.3 can be approximated by a quadratic
Bezier segment that shares the same end-points positions (C.sub.0
and C.sub.3) and normalized tangents (T.sub.0 and T.sub.3). In this
case, the quadratic Bezier curve segment has the control points
C.sub.0, C.sub.mid, and C.sub.3 where C.sub.mid is
C mid = C 0 + C 1 - C 0 T 3 T 0 T 3 ( C 1 - C 0 ) where ( equation
1 ) T 0 = C 1 - C 0 ( C 1 - C 0 ) ( C 1 - C 0 ) T 3 = C 3 - C 2 ( C
3 - C 2 ) ( C 3 - C 2 ) ( equation 2 ) ##EQU00001##
[0097] Notice these equations will result in division by zero if
C.sub.0 and C.sub.1 are co-located, C.sub.2 and C.sub.3 are
co-located, or T.sub.0 and T.sub.3 are coincident. These are all
situations that can occur when 3 or more control points of the
cubic Bezier segment are collinear. In order to avoid these
collinear situations or very nearly collinear control points (i.e.,
within a collinear threshold), such cubic Bezier segments should be
replaced with line segments appropriately.
[0098] FIG. 5C illustrates a quadratic Bezier curve segment 555
that approximates the generating cubic Bezier curve shown in FIG.
5B, according to one embodiment of the invention. The quadratic
Bezier curve segment 555 shares the same end-point positions
(C.sub.0 and C.sub.3) and normalized tangents (T.sub.0 and T.sub.3)
as the generating cubic Bezier curve 540 and has the control points
C.sub.0, C.sub.mid, and C.sub.3.
[0099] A variance metric V between the cubic Bezier curve 540 and
the approximating quadratic Bezier curve segment 555 with matching
tangent end-points directions is computed as
V = C 0 ( 2 C 0 - 12 C 1 - 9 C 2 + 3 C 3 + 14 C mid ) + C 1 ( 18 C
1 + 27 C 2 - C 3 - 42 C mid ) + C 2 ( 18 C 2 - 12 C 3 - 42 C mid )
+ C 3 ( 2 C 3 + 14 C mid ) + 28 C mid C mid 210 ( equation 3 )
##EQU00002##
[0100] The variance is the square of the deviation between the
cubic curve and its approximating quadratic form. Hence a deviation
value computed as the square root of V divided by an approximation
of the arc length of the cubic Bezier curve 540 is comparable to
the displacement of the approximating quadratic Bezier curve
segment 555 compared with the cubic Bezier curve 540. Other
variance metrics are possible, but equation 3 minimizes in a least
squares sense the difference between corresponding parametric
positions on the cubic Bezier segment and its approximating
quadratic Bezier segment. The deviation value may be compared to
the stroke width to quantify the accuracy of the approximating
quadratic Bezier curve segment 555. When the deviation value is not
within a tolerance threshold, the cubic Bezier curve segment 540 is
subdivided into two cubic Bezier curve segments using the
well-known De Casteljau algorithm for splitting Bezier curves. The
two new cubic Bezier curve segments are again fitted to their
respective approximate quadratic Bezier segment (essentially
treating them as a new generating cubic Bezier curve 540. This
process of subdivision continues until the variance metric is
satisfied or some maximum subdivision limit is reached. The
geometric tangent (G1) continuity at a shared endpoint of the two
new quadratic Bezier curve segments is maintained; this ensures
even under extremely magnified or zoomed viewing there is never any
apparent loss of curved appearance along the curved stroke
segment's boundary, in contrast to the prior art's use of line
segments. In one embodiment, a cubic Bezier curve may be subdivided
into a number of quadratic Bezier curve segments based on the size
of the stroke width. For example, the number may increase as the
stroke width decreases and decrease as the stroke width
increases.
[0101] Following subdivision into approximating quadratic Bezier
curve segments, a point containment algorithm may be used to
determine whether a point is "inside" or "outside" the stroke
region of a path. Applying a point containment algorithm to each
and every sample that is potentially within the boundary defined by
the path or stroked boundary is fundamental to the process of
stroking a rendered path.
[0102] For each quadratic Bezier path segment, the stroking engine
generates a conservative hull polygon that completely encloses a
stroke region of the quadratic Bezier path segment. FIG. 5D
illustrates the quadratic Bezier curve segment 555 of FIG. 5C and
conservative bounding hull geometry 550, according to one
embodiment of the invention. The stroking engine then computes a
set of derived values from each quadratic Bezier path segment and
the stroke width to facilitate an efficient computation of nearest
points on the quadratic Bezier path segment to a point that may be
within the stroke region. When a GPU is used to perform the
stroking operations, the derived values may be stored in a texture
or texture buffer object and ordered to correspond with their
respective quadratic Bezier curve segment's convex hull geometry.
Miter join styles between cubic Bezier segments are added with
conventional triangles.
[0103] The tangent of a sub-path is not necessarily continuous at
junctions between quadratic Bezier curve segments. So additional
rules are needed to determine what happens at and in the vicinity
of such junctions as well as what happens at the terminal (start
and end) points of sub-paths. Therefore stroking specifies further
stroking rules to handle these situations. A join style determines
what happens at the junction between two connected path segments.
Typical join styles are round, miter, and bevel. An end-cap style
indicates what happens at the end points of open (non-closed)
sub-paths. Typical end-cap styles are round, square, none, and
triangle. If the sub-path is closed, the join style is used to
connect the initial and terminal segments rather than using end
caps.
[0104] Therefore, points may belong to the path's stroke based on
additional end-cap and join-style point containment tests. Round
end-cap and join-style tests depend on whether the point is within
r units of the path's end-points or segment join points. The miter
and bevel join-styles depend on the normalized tangent directions
of the initial or terminal points of the path. The miter and bevel
join-styles depend on the two normalized tangent directions when
two path segments join at a segment join point. For a mitered join,
if the cosine of the angle between the tangent directions exceeds
the miter-limit, the miter is treated as either a bevel or
truncated miter.
[0105] In addition to the hull geometry bounding the quadratic
Bezier curve segments, the stroking engine also collects or
generates a set of polygonal geometry for any square or triangular
end-caps or mitered or beveled join styles. The stroking engine
also collects or generates a set of polygonal geometry for rounded
stroking with associated coordinates to generate round end-caps,
join styles, and hemi-circles for cusps of curved segments
converted to line segments. This geometry may include texture
coordinates indicating vertex position relative to the junction,
end-point, or cusp. Cusps on segments of the generating curve are
identified by the stroke engine as key features so that a
generating curve such as a cubic Bezier segment containing a cusp
will be subdivided into quadratic cubic Bezier curve segments on
either side of the cusp location. In order to include the full set
of stroke locations within a stroke radius of such cusp locations,
the stroke engine should add a partial circle centered at such cusp
locations with a radius equal to the stroke radius to the curve's
set of approximating geometry.
[0106] This same process can be used to decompose other
higher-order curved segments into a sequence of quadratic Bezier
curves, partial circles, and line segments. In particular, partial
elliptical arcs can be decomposed by using the procedure above
where the initial and terminal control points are the start and
stop positions of the arc and the tangent vectors of the arc at its
end points can be used to generate extrapolating control points of
a cubic Bezier curve to serve as a proxy for the arc. When
splitting is required, the curve to split should be the generating
higher-order curve is required,
[0107] FIG. 6A is a flow diagram of method steps for stroking a
path including cubic Bezier segments, according to one embodiment
of the present invention. Although the method steps are described
in conjunction with the systems of FIGS. 2A, 2B, 3A, 3B, 3C, and 4,
persons skilled in the art will understand that any system
configured to perform the method steps, in any order, is within the
scope of the inventions. The CPU 102 or parallel processing
subsystem 112 may be configured to stroke a path that includes
cubic Bezier path segments, quadratic Bezier path segments, line
segments, and arcs. In one embodiment, the control points defining
each path segment are sorted before that path segment is processed
to avoid the generation of approximating quadratic Bezier curve
segments that are dependent on the path segment direction; this
allows the path segment's stroke coverage to be invariant with
direction of the stroke.
[0108] At step 605 a path segment including at least one cubic
Bezier path segment and stroke width is received by a path stroke
engine and is approximated by one or more quadratic Bezier curve
segments. The path stroke engine may be embodied as an application
program for execution by CPU 102 and/or parallel processing
subsystem 112 or as circuitry configured to perform the method
steps shown in FIG. 6A. The path stroke engine approximates cubic
Bezier curves and any higher order curves with quadratic Bezier
path segments and lower order path segments. The path stroke engine
determines if each path segment is a degenerate line or within an
epsilon of being so, and if it is, the path segment is approximated
by a line segment. The path stroke engine also identifies line
segments (including line segments generated by the path stroke
engine from degenerate lines) in the path and converts the
identified line segments to rectangles. The path stroke engine also
identifies path commands for curved segments other than cubic
Bezier segments and converts such curved segments into an
approximating sequence of quadratic Bezier curves, as described in
conjunction with FIG. 6B.
[0109] At step 608 bounding hull geometry is generated by the path
stroke engine for the quadratic Bezier path segment. At step 610
per-quadratic Bezier path segment parameters computed by the path
stroke engine. The per-quadratic Bezier path segment parameters may
be computed by the CPU 102. At step 615 the per-quadratic Bezier
path segment parameters are processed by the path stroke engine to
determine which points are within the stroke region of each
quadratic Bezier path segment. The quadratic path segment stroke
containment involves solving of a particular cubic equation for
each point so this computation is typically considerably more
expensive than the computations required to rasterize primitive
such as rectangles or triangles. In one embodiment, the
per-quadratic Bezier path segment parameters are processed by a
combination of a vertex shader program and a fragment shader
program executed by the parallel processing subsystem 112.
[0110] At step 620 the path stroke engine determines if the path to
be stroked includes another quadratic Bezier path segment, and, if
so, then steps 608, 610, and 615 are repeated. Otherwise, at step
625 stroking of the path is complete. In one embodiment, the
fragment shader is configured to discard fragments not within the
quadratic Bezier path segment and thereby avoid writing a stencil
buffer to indicate whether or not each pixel is within the stroke
region of a path. One or more geometric hulls that conservatively
cover the entire path are generated and rendered to fill the stroke
region by writing the color buffer based on the stencil buffer. In
another embodiment, the stroke region is filled by writing the
color buffer as the hull geometry for each quadratic Bezier path
segment is processed.
[0111] FIG. 6B is a flow diagram of method steps for approximating
a curved path including a cubic Bezier segment into one or more
quadratic Bezier curve segments as performed in method step 605
shown in FIG. 6A, according to one embodiment of the present
invention. At step 640 the path stroke engine identifies key
features of the path, e.g., locations of cusps, self-intersections,
and points of maximum curvature. At step 642 the path stroke engine
replaces collinear cubic Bezier curve segments with line segments.
At step 645 the path stroke engine subdivides the generating curve,
i.e., path, at the key features.
[0112] At step 650 the path stroke engine fits quadratic Bezier
curve segments to the endpoints and tangents of the cubic Bezier
path segments included in the curve. Importantly, geometric tangent
continuity is maintained during the fitting of the quadratic Bezier
curve segments. At step 655 the path stroke computes a variance
metric and a deviation value that quantifies the accuracy of an
approximating quadratic Bezier curve segment. At step 660 the path
stroke engine determines if the deviation value is within an
acceptable tolerance based on the stroke width or a maximum number
of subdivisions, and, if not, at step 665 the quadratic Bezier
curve segment is subdivided and steps 650, 655, and 660 are
repeated for each new quadratic Bezier curve segment. Otherwise, at
step 670 the path stroke engine determines if another approximating
quadratic Bezier curve segment should be compared with the
originating the cubic Bezier path segment for accuracy. If another
quadratic Bezier curve segment should be compared, then the path
stroke engine repeats steps 655 and 660. Otherwise, all of the
approximating quadratic Bezier curve segments meet the accuracy
constraints and the path stroke engine proceeds to step 608.
[0113] Because the geometry set used to produce the stroked path is
resolution-independent, the stroked path can be rasterized under
arbitrary projective transformations without needing to revisit the
construction of the geometry set. This resolution-independent
property is unlike geometry sets built through a process of
tessellating curved regions into triangles; in such circumstances,
sufficient magnification of the filled path would reveal the
tessellated underlying nature of such a tessellated geometry set.
The approximating quadratic Bezier curve segments are also compact,
meaning that the number of bytes required to represent the stroked
path is linear with the number of quadratic Bezier path segments
generated by original path. This property does not generally hold
for tessellated versions of stroked paths where the process of
subdividing curved edges and introducing tessellated triangles
typically increases the size of the resulting geometry set
considerably.
[0114] One embodiment of the invention may be implemented as a
program product for use with a computer system. The program(s) of
the program product define functions of the embodiments (including
the methods described herein) and can be contained on a variety of
computer-readable storage media. Illustrative computer-readable
storage media include, but are not limited to: (i) non-writable
storage media (e.g., read-only memory devices within a computer
such as CD-ROM disks readable by a CD-ROM drive, flash memory, ROM
chips or any type of solid-state non-volatile semiconductor memory)
on which information is permanently stored; and (ii) writable
storage media (e.g., floppy disks within a diskette drive or
hard-disk drive or any type of solid-state random-access
semiconductor memory) on which alterable information is stored.
[0115] The invention has been described above with reference to
specific embodiments. Persons skilled in the art, however, will
understand that various modifications and changes may be made
thereto without departing from the broader spirit and scope of the
invention as set forth in the appended claims. The foregoing
description and drawings are, accordingly, to be regarded in an
illustrative rather than a restrictive sense.
* * * * *