U.S. patent application number 13/114253 was filed with the patent office on 2011-11-24 for field effect transistor with trench filled with insulating material and strips of semi-insulating material along trench sidewalls.
This patent application is currently assigned to Fairchild Semiconductor Corporation. Invention is credited to Steven Sapp, Peter H. Wilson.
Application Number | 20110284955 13/114253 |
Document ID | / |
Family ID | 30443472 |
Filed Date | 2011-11-24 |
United States Patent
Application |
20110284955 |
Kind Code |
A1 |
Sapp; Steven ; et
al. |
November 24, 2011 |
FIELD EFFECT TRANSISTOR WITH TRENCH FILLED WITH INSULATING MATERIAL
AND STRIPS OF SEMI-INSULATING MATERIAL ALONG TRENCH SIDEWALLS
Abstract
In accordance with an embodiment of the present invention, a
MOSFET includes a first semiconductor region having a first
surface, a first insulation-filled trench region extending from the
first surface into the first semiconductor region, and strips of
semi-insulating material along the sidewalls of the first
insulation-filled trench region. The strips of semi-insulating
material may be insulated from the first semiconductor region.
Inventors: |
Sapp; Steven; (Felton,
CA) ; Wilson; Peter H.; (Boulder Creek, CA) |
Assignee: |
Fairchild Semiconductor
Corporation
San Jose
CA
|
Family ID: |
30443472 |
Appl. No.: |
13/114253 |
Filed: |
May 24, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11862396 |
Sep 27, 2007 |
7977744 |
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13114253 |
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10931887 |
Aug 31, 2004 |
7291894 |
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11862396 |
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10200056 |
Jul 18, 2002 |
6803626 |
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10931887 |
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Current U.S.
Class: |
257/334 ;
257/E27.062 |
Current CPC
Class: |
H01L 29/7802 20130101;
H01L 29/407 20130101; H01L 29/0653 20130101; H01L 29/405 20130101;
H01L 29/7811 20130101; H01L 29/0649 20130101; H01L 29/0634
20130101; H01L 29/0619 20130101; H01L 29/7813 20130101 |
Class at
Publication: |
257/334 ;
257/E27.062 |
International
Class: |
H01L 27/092 20060101
H01L027/092 |
Claims
1.-38. (canceled)
39. A MOSFET comprising: a first semiconductor region having a
first surface; a first insulation-filled trench region extending
from the first surface into the first semiconductor region, the
first insulation-filled trench region having sidewalls and a bottom
surface; strips of semi-insulating material extending along the
sidewalls of the first insulation-filled trench region but not over
at least a center portion of the bottom surface of the first
insulation-filled trench region, the strips of semi-insulating
material being insulated from the first semiconductor region; and
an insulating material extending over at least the center portion
of the bottom surface of the first insulation-filled trench
region.
40. The MOSFET of claim 39 further comprising: a second
insulation-filled trench region extending from the first surface
into the first semiconductor region, the second insulation-filled
trench region having sidewalls and a bottom surface, the second
insulation-filled trench region having strips of semi-insulating
material extending along its sidewalls but not over at least a
center portion of the bottom surface of the second
insulation-filled trench region, the strips of semi-insulating
material being insulated from the first semiconductor region, the
second insulation-filled trench region having an insulating
material extending over at least the center portion of the bottom
surface of the second-insulation-filled trench region, wherein the
first and second insulation-filled trench regions are spaced apart
in the first semiconductor region to form a drift region
therebetween, the volume of each of the first and second
insulation-filled trench regions being greater than one-quarter of
the volume of the drift region.
41. The MOSFET of claim 39 further comprising: a body region
extending from the first surface into the first semiconductor
region, the body region being of a conductivity type opposite that
of the first semiconductor region; a source region in the body
region, the source region being of the same conductivity type as
the first semiconductor region; a second trench region extending
from the first surface into the first semiconductor region; and a
gate in the second trench region extending across a portion of the
body region and overlapping the source and the first semiconductor
regions such that a channel region extending perpendicularly to the
first surface is formed in the body region between the source and
first semiconductor regions.
42. The MOSFET of claim 39 further comprising: first and second
body regions each extending from the first surface into the first
semiconductor region, the first body region being laterally spaced
from the second body region to form a JFET region therebetween, the
first and second body regions being of a conductivity type opposite
that of the first semiconductor region; and first and second source
regions in the first and second body regions respectively, the
first and second source regions being of the same conductivity type
as the first semiconductor region.
43. The MOSFET of claim 42 further comprising a gate extending over
but being insulated from the JFET region and a portion of the first
and second body regions, and overlapping the first and second
source regions such that a channel region is formed along a body
surface of each of the first and second body regions between the
corresponding source and JFET regions.
44. The MOSFET of claim 42 further comprising: a gate extending
over but being insulated from each of the first and second body
regions such that a channel region is formed along a surface of
each of the first and second body regions between the corresponding
source and JFET regions, the gate being discontinuous over a
surface of the JFET region between the first and second body
regions.
45. The MOSFET of claim 39 wherein the strips of semi-insulating
material are from oxygen-doped polysilicon material.
46. The MOSFET of claim 39 further comprising a source region,
wherein the strips of semi-insulating material are electrically
connected to the source regions.
47. The MOSFET of claim 39 wherein each of the strips of
semi-insulating material is insulated from its surrounding
regions.
48. The MOSFET of claim 39 wherein each of the strips of
semi-insulating material is floating.
49. The MOSFET of claim 39 further comprising a drain and a source,
each of the strips of semi-insulating material being electrically
coupled between the drain and the source.
50. The MOSFET of claim 39 further comprising a drain and a source,
each of the strips of semi-insulating material being electrically
coupled between the drain and the source so that during an
operating mode of the MOSFET each of the strips of semi-insulating
material acquires a linear voltage gradient from one end of the
strip to an opposite end of the strip.
51. The MOSFET of claim 39 wherein: the first semiconductor region
is over and in contact with a second semiconductor region of same
conductivity type as the first semiconductor region, the second
semiconductor region having a higher doping concentration than the
first semiconductor region, and the strips of semi-insulating
material extending through the first semiconductor region and
terminating in the second semiconductor region.
52. The MOSFET of claim 39 wherein: the first semiconductor region
is over and in contact with a second semiconductor region of same
conductivity type as the first semiconductor region, the second
semiconductor region having a higher doping concentration than the
first semiconductor region, and the first insulation-filled trench
extending through the first semiconductor region and terminating in
the second semiconductor region.
53-71. (canceled)
72. The MOSFET of claim 39 wherein a resistivity of at least one of
the strips of semi-insulating material varies from one end of the
strip to an opposite end of the strip proximal the bottom surface
of the first insulation-filled trench region.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a division of U.S. application Ser. No.
11/862,396, filed Sep. 27, 2007, which is a division of U.S.
application Ser. No. 10/931,887, filed Aug. 31, 2004, which is a
division of U.S. application Ser. No. 10/200,056, filed Jul. 18,
2002. The disclosures of U.S. application Ser. Nos. 10/200,056 and
11/862,396 are incorporated herein by reference for all
purposes.
BACKGROUND OF THE INVENTION
[0002] Power field effect transistors, e.g., MOSFETs (metal oxide
semiconductor field effect transistors), are well known in the
semiconductor industry. One type of power MOSFET is a DMOS
(double-diffused metal oxide semiconductor) transistor. A
cross-sectional view of a portion of a cell array of one known
variety of DMOS transistors is shown in FIG. 1. As shown, an n-type
epitaxial layer 102 overlies n-type substrate region 100 to which
the drain contact is made. Polysilicon-filled trenches extend into
the epitaxial layer 102 from the top surface. The polysilicon 106a,
106b in the trenches are insulated from the epitaxial layer by
oxide layers 104a, 104b. Source regions 108a, 108b in p-type body
regions 110a, 110b are adjacent the trenches at the top surface. A
polysilicon gate 114 overlaps the source regions 108a,b, extends
over a surface portion of the body regions 110a,b, and extends over
a surface area of a region between the two trenches commonly
referred to as the mesa drift region. Metal layer 116 electrically
shorts source regions 108a,b to body regions 110a,b and polysilicon
106a,b in the trenches. The surface area of body regions 110a,b
directly underneath gate 114 defines the transistor channel region.
The area between body regions 110a and 110b under gate 114 is
commonly referred to as the JFET region.
[0003] Upon applying a positive voltage to the gate and the drain,
and grounding the source and the body regions, the channel region
is inverted. A current thus starts to flow from the drain to the
source through the drift region and the surface channel region.
[0004] A maximum forward blocking voltage, hereinafter referred to
as "the breakdown voltage", is determined by the avalanche
breakdown voltage of a reverse-biased body-drain junction. The DMOS
structure in FIG. 1 has a high breakdown voltage due to the
polysilicon-filled trenches. Polysilicon 106a,b cause the depletion
layer formed as a result of the reverse-biased body-drain junction
to be pushed deeper into the drift region. By increasing the
depletion region depth without increasing the electric field, the
breakdown voltage is increased without having to resort to reducing
the doping concentration in the drift region which would otherwise
increase the transistor on-resistance.
[0005] A drawback of the FIG. 1 structure is its high output
capacitance Coss, making this structure less attractive for high
frequency applications such as radio frequency (RF) devices for
power amplifiers in the wireless communication base stations. The
output capacitance Coss of the FIG. 1 structure is primarily made
up of: (i) the capacitance across the oxide between the polysilicon
in the trenches and the drift region (i.e., Cox), in series with
(ii) the capacitance across the depletion region at the body-drift
region junction. Cox is a fixed capacitance while the depletion
capacitance is inversely proportional to the body-drain bias.
[0006] The breakdown voltage of power MOSFETs is dependent not only
upon the cell structure but also on the manner in which the device
is terminated at its outer edges. To achieve a high breakdown
voltage for the device as a whole, the breakdown voltage at the
outer edges must be at least as high as that for the cells. Thus,
for any cell structure, a corresponding terminating structure is
needed which exhibits a high breakdown voltage.
[0007] In most amplifier circuits a significant amount of heat
energy is produced in the transistor. Only 50% efficiency is
typical of the best class AB RF power amplifiers available. An
important factor in designing power devices for high frequency
applications is thus the thermal performance of the device. Because
of the different device performance requirements, the cells in
power MOSFETs are densely packed resulting in concentration of heat
in active regions and poor heat transfer rates. The increase in
temperature resulting from the poor heat transfer rate adversely
effects the device performance.
[0008] Thus, a power MOSFET device with such improved
characteristics as low output capacitance, high breakdown voltage,
and improved thermal performance is desired.
BRIEF SUMMARY OF THE INVENTION
[0009] In accordance with the present invention, MOSFET cell
structures and edge termination structures, and methods of
manufacturing the same, are described which among other features
and advantages exhibit a substantially reduced output capacitance,
high breakdown voltage, and improved thermal performance.
[0010] In one embodiment, a MOSFET comprises at least two
insulation-filled trench regions laterally spaced in a first
semiconductor region to form a drift region therebetween, and at
least one resistive element located along an outer periphery of
each of the two insulation-filled trench regions. A ratio of a
width of each of the insulation-filled trench regions to a width of
the drift region is adjusted so that an output capacitance of the
MOSFET is minimized.
[0011] In another embodiment, a MOSFET comprises a first
semiconductor region having a first surface, a first trench region
extending from the first surface into the first semiconductor
region, and at least one floating discontinuous region along a
sidewall of the first trench region.
[0012] In another embodiment, a MOSFET comprises a first
semiconductor region having a first surface, a first trench region
extending from the first surface into the first semiconductor
region, and a first plurality of regions along a sidewall of the
first trench region.
[0013] In another embodiment, a MOSFET comprises a first
semiconductor region having a first surface, and first and second
insulation-filled trench regions each extending from the first
surface into the first semiconductor region. Each of the first and
second insulation-filled trench regions has an outer layer of
silicon of a conductivity type opposite that of the first
semiconductor region. The first and second insulation-filled trench
regions are spaced apart in the first semiconductor region to form
a drift region therebetween such that the volume of each of the
first and second trench regions is greater than one-quarter of the
volume of the drift region.
[0014] In another embodiment, a MOSFET comprises a first
semiconductor region over a substrate. The first semiconductor
region has a first surface. The MOSFET further includes first and
second insulation-filled trench regions each extending from the
first surface to a predetermined depth within the first
semiconductor region. Each of the first and second
insulation-filled trench regions has an outer layer of doped
silicon material which is discontinuous along a bottom surface of
the insulation-filled trench region so that the insulation material
along the bottom surface of the insulation-filled trench region is
in direct contact with the first semiconductor region. The outer
layer of silicon material is of a conductivity type opposite that
of the first semiconductor region.
[0015] In another embodiment, a MOSFET comprises a first
semiconductor region having a first surface, a first
insulation-filled trench region extending from the first surface
into the first semiconductor region, and strips of semi-insulating
material along the sidewalls of the first insulation-filled trench
region. The strips of semi-insulating material are insulated from
the first semiconductor region.
[0016] In accordance with an embodiment of the present invention, a
MOSFET is formed as follows. A first epitaxial layer is formed over
a substrate. A first doped region is formed in the first epitaxial
layer. The first doped region has a conductivity type opposite that
of the first epitaxial layer. A second epitaxial layer is formed
over the first doped region and the first epitaxial region. A first
trench region is formed which extends from a surface of the second
epitaxial layer through the first and second epitaxial layers and
the first doped region such that the first doped region is divided
into two floating discontinuous regions along sidewalls of the
first trench region.
[0017] In another embodiment, a MOSFET is formed as follows. A
first epitaxial layer is formed over a substrate. First and second
doped regions are formed in the first epitaxial layer. The first
and second doped regions have a conductivity type opposite that of
the first epitaxial layer. A second epitaxial layer is formed over
the first and second doped regions and the first epitaxial region.
First and second trench regions are formed wherein the first trench
region extends through the first and second epitaxial layers and
the first doped region such that the first doped region is divided
into two floating discontinuous regions along sidewalls of the
first trench region, and the second trench region extends through
the first and second epitaxial layers and the second doped region
such that the second doped region is divided into two floating
discontinuous regions along sidewalls of the second trench
region.
[0018] In another embodiment, a MOSFET is formed as follows. A
first trench is formed in a first semiconductor region. A first
doped region is formed along a bottom of the first trench. The
first trench is extended deeper into the first semiconductor region
such that of the first doped region two floating discontinuous
regions remain along sidewalls of the first trench.
[0019] In another embodiment, a MOSFET is formed as follows. A
first semiconductor region is formed over a substrate. The first
semiconductor region has a first surface. A first trench is formed
which extends from the first surface to a predetermined depth
within the first semiconductor region. A layer of doped silicon
material is formed along sidewalls of the trench. The layer of
doped silicon material is of a conductivity type opposite that of
the first semiconductor region.
[0020] The following detailed description and the accompanying
drawings provide a better understanding of the nature and
advantages of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] FIG. 1 shows a cross-sectional view of a cell array of a
known n-channel DMOS transistor;
[0022] FIG. 2 shows a cross-sectional view of a cell array with
floating p regions in accordance with one embodiment of the present
invention;
[0023] FIGS. 3-1a through 3-1e are cross-sectional views showing an
exemplary set of process steps for forming the structure in FIG.
2;
[0024] FIGS. 3-2a through 3-2e are cross-sectional views showing
another exemplary set of process steps for forming the structure in
FIG. 2;
[0025] FIG. 4 shows a cross-sectional view of a cell array having
elongated floating p regions in accordance with another embodiment
of the present invention;
[0026] FIG. 5 shows a cross-sectional view of a cell array having a
wide insulation-filled trench in accordance with yet another
embodiment of the present invention;
[0027] FIG. 6 shows a cross-sectional view of a cell array having
insulation-filled trenches with a thin p layer along its outer
perimeter in accordance with another embodiment of the present
invention;
[0028] FIG. 7 shows a cross-sectional view of a cell array with
wide trenches;
[0029] FIG. 8 shows a cross-sectional view of a cell array with p
strips along sidewalls of the trenches, in accordance with another
embodiment of the present invention;
[0030] FIGS. 9a through 9e are cross-sectional views showing an
exemplary set of process steps for forming the structure in FIG.
8;
[0031] FIGS. 10a, 10b, and 10c show cross-sectional views of cell
arrays having strips of semi-insulating material along sidewalls of
trenches in accordance with three embodiments of the present
invention;
[0032] FIG. 11 shows a cross sectional view of a cell array wherein
the trench structure shown in FIG. 8 is combined with a gate
structure different than that shown in FIG. 8;
[0033] FIG. 12 shows a cross sectional view of a cell array wherein
the trench structure shown in FIG. 8 is combined with yet another
gate structure;
[0034] FIG. 13 shows a cross-sectional view of an edge termination
structure in accordance with one embodiment of the present
invention; and
[0035] FIG. 14 shows a cross-sectional view of another edge
termination structure in accordance with another embodiment of the
present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0036] MOSFET cell structures, edge termination structures, and
methods of manufacturing the same are described in accordance with
the present invention. Among other features and advantages, the
cell and termination structures and methods of manufacturing the
same exhibit a substantially reduced output capacitance, high
breakdown voltage, and improved thermal performance.
[0037] FIG. 2 shows a cross-sectional view of a power MOSFET cell
array in accordance with an embodiment of the present invention. As
shown, both gate terminal 205 and source terminal 207 are located
along the top-side of the device, and drain terminal 203 is located
along the bottom-side. Drain terminal 203 is coupled to the
lightly-doped epitaxial region 202 through a highly doped region
200 serving as the drain contact. Oxide-filled trench regions 204a,
204b extend from the top-side to a predetermined depth in the
epitaxial region 202. Discontinuous floating p-type regions 206a,
206b are spaced along an outer sidewall of trench regions 204a,b.
P-type body regions 208a, 208b extend from the top-side into the
epitaxial region adjacent trench regions 204a,b. As shown, body
regions 208a,b include highly-doped p+ regions 210a,b, although
these p+ regions may be eliminated if desired. Source regions
212a,b are formed in body regions 208a,b as shown.
[0038] Polysilicon gates 216 overlap source regions 212a,b, extend
over the surface area of body regions 208a,b and over the surface
area of epitaxial region 202 between body regions 208a and 208b.
Gates 216 are insulated from the underlying regions by gate oxide
214. The surface area of body regions 208a,b directly under gates
216 form the channel regions. Metal layer 218 overlies the top-side
of the structure and forms the common source-body contact.
[0039] The area of the epitaxial region between trenches 204a and
204b is hereinafter referred to as drift region 209. When proper
biasing is applied to the gate, drain, and source terminals to turn
on the device, current flows between drain terminal 203 and source
terminal 207 through drain contact region 200, drift regions 209,
the channel regions, source diffusion regions 212a,b, and finally
metal layer 218.
[0040] Comparing FIGS. 1 and 2, it can be seen that the polysilicon
106a,b (FIG. 1) in the trenches are replaced with insulating
material, thus eliminating the significant contributor to the
output capacitance of the FIG. 1 structure, namely, Cox. By
replacing the polysilicon with an insulator such as
silicon-dioxide, a greater portion of the space charge region
appears across an insulator rather than silicon. Because the
permitivity of insulator is lower than that of silicon (in the case
of silicon-dioxide, a factor of about three lower), and the area of
the space charge region along its boundaries is reduced (especially
when the application voltage is low), the output capacitance is
significantly reduced (by at least a factor of three).
[0041] As described above, the polysilicon in the trenches of the
prior art FIG. 1 structure helps improve the cell breakdown voltage
by pushing the depletion region deeper into the drift region.
Eliminating the polysilicon would thus result in lowering the
breakdown voltage unless other means of reducing the electric field
are employed. Floating p regions 206a,b serve to reduce the
electric field. In FIG. 2, as the electric field increases with the
increasing drain voltage, floating p regions 206a,b acquire a
corresponding potential determined by their position in the space
charge region. The floating potential of these p regions causes the
electric field to spread deeper into the drift region resulting in
a more uniform field throughout the depth of the drift region and
thus in a higher breakdown voltage. Accordingly, similar breakdown
voltage characteristics to that of the FIG. 1 structure is achieved
but with much reduced output capacitance.
[0042] Floating p regions 206a,b have the adverse effect of
reducing the width of drift regions 209 through which current flows
when the device is in the on-state, and thus result in increased
on-resistance. However, the adverse impact of the floating p
regions on the on-resistance can be reduced by obtaining an optimum
balance between the charge concentration in the drift region and
such features of the floating p regions as size, doping
concentration, and the spacing Lp between them. For example, a
higher charge concentration in the drift region would require a
smaller spacing Lp and vice versa. Further, because the floating p
regions reduce the electric field near the surface in the channel,
the channel length can be reduced to improve the on-resistance and
the general performance of the device as a high frequency
amplifier.
[0043] In one embodiment wherein a breakdown voltage of 80-100V is
desired, epitaxial region 202 has a doping concentration in the
range of 5.times.10.sup.15 to 1.times.10.sup.16 cm.sup.-3 and the
floating p regions 206a,b have a doping concentration of about 5-10
times that of the epitaxial region.
[0044] FIGS. 3-1a through 3-1e are cross-sectional views showing an
exemplary set of process steps for forming the structure in FIG. 2.
In FIG. 3-1a, a first n-epitaxial layer 302 is deposited on a
heavily-doped substrate 300 using conventional methods. P regions
306, 308 are formed by implanting p-type impurities (such as Boron)
through a mask 304. The size of the opening in mask 304 is
dependent upon the desired width of the trenches and the desired
width of the floating p regions which are in turn dictated by the
device performance targets. In one embodiment, the target width of
the trench is in the range of 1-5 .mu.m, the width of p regions
306, 308 is at least 1 .mu.m wider than the trench width, the
lateral spacing between adjacent p regions 306 and 308 is no less
than 1 .mu.m, and n-epitaxial layer 302 has a doping concentration
of about 2.times.10.sup.16 cm.sup.-3 and a thickness in the range
of 2-5 .mu.m.
[0045] In FIG. 3-1b, similar steps to those in FIG. 3-1a are
carried out to from a second n-epitaxial layer 316 and p regions
310, 312. These steps can be repeated depending on the desired
number of floating p regions. Alternatively, the steps in FIG. 3-1b
may be eliminated to form only a single floating p region along
each trench sidewall.
[0046] In FIG. 3-1c, a final epitaxial layer 320 to receive the
device body and source regions is deposited. While the deposition
technique used in forming epitaxial regions 302, 316, and 320 is
the same, the doping concentration of each epitaxial region can be
varied depending on the desired characteristics of the drift
region. Similarly, p regions 306, 308 may be implanted to have a
different doping concentration than p regions 310, 312 if
desired.
[0047] In FIG. 3-1d, mask 330 and conventional silicon trench
etching techniques are used to etch through the three epitaxial
layers 302, 316, 320 and through the center portion of the p
regions 306, 308, 310, 312 to form trenches 322a, 322b and
corresponding floating p regions 306a,b, 308a,b, 310a,b, and
312a,b. The width of the openings in mask 330 determines the width
of the oxide trenches relative to the width of the floating p
regions.
[0048] After preparation of the trench surface, a relatively thin
insulator (e.g., about 300-500 .ANG. of thermal oxide) is grown on
the trench surface. Trenches 322a,b are then filled with a
dielectric material such as silicon-dioxide using conventional
conformal coating method and/or Spin-On Glass (SOG) method. Any low
k dielectric to reduce the output capacitance may be used to fill
trenches 322a,b. Conventional process steps used in forming
self-aligned gate DMOS structures are then carried out to form the
gate structure as shown in FIG. 3e.
[0049] An alternate method of manufacturing the structure in FIG. 2
is described next using the simplified cross-sectional views in
FIGS. 3-2a through 3-2c. In FIG. 3-2a: an initial n-epitaxial layer
342 is deposited on a heavily-doped substrate 340; a trench 344a is
then formed in n-epitaxial layer 342; and an implant step is then
carried out to form a p region 346 at the bottom of trench 344a,
followed by a diffusion step to diffuse the p dopants further into
epitaxial region 342. In FIG. 3-2b: trench 344a is further etched
past p region 346 into epitaxial region 342 to form a deeper trench
344b; and similar implant and diffusion steps to those in FIG. 3-2a
are carried out to form p region 348 at the bottom of trench 344b.
In FIG. 3-2c: trench 344b is etched past p region 348 into
epitaxial layer 342 to form an even deeper trench 344c; and trench
344c is then filled with a suitable insulator. Thus, an
insulator-filled trench 344c and floating p regions 346a,b and
348a,b are formed. The remaining process steps would be similar to
those described in connection with FIG. 3-1e.
[0050] Referring back to FIG. 2, the vertical charge control
enabled by the floating p regions allows the cells to be laterally
spaced apart without impacting the electrical characteristics of
the device. With the cells spaced further apart, the heat generated
by each cell is distributed over a larger area and less heat
interaction occurs between adjacent cells. A lower device
temperature is thus achieved.
[0051] To achieve effective vertical charge control, spacing Lp
(FIG. 2) between adjacent floating p regions 206a and 206b needs to
be carefully engineered. In one embodiment, spacing Lp is
determined in accordance with the following proposition: the
product of the doping concentration in the drift region and the
spacing Lp be in the range of 2.times.10.sup.12 to
4.times.10.sup.12 cm.sup.-2. Thus, for example, for a drift region
doping concentration of 5.times.10.sup.15 cm.sup.-3, the spacing Lp
needs to be about 4 .mu.m. Once an optimum spacing Lp is
determined, the spacing Lc between a center axis of adjacent
trenches 204a,b can be independently increased without impacting
the electrical characteristics of the device.
[0052] Two ways of achieving the increased Lc spacing while keeping
Lp spacing the same are shown in FIGS. 4 and 5. In FIG. 4,
discontinuous floating p regions 406a,b along with the source and
body regions are extended across a large portion of the area
between adjacent trenches to achieve a larger Lc spacing. In one
embodiment, a combined width Wt of one trench (e.g., 404b) and one
of the first plurality of floating regions (e.g., 406b) is greater
than one-quarter of the spacing Lp. The FIG. 4 embodiment is
particularly useful in technologies where the trench width Wt is
tightly limited to a maximum size. If the trench width is not
tightly limited, then the width of the trenches can be increased to
obtain a larger Lc spacing while keeping spacing Lp the same as
shown in FIG. 5.
[0053] An advantage of the FIG. 5 structure over that in FIG. 4 is
the lower output capacitance because of the smaller floating p
regions, and because a larger portion of the depletion region
occurs in the wider insulation-filled trenches. Thus, the reduction
in output capacitance due to the wider size of the trenches can be
promoted by designing the cell structure to have a high ratio of
trench insulation volume to drift region volume. A wider trench
also results in improved thermal performance. In one embodiment,
the volume of the insulation in the trench is at least one-quarter
of the volume of the drift region. Thus, the larger the trench
volume, the lower the output capacitance and the better the thermal
performance of the device. However, little is gained in making the
trench wider than the thickness of the die (e.g., 100 .mu.m).
[0054] Although FIGS. 2 through 5 show multiple floating p regions
along the trench sidewalls, the invention is not limited as such.
Depending on the device performance requirements and design goals,
only a single floating p region may be formed along each sidewall
of the trenches.
[0055] FIG. 6 shows a cross section view of a power MOSFET cell
array in accordance with another embodiment of the present
invention. The structure in FIG. 6 is similar to that in FIG. 2
except that floating p regions 206a,b (FIG. 2) are eliminated and p
layers (or p liners) 606a,b are introduced along the outer
perimeter of trenches 604a and 604b. Similar to floating p regions
206a,b, help spread the depletion region deeper into the drift
regions, thus improving the breakdown voltage. P liners 606a,b are
biased to the same potential as body regions 608a,b since they are
in electrical contact with body regions 608a,b.
[0056] In FIG. 7, as in FIG. 5, the width Wt of the oxide trench is
increased to achieve improved thermal performance, while the Lp
spacing is maintained at the same optimum value. A drawback of the
FIG. 7 structure is that p liners 706a,b result in higher output
capacitance since they cause the space charge region to follow the
entire contour of the trench. One approach in reducing the p
liners' contribution to the output capacitance is to eliminate that
portion of the p liners extending across the bottom of the
trenches, as shown in FIG. 8. In this manner, the output
capacitance is reduced while the same breakdown voltage is
maintained since p strips 806a,b (FIG. 8) spread the depletion
region deeper into the drift regions.
[0057] An exemplary set of process steps for forming the structure
of FIG. 8 is shown in FIGS. 9a through 9c. In FIG. 9a, a hard mask
906 along with conventional silicon trench etch methods are used to
etch epitaxial region 902 to form wide trenches 904a, 904b. Using
the same mask, p liners 908 are formed by implanting p-type
impurities at about a 45.degree. angle into both sidewalls and
bottom of the trenches using conventional methods. In FIG. 9b,
conventional silicon etch method is carried out to remove the
portion of the p liners along the bottom of the trenches, leaving p
strips 908a,b along the sidewalls of the trenches. In FIG. 9c, a
thermally-grown oxide layer 910a,b is formed along the inner
sidewalls and bottom of each trench. The p-type dopants in p strips
908a,b are then activated using conventional methods. Conventional
oxide deposition steps (e.g., SOG method) are carried out to fill
the trenches with oxide, followed by planarization of the oxide
surface. Conventional process steps used in forming the gate
structure in self-aligned gate DMOS structures are then carried out
to form the full structure as shown in FIG. 9c. Note that in the
FIGS. 7 and 8 structures the thermally grown oxide liners, similar
to those in FIG. 9c, are present but are not shown for simplicity.
The thermally grown oxide layers are included to provide a cleaner
interface between the trench insulator and the p strips.
[0058] From the above, it can be seen that manufacturing of the
FIG. 8 structure is less complex than that of the FIG. 5 structure
because of the extra steps required in forming the floating p
regions in the FIG. 5 structure.
[0059] The doping concentration in the p liners/strips in FIGS. 6-8
impacts the output capacitance of each of these structures.
Highly-doped p regions lead to higher output capacitance since a
higher reverse bias potential is needed to fully deplete these p
regions. Thus, a low doping concentration (e.g., of about
1.times.10.sup.17 cm.sup.-3) would be desirable for these p
regions. Note that these p regions have less effect on the output
capacitance at high operating voltages.
[0060] FIGS. 10a-10c show cross sectional views of three power
MOSFET cell arrays each of which includes strips of semi-insulating
material (e.g., oxygen-doped polysilicon SiPOS) along the trench
sidewalls. In all three figures, wide insulation-filled trenches
1004a,b are used to achieve improved thermal performance as in
previous embodiments. Also, the semi-insulating strips in these
structures function similar to polysilicon 106a,b in the prior art
FIG. 1 in pushing the depletion region deeper into the drift
region, thus improving the breakdown voltage.
[0061] In FIG. 10a, strips 1006a,b of semi-insulating material
extend along the trench sidewalls and are insulated from epitaxial
region 1002 and body regions 1008a,b by a layer of insulating
material 1010a,b. Strips 1006a,b are in electrical contact with the
top metal layer 1018, and thus are biased to the same potential as
the source and body regions.
[0062] In FIG. 10b, strips 1020a,b of semi-insulating material are
integrated in the cell array in a similar manner to those in FIG.
10a except that strips 1020a,b are insulated from the top metal
layer 1018 and thus are floating. During operation, the potential
in the space charge region couples to the semi-insulating strips
through insulation layers 1010a,b to bias the strips to a
corresponding mostly uniform potential.
[0063] In FIG. 10c, the insulation-filled trenches 1024a,b extend
all the way through epitaxial region 1002 and terminate in
substrate 1000. Semi-insulating strips 1022a,b extend along the
sidewalls of the trenches and electrically contact the source
terminal through the top metal layer 1018 and the drain terminal
through substrate region 1000. Thus, the strips form a resistive
connection between drain and source terminals. During operation,
the strips acquire a linear voltage gradient with the highest
potential (i.e., drain potential) at their bottom to lowest
potential (i.e., source potential) at their top. Strips 1022a,b are
insulated from epitaxial regions 1002 by insulating layers 1026a,b.
The gate structure in FIG. 10c as well as in FIGS. 10a and 10b is
similar to the previous embodiments.
[0064] The semi-insulating strips in the structures of FIGS.
10a-10c serve as an additional tool by which the electrical
characteristics of the device can be optimized. Depending on the
application and the design targets, one structure may be preferred
over the other. The resistivity of the strips of semi-insulating
material in each of the FIGS. 10a, 10b, 10c structures can be
adjusted and potentially varied from the top to the bottom to
enable shaping of the space charge region formation in response to
the applied drain-source voltage V.sub.DS.
[0065] An exemplary set of process steps for forming the structure
in FIG. 10a is as follows. A hard mask is used to etch the silicon
back to form wide trenches as in previous embodiments with wide
trenches. A layer of thermally grown oxide having a thickness in
the range of 200-1000 .ANG. is then formed along the inner walls
and bottom of the trench. About 4000 .ANG. of conformal oxide is
then deposited over the thermally grown oxide layer. Oxygen-doped
polysilicon (SiPOS) is then deposited in the trench regions and
etched to form strips 1008a,b along the sidewalls. The trenches are
then filled with insulation using conventional methods (e.g., SOG
method), followed by planarization of the oxide surface.
Conventional steps used in forming self-aligned gate DMOS
structures are then carried out to form the full cell structure as
shown in FIG. 10a.
[0066] The depth of the trenches in the different embodiments
described above may vary depending on the desired device
performance and the target application for the device. For example,
for high breakdown voltage (e.g., greater than 70V), the trenches
may be extended deeper into the epitaxial region (e.g., to a depth
of about 5 .mu.m). As another example, the trenches can be extended
all the way through the epitaxial region to meet the substrate
regions (as in FIG. 10c). For lower voltage applications, the p
regions (e.g., the floating p regions in FIG. 2 and the p strips in
FIG. 8) need not extend deep into the epitaxial region since the
device is not required to meet high breakdown voltages, and also to
minimize the contribution of the p regions to the output
capacitance.
[0067] Although the trench structures in the different embodiments
described above are shown in combination with the gate structure of
conventional DMOS cells, the invention is not limited as such. Two
examples of other gate structures with which these trench
structures may be combined are shown in FIGS. 11 and 12. These two
cell structures have the benefit of lower gate to drain capacitance
which in combination with the low output capacitance of the trench
structures yields power devices particularly suitable for high
frequency applications.
[0068] The FIG. 11 structure is similar to that in FIG. 8 except
that a substantial portion of the gate extending over the surface
of the drift region is eliminated. Thus, the gate to drain
capacitance is reduced by an amount corresponding to the eliminated
portion of the gate. In the FIG. 12 structure, the trench structure
in FIG. 8 is combined with the gate structure of a conventional
UMOS cell. Thus, the advantages of the UMOS cell (e.g., low
on-resistance) are obtained while the low output capacitance and
improved thermal performance of the trench structure in accordance
with the present invention are maintained. In one embodiment
wherein the FIG. 12 structure is intended for lower voltage
applications (e.g., in the range 30-40V) the depth of p strips
1208a,b is relatively shallow (e.g., in the range of 1.5 .mu.m to 3
.mu.m).
[0069] Combining the gate structures in FIGS. 11 and 12 or any
other gate structure with the different trench structures described
above would be obvious to one skilled in this art in view of this
disclosure.
[0070] In the above embodiments, the vertical charge control
enabled by the resistive elements located along the
insulation-filled trenches allows the cells to be laterally spaced
apart without impacting the electrical characteristics of the
device. With the cells spaced further apart, the heat generated by
each cell is distributed over a larger area and less heat
interaction occurs between adjacent cells. A lower device
temperature is thus achieved.
[0071] Although the above embodiments show the drain to be located
along the bottom-side of the die, the invention is not limited as
such. Each of the above cell structures can be modified to become a
quasi-vertically conducting structure by including a highly-doped
n-type buried layer extending along the interface between the
epitaxial region and the underlying highly-doped substrate region.
At convenient locations, the buried layer is extended vertically to
the top surface where it can be contacted to form the drain
terminal of the device. In these embodiments, the substrate region
may be n-type or p-type depending on the application of the
MOSFET.
[0072] As mentioned earlier, edge termination structures with
breakdown voltages equal to or greater than that of the individual
cells are required to achieve a high device breakdown voltage. In
the case of the FIG. 8 structure, simulation results indicate that
terminating at the outer edge of the device with a trench structure
like trench 804b would result in higher electric fields due to the
electric field transition up to the top surface at the outside of
the outer trench. An edge termination structure which yields the
same or higher breakdown voltage than the cell structure in FIG. 8
is shown in FIG. 13.
[0073] In FIG. 13, the active gate over the drift region between
the outer two trenches 1306b and 1306c is eliminated allowing the
drift region spacing Lt between these outer two trenches to be
reduced to less than the drift region spacing Lc in the cell
structures. The active gate however may be left in if obtaining the
Lt spacing does not require its removal. The outer p strip 1308d is
not biased (i.e., is floating), and may be eliminated if desired. A
conventional field plate structure 1310 is optionally included in
FIG. 13. The termination structure in FIG. 13 results in: (a) the
depletion region terminating within the outer trench 1306c, thus
reducing the electric field at the outside of trench 1306c, and (b)
the field on the inside of outer trench 1306c is reduced due to
short Lt spacing pushing the depletion region into the drift
region.
[0074] In another embodiment, the gate structure is included
between trenches 1306b and 1306c, with spacing Lt equaling spacing
Lc. In this embodiment, the p strip immediately to the right of the
gate structure between trenches 1306b and 1306c (i.e., the p strip
corresponding to the strip along the left side of trench 1306c) is
not connected to the source and thus floats.
[0075] Other variations of the FIG. 13 embodiment are possible. For
example, floating guard-rings may be used on the outside of trench
1306c with or without field plate structure 1310. Although cell
trenches 1306a,b and termination trench 1306c are shown to be
narrower than the cell trenches in FIG. 8, trenches 1306a,b,c may
be widened as in FIG. 8. Further, the width Wt of termination
trench 1306c may be designed to be different than cell that of
trenches 1306a,b if desired.
[0076] FIG. 14 is a cross sectional view showing another
termination structure in combination with the cell structure shown
in FIG. 8. As shown, the termination structure includes a
termination trench 1408 lined with an insulation layer 1410 along
its sidewalls and bottom. A field plate 1406 (e.g., from doped
polysilicon) is provided over insulation layer 1410 in trench 1408,
and extends laterally over the surface and away from the active
regions.
[0077] Although the above-described termination structures are
shown in combination with the cell structure in FIG. 8, these and
other known termination structures may be combined with any of the
cell structures described above.
[0078] While the above is a complete description of the embodiments
of the present invention, it is possible to use various
alternatives, modifications and equivalents. For example, the
different embodiments described above are n-channel power MOSFETs.
Designing equivalent p-channel MOSFETs would be obvious to one
skilled in the art in light of the above teachings. Further, p+
regions, similar to p+ regions 210a,b in the FIG. 2 structure, may
be added in the body regions of the other structures described
herein to reduce the body resistance and prevent punch-through to
the source. Also, the cross sectional views are intended for
depiction of the various regions in the different structures and do
not necessarily limit the layout or other structural aspects of the
cell array. Therefore, the scope of the present invention should be
determined not with reference to the above description but should,
instead, be determined with reference to the appended claim, along
with their full scope of equivalents.
* * * * *