U.S. patent application number 13/078869 was filed with the patent office on 2011-11-10 for output current distortion compensating apparatus in inverter.
This patent application is currently assigned to LSIS CO., LTD.. Invention is credited to Kwang Yeon KIM.
Application Number | 20110273914 13/078869 |
Document ID | / |
Family ID | 44888155 |
Filed Date | 2011-11-10 |
United States Patent
Application |
20110273914 |
Kind Code |
A1 |
KIM; Kwang Yeon |
November 10, 2011 |
OUTPUT CURRENT DISTORTION COMPENSATING APPARATUS IN INVERTER
Abstract
An output current distortion compensating apparatus in an
inverter is disclosed, the inverter including an inverter
controller generating a PWM signal for controlling a PWM voltage
generator, wherein the inverter controller includes a first dead
time compensation voltage generator generating a compensation
voltage based on an output current polarity of each phase in the
inverter, and a second dead time compensation voltage generator
generating a compensation voltage based on an output current
waveform of each phase in the inverter, and wherein a first dead
time compensation voltage outputted from the first dead time
compensation voltage generator and a second dead time compensation
voltage outputted from the second dead time compensation voltage
generator are added to generate a final dead time compensation
voltage, thereby preventing occurrence of hunting phenomenon in
which a current is greatly fluctuated.
Inventors: |
KIM; Kwang Yeon; (Seoul,
KR) |
Assignee: |
LSIS CO., LTD.
|
Family ID: |
44888155 |
Appl. No.: |
13/078869 |
Filed: |
April 1, 2011 |
Current U.S.
Class: |
363/41 |
Current CPC
Class: |
H02M 1/12 20130101; H02M
7/5387 20130101 |
Class at
Publication: |
363/41 |
International
Class: |
H02M 1/12 20060101
H02M001/12 |
Foreign Application Data
Date |
Code |
Application Number |
May 6, 2010 |
KR |
10-2010-0042657 |
Claims
1. An output current distortion compensating apparatus in an
inverter, the inverter including an inverter controller generating
a PWM signal for controlling a PWM voltage generator, wherein the
inverter controller includes a first dead time compensation voltage
generator generating a compensation voltage based on an output
current polarity of each phase in the inverter, and a second dead
time compensation voltage generator generating a compensation
voltage based on an output current waveform of each phase in the
inverter, and wherein a first dead time compensation voltage
outputted from the first dead time compensation voltage generator
and a second dead time compensation voltage outputted from the
second dead time compensation voltage generator are added to
generate a final dead time compensation voltage.
2. The apparatus of claim 1, wherein the second dead time
compensation voltage generator includes an accumulated current
computation unit calculating an integrated value of a period
relative to an output current of each phase in the inverter, and a
second dead time compensation voltage generator generating a second
dead time compensation voltage based on the integrated value of a
period calculated by the accumulated current computation unit.
3. The apparatus of claim 2, wherein each of the second dead time
compensation voltages (dVa2, dVb2, dVc2) is generated by
multiplying an additional compensation gain (-K) to the integrated
value (positive or negative) of a period relative to an output
current of each phase in the inverter.
4. The apparatus of claim 3, wherein each of the second dead time
compensation voltages (dVa2, dVb2, dVc2) is generated by
multiplying an additional compensation gain (-K) to the integrated
value of a period having a positive value, if an output current
waveform of each phase is leaned to a positive direction.
5. The apparatus of claim 3, wherein each of the second dead time
compensation voltages (dVa2, dVb2, dVc2) is generated by
multiplying an additional compensation gain (-K) to the integrated
value of a period having a negative value, if an output current
waveform of each phase is leaned to a negative direction.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present application is based on, and claims priority
from, Korean Application Numbers 10-2010-0042657, filed May 6,
2010, the disclosure of which is incorporated by reference herein
in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present disclosure relates to an output current
distortion compensating apparatus in an inverter, and more
particularly to an output current distortion compensating apparatus
in an inverter configured to prevent an output current distortion
in an inverter by generating an additional compensation voltage to
cope with a distortion phenomenon of an output current caused by an
error in a dead time compensation voltage.
[0004] 2. Description of Related Art
[0005] An inverter for motor driving can be used for various
purposes. Examples of the inverter for driving a motor may include
industrial manufacturing facilities, building air conditioners and
elevators. A conventional 3-phase inverter receives an electric
power of 3-phase (R, S, T) to output a 3-phase output of U, V, and
W phases to a motor, where, two switching elements (divided to a
+phase switching element and a +phase switching element based on
current polarity) such as IGBTs (insulated gate bipolar
transistors) are formed at each phase in order to control speed and
current in the motor, and a desired current or voltage is outputted
by turning on or off a relevant switching element in response to an
inputted PWM (Pulse Width Modulation) control signal.
[0006] At this time, if a +phase switching element and a -phase
switching element on the same phase are turned on, a current more
than a threshold current exceeding a rated current of the switching
element flows to break the switching elements, and in order to
protect the switching elements against the breakage, a dead time is
inserted to the PWM control signal controlling the switching
element to protect the switching elements.
[0007] However, there is a disadvantage in the conventional method
in that an actual dead time voltage is changed by ON/OFF
characteristics of a power switch element, and a dead time
compensation voltage generates an error responsive to noises
detected by a current detector, where the error in turn generates a
distortion to a voltage applied to an electric motor, leading to
occurrence of hunting phenomenon in which current is greatly
fluctuated.
SUMMARY OF THE INVENTION
[0008] The present disclosure is directed to solve the
abovementioned disadvantages and/or problems and it is an object of
the present disclosure to provide an output current distortion
compensating apparatus in an inverter, configured to output a
stable inverter PWM control signal by generating an additional dead
time compensation voltage responsive to a distorted inverter output
current, if vibration is generated in the inverter due to the
inverter output current distorted by an error in a dead time
compensation voltage.
[0009] Technical problems to be solved by the present disclosure
are not restricted to the above-mentioned descriptions, and any
other technical problems not mentioned so far will be clearly
appreciated from the following description by skilled in the
art.
[0010] An object of the invention is to solve at least one or more
of the above problems and/or disadvantages in a whole or in part
and to provide at least the advantages described hereinafter. In
order to achieve at least the above objects, in whole or in part,
and in accordance with the purposes of the invention, as embodied
and broadly described, and in one general aspect of the present
invention, there is provided an output current distortion
compensating apparatus in an inverter, the inverter including an
inverter controller generating a PWM signal for controlling a PWM
voltage generator, wherein the inverter controller includes a first
dead time compensation voltage generator generating a compensation
voltage based on an output current polarity of each phase in the
inverter, and a second dead time compensation voltage generator
generating a compensation voltage based on an output current
waveform of each phase in the inverter, and wherein a first dead
time compensation voltage outputted from the first dead time
compensation voltage generator and a second dead time compensation
voltage outputted from the second dead time compensation voltage
generator are added to generate a final dead time compensation
voltage.
[0011] Preferably, the second dead time compensation voltage
generator includes an accumulated current computation unit
calculating an integrated value of a period relative to an output
current of each phase in the inverter, and a second dead time
compensation voltage generator generating a second dead time
compensation voltage based on the integrated value of a period
calculated by the accumulated current computation unit.
[0012] Preferably, each of the second dead time compensation
voltages (dVa2, dVb2, dVc2) is generated by multiplying an
additional compensation gain (-K) to the integrated value (positive
or negative) of a period relative to an output current of each
phase in the inverter.
[0013] Preferably, each of the second dead time compensation
voltages (dVa2, dVb2, dVc2) is generated by multiplying an
additional compensation gain (-K) to the integrated value of a
period having a positive value, if an output current waveform of
each phase is leaned to a positive direction.
[0014] Preferably, each of the second dead time compensation
voltages (dVa2, dVb2, dVc2) is generated by multiplying an
additional compensation gain (-K) to the integrated value of a
period having a negative value, if an output current waveform of
each phase is leaned to a negative direction.
[0015] The output current distortion compensating apparatus in an
inverter according to the present disclosure has an advantageous
effect in that a dead time compensation error generated by ON/OFF
characteristics of a power switch element and noises detected by a
current detector is reduced to decrease imbalance in voltage
applied to an electric motor, thereby preventing occurrence of
hunting phenomenon in which a current is greatly fluctuated.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The teachings of the present disclosure can be readily
understood by considering the following detailed description in
conjunction with the accompanying drawings, in which:
[0017] FIG. 1 is a block diagram illustrating an output current
distortion compensating apparatus in an inverter;
[0018] FIG. 2 is a block diagram illustrating an output current
distortion compensating apparatus in an inverter according to an
exemplary embodiment of the present disclosure; and;
[0019] FIG. 3 is a waveform diagram illustrating a method a second
dead time compensation voltage from an accumulated current value of
one period according to the present disclosure.
DETAILED DESCRIPTION OF THE INVENTION
[0020] The particulars shown herein are by way of example and for
purposes of illustrative discussion of the embodiments of the
present disclosure only and are presented in the cause of providing
what is believed to be the most useful and readily understood
description of the principles and conceptual aspects of the present
disclosure.
[0021] In this regard, no attempt is made to show structural
details of the present disclosure in more detail than is necessary
for the fundamental understanding of the present disclosure, the
description taken with the drawings making apparent to those
skilled in the art how the several forms of the present disclosure
may be embodied in practice.
[0022] This disclosure is not limited in its application to the
details of construction and the arrangement of components set forth
in the following description or illustrated in the drawings. The
disclosure is capable of other embodiments and of being practiced
or of being carried out in various ways. Also, the phraseology and
terminology used herein is for the purpose of description and
should not be regarded as limiting. The use of "including,"
"comprising," or "having," "containing", "involving", and
variations thereof herein, is meant to encompass the items listed
thereafter and equivalents thereof as well as additional items.
[0023] In the following description, numerous specific details are
set forth to provide a thorough understanding of the embodiments.
One skilled in the relevant art will recognize, however, that the
techniques described herein can be practiced without one or more of
the specific details, or with other methods, components, materials,
etc. In other instances, well-known structures, materials, or
operations are not shown or described in detail to avoid obscuring
certain aspects.
[0024] In the drawings, the size and relative sizes of layers and
regions may be exaggerated for clarity. Like numbers refer to like
elements throughout, and explanations that duplicate one another
will be omitted.
Now, the exemplary embodiments of an output current distortion
compensating apparatus in an inverter according to the present
disclosure will be explained in detail hereinbelow together with
the figures.
[0025] FIG. 1 is a block diagram illustrating an output current
distortion compensating apparatus in an inverter.
[0026] Referring to FIG. 1, an output current distortion
compensating apparatus in an inverter includes a rectifier (2)
receiving a power from a 3-phase power source (1) and converting a
3-phase alternating current (AC) to a direct current (DC), a DC
smoother (3) smoothing the rectified voltage, a PWM (Pulse Width
Modulation) voltage generator (4) generating a PWM voltage using a
power switch element from a PWM generation signal of a PWM signal
generator (140), an electric motor (5) generating a rotational
force using the PWM generation voltage, a phase voltage command
unit (110) making PWM output voltage commands (Va*, Vb*, Vc*) of
each phase using a frequency and a voltage command, a current
detector (6) detecting currents (Ia, Ib, Ic) of the electric motor,
a current polarity discriminator (120) discriminating a polarity of
each current using the detected currents, and a dead time
compensation voltage generator (130) generating dead time
compensation voltages (dVa, dVb, dVc) using the current
polarity.
[0027] That is, an inverter controller (100) generating a PWM
control signal outputs the PWM control signal by adding the dead
time compensation voltage based on polarity of output current of
the inverter for reducing influence of the dead time.
[0028] The phase voltage command unit (110) makes commands (Va*,
Vb*, Vc*) of each phase voltage relative to present frequency
commands using frequency commands and a predetermined V/F
ratio.
[0029] The current polarity discriminator (120) discriminates
polarity of each current from the currents (Ia, Ib, Ic) obtained
from the current detector (6), and outputs +1 if the polarity of
current is +, and outputs -1 if the polarity of current is -.
[0030] The dead time compensation voltage generator (130) generates
dead time compensation voltages (dVa, dVb, dVc) using an output of
the current polarity discriminator (120). Computation of the dead
time compensation voltage is such that the dead time compensation
voltage generator (130) generates a voltage (+dV) corresponding to
a dead time of the current polarity being +, and generates a
voltage (-dV) corresponding to a dead time of the current polarity
being -.
[0031] Now, the output current distortion compensating apparatus in
an inverter according to an exemplary embodiment of the present
disclosure will be described in detail.
[0032] FIG. 2 is a block diagram illustrating an output current
distortion compensating apparatus in an inverter according to an
exemplary embodiment of the present disclosure.
[0033] Referring to FIG. 2, the output current distortion
compensating apparatus in an inverter according to an exemplary
embodiment of the present disclosure includes a rectifier (2)
receiving a power from a 3-phase power source (1) and converting a
3-phase alternating current (AC) to a direct current (DC), a DC
smoother (3) smoothing the rectified voltage, a PWM (Pulse Width
Modulation) voltage generator (4) generating a PWM voltage using a
power switch element from a PWM generation signal of a PWM signal
generator (10), an electric motor (5) generating a rotational force
using the PWM generation voltage, and an inverter controller (100)
generating the PWM signal.
[0034] The inverter controller (100) includes a phase voltage
command unit (110) making voltage commands (Va*, Vb*, Vc*) of each
phase using a frequency and a voltage command, a current polarity
discriminator (120) discriminating a polarity of each current using
the currents detected by the current detector (6) detecting the
currents (Ia, Ib, Ic) of the electric motor (5), a first dead time
compensation voltage generator (130) generating first dead time
compensation voltages (dVa1, dVb1, dVc1) using the discriminated
current polarity, and an additional dead time compensation voltage
generator (150).
[0035] Referring to FIG. 2 again, the inverter supplies the 3-phase
AC input power applied from the 3-phase power source to the DC
smoother (3) through the rectifier (2), and the PWM voltage
generator (4) generates a PWM voltage using the power switch
elements (e.g., IGBT) according to the PWM control signal outputted
from the PWM signal generator (140) of the inverter controller
(100) and supplies the PWM voltage to the electric motor (5).
[0036] The first dead time compensation voltage generator (130)
generates the first dead time compensation voltages (dVa1, dVb1,
dVc1) by receiving the polarity of current through the current
polarity discriminator (120) discriminating a polarity of each
current using the currents detected by the current detector (6),
which is an output of the current detector (6), where the current
polarity discriminator (120) discriminates polarity of each current
from the currents (Ia, Ib, Ic) obtained from the current detector
(6), and outputs +1 if the polarity of current is +, and outputs -1
if the polarity of current is -.
[0037] That is, the first dead time compensation voltage generator
(130) outputs the first dead time compensation voltages (dVa1,
dVb1, dVc1) using the output of the current polarity discriminator
(120). Computation of the dead time compensation voltage is such
that the first dead time compensation voltage generator (130)
generates a voltage (+dV) corresponding to a dead time of the
current polarity being +, and generates a voltage (-dV)
corresponding to a dead time of the current polarity being -.
[0038] At this time, the first dead time compensation voltage
outputted from the first dead time compensation voltage generator
(130) may differ based on ON/OFF characteristics of power switch
elements (e.g., IGBT) and have an error according to noises
detected by the current detector.
[0039] Thus, the output current distortion compensating apparatus
in an inverter according to an exemplary embodiment of the present
disclosure includes the additional dead time compensation voltage
generator (150) that generates an additional dead time compensation
voltage responsive to types of distorted currents detected by the
current detector (6) so as to maintain a sine wave where a current
flowing in the motor is not leaned to +nor to -.
[0040] The additional dead time compensation voltage generator
(150) includes an accumulated current computation unit (151)
accumulating a current of each phase for a period, and a second
dead time compensation voltage generator (152) generating
additional dead time compensation voltages (dVa2, dVb2, dVc2) using
an accumulated current value.
[0041] The second dead time compensation voltage generator (152)
generates the second dead time compensation voltages (dVa2, dVb2,
dVc2) by multiplying a gain to the accumulated current value of a
period from the accumulated current computation unit (151)
accumulating a current of each phase for a period.
[0042] FIG. 3 is a waveform diagram illustrating a method a second
dead time compensation voltage from an accumulated current value of
one period according to the present disclosure.
[0043] Referring to FIG. 3, FIG. 3(a) shows a waveform of an output
current (Ia), FIG. 3(b) illustrates an accumulated current
computation value and FIG. 3 (c) depicts an additional dead time
compensation value.
[0044] In case a current is a sine wave (i.e., a balanced state
that is not leaned to a positive or to negative side) as in the
waveform of the detected output current Ia (G1), an integrated
value of a current during a period (accumulated current computation
value) becomes zero as a waveform (G2), and the additional dead
time compensation value (second dead time compensation voltage
dVa2) becomes zero referring to a waveform (G3).
[0045] Meanwhile, in a case a current is leaned to a positive side
as in the waveform Ia (G4) of the detected output current, an
integrated value of a current during a period (accumulated current
computation value: G5) becomes a positive value, whereby a
correction voltage of a negative value must be provided to the
output voltage in the next period in order to reduce an offset of
positive direction, and the size of the correction voltage must be
proportional to an integrated value of a current during a period.
That is, the additional dead time compensation value (G6: second
dead time compensation voltage dVa2) becomes -k*Ia_integral, where
K is a compensation gain, and becomes Ia_integral is an integrated
value of a current of Ia phase during a period.
[0046] Meanwhile, in a case a current is leaned to a negative side
as in the waveform Ia (G7) of the detected output current, an
integrated value of a current during a period (accumulated current
computation value: G8) becomes a negative value, whereby a
correction voltage of a positive value must be provided to the
output voltage in the next period in order to reduce an offset of
negative direction, and the size of the correction voltage must be
proportional to an integrated value of a current during a period.
That is, the additional dead time compensation value (G9: second
dead time compensation voltage dVa2) becomes -k*Ia_integral.
Although a detected current (Ia) of one phase has been described in
the exemplary embodiment of the present disclosure, the same
applies to the second dead time compensation voltages (dVb2, dVc2)
relative to the detected current (Ib, Ic) of each phase.
[0047] Referring to FIG. 2 again, a final dead time compensation
voltages (dVa, dVb, dVc) are generated by adding the first dead
time compensation voltages (dVa1, dVb1, dVc1) outputted by the
first dead time compensation voltage generator (130) of each phase
to the second dead time compensation voltages (dVa2, dVb2, dVc2)
outputted by the second dead time compensation voltage generator
(152) of each phase.
[0048] Therefore, the PWM signal generator (140) generates a PWM
signal from final output voltage commands (Va**, Vb**, Vc**) of
each phase in which the final dead time compensation voltages (dVa,
dVb, dVc) and voltage commands (Va*, Vb*, Vc*) of each phase
generated by phase commend (110) are added voltage commands.
[0049] As apparent from the foregoing, the output current
distortion compensating apparatus in an inverter according to the
present disclosure has an industrial applicability and advantage in
that a dead time compensation error generated by ON/OFF
characteristics of a power switch element and noises detected by a
current detector is reduced to decrease imbalance in voltage
applied to an electric motor, thereby preventing occurrence of
hunting phenomenon in which a current is greatly fluctuated.
[0050] The above-mentioned output current distortion compensating
apparatus in an inverter according to the present disclosure may,
however, be embodied in many different forms and should not be
construed as limited to the exemplary embodiments set forth herein.
Thus, it is intended that embodiments of the present disclosure may
cover the modifications and variations of this disclosure provided
they come within the scope of the appended claims and their
equivalents. While particular features or aspects may have been
disclosed with respect to several embodiments, such features or
aspects may be selectively combined with one or more other features
and/or aspects of other embodiments as may be desired.
* * * * *