U.S. patent application number 13/095657 was filed with the patent office on 2011-10-27 for manufacturing method for semiconductor device containing stacked semiconductor chips.
This patent application is currently assigned to Sanyo Electric Co., Ltd.. Invention is credited to Hideki Mizuhara, Takeshi Nakamura, Ryosuke Usui.
Application Number | 20110263121 13/095657 |
Document ID | / |
Family ID | 34373339 |
Filed Date | 2011-10-27 |
United States Patent
Application |
20110263121 |
Kind Code |
A1 |
Usui; Ryosuke ; et
al. |
October 27, 2011 |
MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE CONTAINING STACKED
SEMICONDUCTOR CHIPS
Abstract
An adhesive film is formed on an electrode film, and a coating
film is formed thereon. Nickel, chrome, molybdenum, tungsten,
aluminum or an alloy of them is used as a constituent material of
the adhesive film. Gold, silver, platinum or an alloy of them is
used as a constituent material of the coating film.
Inventors: |
Usui; Ryosuke;
(Ichinomiya-city, JP) ; Mizuhara; Hideki;
(Bisai-City, JP) ; Nakamura; Takeshi; (Sawa-gun,
JP) |
Assignee: |
Sanyo Electric Co., Ltd.
Osaka
JP
|
Family ID: |
34373339 |
Appl. No.: |
13/095657 |
Filed: |
April 27, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12143603 |
Jun 20, 2008 |
7939373 |
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13095657 |
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10951541 |
Sep 28, 2004 |
7405484 |
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12143603 |
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Current U.S.
Class: |
438/669 ;
257/E21.158 |
Current CPC
Class: |
H01L 2221/68345
20130101; H01L 2924/19105 20130101; H01L 2224/49171 20130101; H01L
25/16 20130101; H05K 2201/0989 20130101; H01L 2924/181 20130101;
H01L 2924/13055 20130101; H05K 3/305 20130101; H01L 2224/48227
20130101; H01L 2924/14 20130101; H01L 24/48 20130101; H01L
2224/45144 20130101; H01L 2224/49175 20130101; H01L 23/498
20130101; H01L 2924/01004 20130101; H01L 2224/05554 20130101; H01L
2224/73265 20130101; H05K 3/3452 20130101; H01L 23/3128 20130101;
H01L 2224/0603 20130101; H01L 2924/01078 20130101; H05K 3/244
20130101; H01L 2924/19041 20130101; H01L 2924/01028 20130101; H01L
2924/0105 20130101; H01L 2924/01013 20130101; H01L 24/45 20130101;
Y10S 438/906 20130101; H01L 24/49 20130101; H01L 2924/12042
20130101; H05K 2203/095 20130101; H05K 3/381 20130101; H05K
2203/049 20130101; H01L 2224/48091 20130101; H01L 21/6835 20130101;
H01L 2924/15311 20130101; H01L 2924/01029 20130101; H01L 2924/01079
20130101; H01L 2224/45144 20130101; H01L 2924/00014 20130101; H01L
2224/48091 20130101; H01L 2924/00014 20130101; H01L 2924/13055
20130101; H01L 2924/00 20130101; H01L 2924/12042 20130101; H01L
2924/00 20130101; H01L 2924/181 20130101; H01L 2924/00012
20130101 |
Class at
Publication: |
438/669 ;
257/E21.158 |
International
Class: |
H01L 21/28 20060101
H01L021/28 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 30, 2003 |
JP |
2003-339123 |
Claims
1-11. (canceled)
12. A manufacturing method of a semiconductor device comprising:
providing a base material including a conductor circuit; forming a
dielectric film and a pad electrode, the dielectric film covering
at least a part of the base material, the pad electrode being
connected with the conductor circuit and being located on a surface
of the base material or a surface of the dielectric film; and
performing plasma treatment on exposed surfaces of the dielectric
film and the pad electrode, wherein the pad electrode comprises an
electrode film on the dielectric film and a plasma-resistant
protective film covering the electrode film.
13. The manufacturing method of claim 12, wherein forming the pad
electrode includes forming an adhesive film covering the electrode
film and forming a plasma-resistant protective film covering the
adhesive film.
14. The manufacturing method of claim 12, wherein performing plasma
treatment forms a cluster of micro projections on the exposed
surfaces of the dielectric film.
15. The manufacturing method of claim 12, wherein performing plasma
treatment forms a cluster of micro projections on the exposed
surfaces of the pad electrode.
16. The manufacturing method of claim 12, wherein forming the
dielectric film and the pad electrode comprises: forming the
dielectric film on a surface of the pad electrode and the base
material; and forming an opening in the dielectric film at a
location of the pad electrode.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention relates to a semiconductor device provided
with semiconductor chips, and a manufacturing method thereof.
[0003] 2. Description of the Related Art
[0004] Portable electronics devices such as a cellular phone, a
PDA, a DVC and a DSC become increasingly sophisticated. The
fabrication of the devices with a compact size and lightweight are
indispensable so that such devices are accepted in the market.
System LSI higher integrated is required for the realization of
such devices. On the other hand, LSI used for the devices is
required to be with a high functionality and a high performance for
the realization of friendly and convenient electronics devices. For
this reason, while the number of I/O is increasing with the
acceleration of LSI chip integration, downsizing of the package is
also required. The development of the packages appropriate to the
board assembly of semiconductor components with a high density is
strongly desired to satisfy both of the integration and the
downsizing. Some kinds of package technique called CSP (Chip Size
Package) are developed to correspond with such demand.
[0005] BGA (Ball Grid Array) is known as an example of such a
package as described above. BGA is formed by mounting a
semiconductor chip on a substrate for the package, molding it by
resin, and forming solder balls in an array on the backside surface
of the substrate as an external terminal. Since the mounting part
of BGA has an area, the downsizing of the package becomes easy.
Furthermore, a circuit board corresponding to a narrow pitch, and a
mounting technique with a high precision become unnecessary.
Therefore, a total mounting cost can be reduced by using BGA even
when a packaging cost is relatively high.
[0006] FIG. 1 is a schematic illustration of such a standard
configuration of BGA as disclosed in Japanese Laid-Open Patent
Application H7-183426. BGA 100 has a configuration in which the LSI
chip 102 is mounted on the adhesion layer 108 formed on the glass
epoxy board 106. The LSI chip 102 is molded by mold resin. The LSI
chip 102 is electrically connected with the glass epoxy board 106
by the metal wire 104. The solder balls 112 are formed in an array
arrangement on the backside surface of the glass epoxy board 106.
BGA 100 is mounted on a printed circuit board by the intermediary
of the solder balls 112.
[0007] In such a package, a semiconductor chip is connected with a
interconnect layer by a wire bonding method or a flip chip method.
That is, a pad electrode consisting of a metal film is provided on
the top of a interconnect layer, and the pad electrode is connected
with a pad electrode of a semiconductor chip by a predetermined
conductive member such as a gold wire and solder. It becomes
important technical problems to reduce the resistance at the
connecting point and to improve the connection strength stably, to
improve a yield rate and element reliability.
Related Art List
[0008] JPA laid open H7-183426
SUMMARY OF THE INVENTION
[0009] The resistance and the connection strength at the connecting
point are not obtained enough in some package formation processes.
The inventors of the present invention recognized that defects
frequently arose in wire bonding and so on, in particular when a
process including plasma treatment is introduced for the formation
of elements on an interconnect layer.
[0010] The present invention is achieved in view of the
aforementioned circumstances and an object thereof is to provide a
technique capable of suppressing bad connection between a
semiconductor chip and an interconnect layer so that element
reliability and a yield rate are improved.
[0011] The inventors of the present invention investigated
earnestly the reason for inducing the bad connection between a
semiconductor chip and an interconnect layer. As a result, they
found that the surface property of pad electrodes was changed so
that the connection strength declines, when a process such as a
plasma treatment, which changes a property of metal surface, is
implemented in an element mounting process on the interconnect
layer. The present invention is achieved based on such
knowledge.
[0012] A semiconductor device according to one aspect of the
present invention includes: a base material; a conductor circuit
provided in the base material; a dielectric film covering at least
a part of the base material; a pad electrode provided on a surface
of the base material or a surface of the dielectric film and
connected with the conductor circuit; a semiconductor chip formed
on the dielectric film, and a conductive member electrically
connecting the pad electrode and the semiconductor chip, wherein
the pad electrode includes a electrode film and a conductive
protective film formed on a surface of the electrode film, and the
conductive member is formed so that one end thereof contacts with
the conductive protective film.
[0013] A manufacturing method of a semiconductor device according
to one aspect of the present invention includes: providing a base
material including a conductor circuit; with forming a dielectric
film covering at least a part of the base material, forming a pad
electrode, which is connected with the conductor circuit, on a
surface of the base material or a surface of the dielectric film;
and performing plasma treatment of exposed surfaces of the
dielectric film and the pad electrode.
[0014] According to the present invention, degradation of surface
of pad electrodes can be suppressed since a conductive protective
film is provided on the surface of the pad electrodes.
[0015] This semiconductor device may have a construction in which
the surface of the dielectric film is a plasma treatment surface,
and the surface of the conductive protective film includes a
plasma-resistant material. The dielectric film may have a cluster
of micro projections formed on the surface thereof by the plasma
treatment. Although the plasma treatment of the surface of the
dielectric film leads to the improvement of adhesion for a film
formed thereon, degradation of the surface of the pad electrode
simultaneously arises, and the bad connection between the
semiconductor chip and the interconnect layer becomes a problem.
According to the construction described above, such a problem can
be solved since the degradation of the surface of the pad electrode
can be suppressed by the conductive protective film.
[0016] The semiconductor device may have a construction in which
the dielectric film has a concave part, the pad electrode is formed
inside the concave part, and a void part is provided between the
inside wall of the concave part and the side wall of the pad
electrode. With this construction, the adhesion for the film, such
as mold resin, formed on the dielectric film can be improved.
Furthermore, the surface of the pad electrode becomes less subject
to the attachment of particles of the dielectric film material.
[0017] The conductive protective film according to the present
invention may include an adhesive film formed on the electrode
film, and a coating film formed on the adhesive film, which
constitutes the surface of the conductive protective film.
[0018] This summary of the invention does not necessarily describe
all necessary features so that the invention may also be a
sub-combination of these described features.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] FIG. 1 shows a package configuration according to a prior
art.
[0020] FIG. 2 shows a configuration of ISB.TM..
[0021] FIG. 3A shows manufacturing process of BGA.
[0022] FIG. 3B shows manufacturing process of ISB.TM..
[0023] FIG. 4 shows a configuration of a semiconductor device
according to the embodiment.
[0024] FIG. 5A shows a manufacturing process of a semiconductor
device according to the embodiment.
[0025] FIG. 5B shows a manufacturing process of a semiconductor
device according to the embodiment.
[0026] FIG. 5C shows a manufacturing process of a semiconductor
device according to the embodiment.
[0027] FIG. 6A shows a manufacturing process of a semiconductor
device according to the embodiment.
[0028] FIG. 6B shows a manufacturing process of a semiconductor
device according to the embodiment.
[0029] FIG. 7A shows a manufacturing process of a semiconductor
device according to the embodiment.
[0030] FIG. 7B shows a manufacturing process of a semiconductor
device according to the embodiment.
[0031] FIG. 7C shows a manufacturing process of a semiconductor
device according to the embodiment.
DETAILED DESCRIPTION OF THE INVENTION
[0032] Although the invention will be described below based on the
preferred embodiments, the ISB.TM. configuration introduced in each
embodiment will be now described prior to it. ISB.TM. (Integrated
System in Board) is a unique package developed by the inventors of
the present invention. ISB.TM. is a unique coreless system-in
package in the packaging techniques involving electric circuits
including semiconductor bare chips mainly, and it has interconnect
patterns made of copper but no core (base material) to support
circuit components.
[0033] FIG. 2 shows a schematic illustration of an example of
ISB.TM.. Although a single interconnect layer is shown for a simple
explanation of the overall configuration of ISB.TM., the
configuration practically includes a plurality of interconnect
layers stacked. This ISB.TM. has a configuration that includes the
LSI bare chip 201, Tr bare chip 202 and the chip CR 203 connected
by interconnect lines that include the copper pattern 205. The LSI
bare chip 201 is connected with extraction electrodes and the
interconnect lines by the gold wire bonding 204. The ISB.TM. is
mounted on a printed circuit board by the conductive paste 206
formed beneath the LSI bare chip 201. ISB.TM. is entirely sealed
with a resin package 207 made of epoxy resin and so on. Although
the configuration that includes a single interconnect layer is
shown in this figure, a multilayer interconnect configuration may
be also adopted.
[0034] FIGS. 3A and 3B show a comparison of manufacturing processes
of a conventional CSP and the ISB.TM. according to one aspect of
the present invention. FIG. 3A shows a manufacturing process of the
conventional CSP. A frame is firstly formed on a base substrate,
and chips are mounted on the element formation areas segmented by
the frame. After that, a package made of thermosetting resin is
provided for each element, and blanking is performed for each
element by using a metal die. In the final blanking process, the
mold resin and the base substrate are cut simultaneously.
Therefore, the roughness of the cut surface becomes a problem.
Furthermore, since a large amount of waste material after the
blanking process generates, a problem also arises from the
viewpoint of environmental burden.
[0035] FIG. 3B shows the ISB.TM. manufacturing process. Frames are
firstly formed on a metal foil. Circuit elements such as a LSI are
mounted on interconnect patterns formed in each module formation
area. After packaging each module, finished products are obtained
by dicing along scribing areas. Since the metal foil as a base is
removed after the packaging process and before the scribing
process, only the resin layer is cut by dicing in the scribing
process. Therefore, the roughness of the cut surface can be
prevented, and the dicing can be performed more accurately.
[0036] The following advantages are obtained by the technique of
ISB.TM..
(i) Transistors, ICs and LSIs can be made smaller and thinner
because of the coreless assembly. (ii) High-performance SIP
(System-in Package) can be realized since a circuit including
transistors, system LSIs, chip capacitors and chip resistors can be
formed and packaged. (iii) It becomes possible to develop a system
LSI in a short term since existing semiconductor chips can be used
in combination. (iv) High rate of heat radiation can be obtained
since the semiconductor bare chip is directly mounted on copper.
(v) Since the interconnect material is copper and there is no core
material, the circuit interconnect has a low dielectric constant so
that the excellent properties in high-speed transfer of data and in
a high-frequency circuit can be obtained. (vi) The formation of
particle contamination of the electrode material can be suppressed
because of the configuration where the electrodes are embedded in
the package. (vii) Environmental burden can be reduced since the
package size is free, and the amount of the waste material per one
package is one-tenth of that of SQEP package having 64 pins. (viii)
The concept of a system construction can be changed from a printed
circuit board to mount components into a functional circuit board.
(ix) The design of ISP patterns is as easy as the design of printed
circuit board patterns, and can be performed by engineers
themselves in set manufacturers.
[0037] Next, the preferred embodiments of the present invention
will be explained referring to figures.
[0038] A semiconductor device having an ISB.TM. configuration
described above will be taken as an example for a following
explanation of the preferred embodiment of the present invention.
FIG. 4 shows a cross sectional view of a semiconductor device
according to the present embodiment. This semiconductor device
includes a multilevel interconnect configuration, and the element
410a and the circuit element 410b that are formed on the multilevel
interconnect configuration. The multilevel interconnect
configuration includes a plurality of interconnect layers stacked,
each of which consists of the interlayer dielectric film 405 or 406
and the interconnect line 407 made of copper, and the solder resist
layer 408 formed as the top layer. The solder ball 420 is provided
on the backside surface of the multilevel interconnect
configuration. The element 410a and the circuit element 410b are
molded by the mold resin 415.
[0039] The pad electrode 460 is electrically connected to the
interconnect line 407. The pad electrode 460 and the element 410a
are connected by the gold wire 470. The pad electrode 460 and the
element 410b are connected by a flip chip method. The pad electrode
460 includes a copper film and a plasma-resistant protective film,
which is made of a conductive material, formed on the copper film.
The configuration of the plasma-resistant protective film will be
described below.
[0040] The resin materials such as a melamine derivative such as BT
resin, a liquid crystal polymer, an epoxy resin, a PPE resin, a
polyimide resin, a fluorocarbon resin, a phenol resin and a
thermosetting resin such as a polyamide bismaleimide can be
selected for the solder resist layer 408, the interlayer dielectric
film 405 and the mold resin 415 in FIG. 4, respectively. In
particular, the liquid crystal polymer, the epoxy resin and the
melamine derivative such as BT resin are preferably used since they
have an excellent high-frequency property. Filler or additive may
be arbitrarily added to the resin.
[0041] Next, a manufacturing method of the semiconductor device
shown in FIG. 4 will be described in reference to FIGS. 5A to 7C.
The via hole 404 is formed at a predetermined location on the metal
foil 400, and the conductive film 402 is formed in the via hole 404
selectively as shown in FIG. 5A. More specifically, after coating
the metal foil 400 by the photo resist 401, the conductive film 402
is formed on an exposed part of the surface of the metal foil 400
by an electric field plating method. The conductive film 402 has a
thickness of about 1 to 10 .mu.m, for example. Since the conductive
film 402 will become finally a backside electrode of a
semiconductor device, gold or silver, which has a good adhesiveness
for brazing filler metal such as solder, is preferably used for the
conductive film 402.
[0042] After that, the interconnect pattern of the first layer are
formed on the metal foil 400 as shown in FIG. 5B. First, chemical
polishing is performed against the metal foil 400 for cleaning the
surface and to form a rough surface. Next, the conductive film 402
on the metal foil 400 is entirely coated by thermosetting resin,
and heat hardening is performed so that the film surface becomes
flat. Next, a via hole with a diameter of about 100 .mu.m reaching
to the conductive film 402 is formed in the film. The via hole is
formed by a laser processing in the present embodiment. Machining,
chemical etching, and dry etching by using plasma can be also used
to form the via hole. After that, etching residue is removed by
laser exposure, and a copper plating layer is formed on overall the
surface with embedding the via hole 404. The copper plating layer
is etched by using a photo resist mask so that the interconnect
line 407 made of copper is formed. The interconnect pattern can be
formed by removing unnecessary copper foil by spraying etching
solution to the surface exposed out of the resist, for example.
[0043] The formation of the interlayer dielectric film 405, the via
hole and the copper plating layer, and the patterning of the copper
plating layer mentioned above are repeated in turn so that the
multilevel interconnect configuration in which the interconnect
layers including the interconnect line 407 and the interlayer
dielectric films 405 and 406 are stacked is formed as shown in FIG.
5C.
[0044] After the formation of the pad electrodes 460 and the solder
resist layer 408 that has openings at the locations of the pad
electrodes 460, the element 410a and the circuit element 410b are
formed on the solder resist layer 408. A dielectric material that
has a good solder heat resistance is used for the solder resist
layer 408. For example, an epoxy resin may be used. The element
410a and the circuit element 410b may be, for example,
semiconductor chips such as a transistor, a diode and an IC chip,
or passive elements such as a chip capacitor and a chip resistor.
Face-down semiconductor elements such as a CSP and a BGA may be
also mounted. In the present embodiment, the element 410a is a bare
semiconductor chip (a transistor chip) and the circuit element 410b
is a chip capacitor. These elements are stuck on the solder resist
layer 408.
[0045] The formation process of the configuration shown in FIG. 6A
is now described referring to FIG. 7. After formation of a copper
film on the interlayer dielectric film 406, the electrode film 462
is formed by patterning processes. After that, the adhesive film
464 is formed on the surface of the electrode film 462 by a
selective plating method, followed by forming the coating film 466.
Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them
is, for example, used for the adhesive film 464. Gold, silver,
platinum or an alloy of them is, for example, used for the coating
film 466. Each of the films may have either a single layer or a
double layer. Next, the solder resist layer 408 is formed by
thermocompression of a solder resist sheet stuck on the surface of
the interlayer dielectric film 406. Opening is formed at the
location of the electrode film 462 in the solder resist layer 408
by exposure and development. A void part is provided between the
side wall of the electrode film 462 and the inside wall of the
opening in the solder resist layer 408. Although the solder resist
layer 408 made of an epoxy resin is formed by using an epoxy resin
sheet in the present embodiment, other kinds of material may be
used.
[0046] When the electrode film 462 is made of copper or
copper-aluminum alloy, nickel and gold are, for example, preferably
used for the adhesive film 464 and the coating film 466,
respectively. This combination is adopted in the present
embodiment.
[0047] The pad electrode 460 with a plasma-resistant protective
film, in which the adhesive film 464 and the coating film 466 are
stacked on the electrode film 462 in this order, is formed as
mentioned above. In this configuration, the coating film 466
contributes to improvement of plasma-resistance, and the adhesive
film 464 contributes to improvement of the adhesion between the
coating film 466 and the electrode film 462. The configuration
shown in FIG. 6A can be obtained as described above.
[0048] Plasma treatment is performed for the configuration shown in
FIG. 6A. The plasma exposure condition may be arbitrarily
determined corresponding to used resin so that a cluster of micro
projections mentioned above is formed. A bias voltage is preferably
not applied to the substrate. For example, the following condition
is adopted. [0049] Bias voltage: no voltage applied [0050] Plasma
gas: argon of 10 to 20 sccm and oxygen of 0 to 10 sccm
[0051] By the plasma exposure, the surface of the interconnect line
407 is cleaned, the surface property of the solder resist layer 408
is modified, and a cluster of micro projections is formed on the
surface. The cluster of micro projections formed on the surface of
the solder resist layer 408 and the surface of the elements 410a
and 410b have an average diameter of 1 to 10 nm and a number
density of about 1.times.10.sup.3 .mu.m.sup.-2.
[0052] After connecting the element 410a and the pad electrode 460
by the gold wire 470, they are molded by the mold resin 415 as
shown in FIG. 6B. FIG. 6B shows a molded configuration. The mold
process of semiconductor elements is performed simultaneously for a
plurality of modules mounted on the metal foil 400 by using a mold.
Transfer mold, injection mold, potting and dipping may be used for
the mold process. When a thermosetting resin such as an epoxy resin
is used, the transfer mold or potting can be adopted. When a
thermoplastic resin such as a polyimide resin and a polyphenylene
sulfide is used, the injection mold can be adopted.
[0053] After removing the metal foil 400 from the configuration
shown in FIG. 6B, solder balls are formed on the backside surface.
The metal foil 400 can be removed by polishing, grinding, etching
or laser vaporization, for example. The method adopted in the
present embodiment is as follows: the metal foil 400 is overall
grinded about 50 .mu.m by a polisher or a grinder, and the rest of
the metal foil 400 is removed by chemical wet etching. Wet etching
may be used also for removing the entire metal foil 400. By these
processes, the lower surface of the interconnect line 407 in the
first layer is exposed on the opposite side of the surface where
the semiconductor elements are mounted. With this configuration, a
module having a flat underside surface is obtained in the present
embodiment. Therefore, when the semiconductor device is mounted, it
moves horizontally by surface tension of solder and so on, and an
advantage in the processing, i.e., easy self alignment, can be
obtained.
[0054] After that, the solder ball 420 is formed by sticking a
conductive material such as solder on the backside surface of the
conductive film 402, which is exposed by removing the metal foil
400. Then the semiconductor device shown in FIG. 4 is obtained by
dicing. The wafer is subsequently cut by dicing so that a chip of
the semiconductor device can be obtained. The metal foil 400 is a
supporting substrate before removing the metal foil 400 as
described above. The metal foil 400 is also used as an electrode in
the electric field plating process to form the interconnect line
407. Furthermore, also when the mold resin 415 is molded, the metal
foil 400 makes the workability of carrying to a mold and of
mounting in the mold favorable.
[0055] In the semiconductor according to the present embodiment,
the property of surfaces of the solder resist layer 408, the
element 410a and the circuit element 410b is modified by Ar plasma
treatment in the process shown in FIG. 6A, and micro projections
are formed thereon. As a result, the interface adhesiveness between
them and the mold resin 415 is significantly improved, and the
yield rate and the element reliability are advanced.
[0056] Moreover, a bad connection between a semiconductor chip and
an interconnect layer can be suppressed in the wire bonding process
since the surface of the pad electrode 460 does not degrade even if
such a plasma treatment as described above is performed. Therefore,
high reliability and a high yield rate can be realized.
[0057] Although the present invention has been described by way of
exemplary embodiments, it should be understood that many changes
and substitutions may be made by those skilled in the art without
departing from the spirit and the scope of the present invention
which is defined only by the appended claims.
* * * * *