U.S. patent application number 13/155576 was filed with the patent office on 2011-10-13 for semiconductor storage device memory disk unit with multiple host interfaces.
Invention is credited to Byungcheol Cho.
Application Number | 20110252250 13/155576 |
Document ID | / |
Family ID | 44761786 |
Filed Date | 2011-10-13 |
United States Patent
Application |
20110252250 |
Kind Code |
A1 |
Cho; Byungcheol |
October 13, 2011 |
SEMICONDUCTOR STORAGE DEVICE MEMORY DISK UNIT WITH MULTIPLE HOST
INTERFACES
Abstract
In general, embodiments of the present invention provide a
Semiconductor Storage Device (SSD) memory disk unit having multiple
host interface units. Specifically, in a typical embodiment, the
SSD memory disk unit comprises a plurality of host interface units
for coupling the SSD memory disk unit to at least one host; a host
interface controller unit coupled to each of the plurality of host
interface units; a DMA controller coupled to the host interface
controller unit; an ECC controller coupled to the DMA controller; a
memory controller coupled to the ECC controller; and a memory array
coupled to the memory controller, the memory array comprising at
least one SSD memory block.
Inventors: |
Cho; Byungcheol; (Seochogu,
KR) |
Family ID: |
44761786 |
Appl. No.: |
13/155576 |
Filed: |
June 8, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12758937 |
Apr 13, 2010 |
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13155576 |
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Current U.S.
Class: |
713/300 ;
710/308; 713/400 |
Current CPC
Class: |
G06F 3/0659 20130101;
G06F 3/0688 20130101; G06F 3/0607 20130101; G06F 3/0613
20130101 |
Class at
Publication: |
713/300 ;
710/308; 713/400 |
International
Class: |
G06F 13/36 20060101
G06F013/36; G06F 13/42 20060101 G06F013/42 |
Claims
1. A semiconductor storage device (SSD) memory disk unit having
multiple host interface units, comprising: a plurality of host
interface units for coupling the SSD memory disk unit to at least
one host; a host interface controller unit coupled to each of the
plurality of host interface units; a DMA controller coupled to the
host interface controller unit; an ECC controller coupled to the
DMA controller; a memory controller coupled to the ECC controller;
and a memory array coupled to the memory controller, the memory
array comprising a set of SSD memory blocks.
2. The SSD memory disk unit of claim 1, further comprising: a
redundant array of independent disks (RAID) controller coupled to
the SSD memory disk unit; a controller unit coupled to the RAID
controller; and a system interface unit coupled to the controller
unit.
3. The SDD memory disk unit of claim 2, the controller unit
comprising: a memory control module for controlling data
input/output of the SSD memory disk unit; a DMA control module
which controls the memory control module to store data in the SSD
memory disk unit or reads data from the SSD memory disk unit to
provide the data to the host, according to an instruction from the
host received through the host interface unit; a buffer which
buffers data according to control of the DMA control module; a
synchronization control module, which when receiving a data signal
corresponding to the data read from the SSD memory disk unit by the
control of the DMA control module through the DMA control module
and the memory control module, adjusts synchronization of a data
signal so as to have a communication speed corresponding to a
PCI-Express communications protocol to transmit the synchronized
data signal to the PCI-Express host interface unit, and when
receiving a data signal from the host through the PCI-Express host
interface unit, adjusts synchronization of the data signal so as to
have a transmission speed corresponding to a communications
protocol used by the SSD memory disk unit to transmit the
synchronized data signal to the SSD memory disk unit through the
DMA control module and the memory control module; and a high-speed
interface module which processes the data transmitted/received
between the synchronization control module and the DMA control
module at high speed, includes a buffer having a double buffer
structure and a buffer having a circular queue structure, and
processes the data transmitted/received between the synchronization
control module and the DMA control without loss of high speed by
buffering the data communicated between the synchronization control
module and the DMA control module using the buffers and adjusting
data clocks.
4. The SSD memory disk unit of claim 2, further comprising: a set
of backup storage units coupled to the controller unit, the
controller unit storing data of the SSD memory disk unit; and a
backup control unit coupled to the SSD memory disk unit, the backup
control unit backing up data stored in the SSD memory disk unit
according to at least one of the following: an instruction from the
at least one host or when an error occurs in the power transmitted
from the at least one host.
5. The SSD memory disk unit of claim 3, further comprising: an
auxiliary power source unit coupled to the backup control unit, the
auxiliary power source being charged to maintain a predetermined
power using the power transferred from the at least one host
through the system interface unit; and a power source control unit
coupled to the auxiliary power source, the power source control
unit supplying power transferred from the at least one host through
the system interface unit to the controller unit, the memory disk
unit, the backup storage unit, and the backup control unit, and
when the power transferred from the host through the host interface
unit is blocked or an error occurs in the power transferred from
the host, receives power from the auxiliary power source unit and
supplies the power to the memory disk until through the controller
unit.
6. The SSD memory disk unit of claim 1, further comprising a status
monitor coupled to the SSD memory disk unit.
7. The SSD memory disk unit of claim 1, the set of SSD memory
blocks being volatile, and the plurality of host interface units
being PCI-Express host interface units.
8. A semiconductor storage device (SSD) memory disk unit having
multiple host interface units, comprising: a first host interface
unit and a second host interface unit coupled to the first host
interface unit, the first host interface unit and the second host
interface unit for coupling the SSD memory disk unit to at least
one host; a host interface controller unit coupled to the first
host interface unit and the second host interface unit; a DMA
controller coupled to the host interface controller unit; an ECC
controller coupled to the DMA controller; a memory controller
coupled to the ECC controller; and a memory array coupled to the
memory controller, the memory array comprising a set of SSD memory
blocks.
9. The SSD memory disk unit of claim 1, further comprising: a
redundant array of independent disks (RAID) controller coupled to
the SSD memory disk unit; a controller unit coupled to the RAID
controller; and a system interface unit coupled to the controller
unit.
10. The SDD memory disk unit of claim 9, the controller unit
comprising: a memory control module for controlling data
input/output of the SSD memory disk unit; a DMA control module
which controls the memory control module to store data in the SSD
memory disk unit or reads data from the SSD memory disk unit to
provide the data to the host, according to an instruction from the
host received through the host interface unit; a buffer which
buffers data according to control of the DMA control module; a
synchronization control module, which when receiving a data signal
corresponding to the data read from the SSD memory disk unit by the
control of the DMA control module through the DMA control module
and the memory control module, adjusts synchronization of a data
signal so as to have a communication speed corresponding to a
PCI-Express communications protocol to transmit the synchronized
data signal to the PCI-Express host interface unit, and when
receiving a data signal from the host through the PCI-Express host
interface unit, adjusts synchronization of the data signal so as to
have a transmission speed corresponding to a communications
protocol used by the SSD memory disk unit to transmit the
synchronized data signal to the SSD memory disk unit through the
DMA control module and the memory control module; and a high-speed
interface module which processes the data transmitted/received
between the synchronization control module and the DMA control
module at high speed, includes a buffer having a double buffer
structure and a buffer having a circular queue structure, and
processes the data transmitted/received between the synchronization
control module and the DMA control without loss of high speed by
buffering the data communicated between the synchronization control
module and the DMA control module using the buffers and adjusting
data clocks.
11. The SSD memory disk unit of claim 9, further comprising: a set
of backup storage units coupled to the controller unit, the
controller unit storing data of the SSD memory disk unit; and a
backup control unit coupled to the SSD memory disk unit, the backup
control unit backing up data stored in the SSD memory disk unit
according to at least one of the following: an instruction from the
at least one host or when an error occurs in the power transmitted
from the at least one host.
12. The SSD memory disk unit of claim 11, further comprising: an
auxiliary power source unit coupled to the backup control unit, the
auxiliary power source being charged to maintain a predetermined
power using the power transferred from the at least one host
through the system interface unit; and a power source control unit
coupled to the auxiliary power source, the power source control
unit supplying power transferred from the at least one host through
the system interface unit to the controller unit, the memory disk
unit, the backup storage unit, and the backup control unit, and
when the power transferred from the host through the host interface
unit is blocked or an error occurs in the power transferred from
the host, receives power from the auxiliary power source unit and
supplies the power to the memory disk until through the controller
unit.
13. The SSD memory disk unit of claim 8, further comprising a
status monitor coupled to the SSD memory disk unit.
14. The SSD memory disk unit of claim 8, the set of SSD memory
blocks being volatile, and the plurality of host interface units
being PCI-Express host interface units.
15. A method for producing a semiconductor storage device (SSD)
memory disk unit having multiple host interface units, comprising:
providing a plurality of host interface units for coupling the SSD
memory disk unit to at least one host; coupling a host interface
controller unit to each of the plurality of host interface units;
coupling a DMA controller to the host interface controller unit;
coupling an ECC controller to the DMA controller; a memory
controller coupled to the ECC controller; and coupling a memory
array to the memory controller, the memory array comprising a set
of SSD memory blocks.
16. The method of claim 15, further comprising: coupling a
redundant array of independent disks (RAID) controller to the SSD
memory disk unit; coupling a controller unit to the RAID
controller; and coupling a system interface unit cupled to the
controller unit.
17. The method of claim 16, producing the controller unit by:
providing a memory control module for controlling data input/output
of the SSD memory disk unit; coupling a DMA control module to the
memory control module, the DMA control module controlling the
memory control module to store data in the SSD memory disk unit or
reads data from the SSD memory disk unit to provide the data to the
host, according to an instruction from the host received through
the host interface unit; coupling a buffer to the DMA control
module, the buffer buffering data according to control of the DMA
control module; coupling a synchronization control module to the
buffer, the synchronization control module, which when receiving a
data signal corresponding to the data read from the SSD memory disk
unit by the control of the DMA control module through the DMA
control module and the memory control module, adjusts
synchronization of a data signal so as to have a communication
speed corresponding to a PCI-Express communications protocol to
transmit the synchronized data signal to the PCI-Express host
interface unit, and when receiving a data signal from the host
through the PCI-Express host interface unit, adjusts
synchronization of the data signal so as to have a transmission
speed corresponding to a communications protocol used by the SSD
memory disk unit to transmit the synchronized data signal to the
SSD memory disk unit through the DMA control module and the memory
control module; and coupling a high-speed interface module to the
synchronization control module, the high-speed interface module
processing the data transmitted/received between the
synchronization control module and the DMA control module at high
speed, includes a buffer having a double buffer structure and a
buffer having a circular queue structure, and processes the data
transmitted/received between the synchronization control module and
the DMA control without loss of high speed by buffering the data
communicated between the synchronization control module and the DMA
control module using the buffers and adjusting data clocks.
18. The method of claim 16, further comprising: coupling a set of
backup storage units to the controller unit, the controller unit
storing data of the SSD memory disk unit; and coupling a backup
control unit to the SSD memory disk unit, the backup control unit
backing up data stored in the SSD memory disk unit according to at
least one of the following: an instruction from the at least one
host or when an error occurs in the power transmitted from the at
least one host.
19. The method of claim 18, further comprising: coupling an
auxiliary power source unit to the backup control unit, the
auxiliary power source being charged to maintain a predetermined
power using the power transferred from the at least one host
through the system interface unit; and coupling a power source
control unit to the auxiliary power source, the power source
control unit supplying power transferred from the at least one host
through the system interface unit to the controller unit, the
memory disk unit, the backup storage unit, and the backup control
unit, and when the power transferred from the host through the host
interface unit is blocked or an error occurs in the power
transferred from the host, receives power from the auxiliary power
source unit and supplies the power to the memory disk until through
the controller unit.
20. The method of claim 15, further comprising coupling a status
monitor to the SSD memory disk unit.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation-in-part of
commonly-owned, co-pending application Ser. No. 12/758,937,
entitled "SEMICONDUCTOR STORAGE DEVICE", filed on Apr. 13, 2010,
the entire contents of which are herein incorporated by reference.
This application is also related in some aspects to commonly-owned,
co-pending application number 13,029,476 entitled "SEMICONDUCTOR
STORAGE DEVICE-BASED CACHE STORAGE SYSTEM", filed on Feb. 17, 2011,
the entire contents of which are herein incorporated by reference.
This application is also related in some aspects to commonly-owned,
co-pending application number (to be provided) entitled
"SEMICONDUCTOR STORAGE DEVICE MEMORY DISK UNIT WITH PROGRAMMABLE
HOST INTERFACE, filed on (to be provided), having attorney docket
number SSD-0027, the entire contents of which are herein
incorporated by reference.
FIELD OF THE INVENTION
[0002] The present invention relates to a semiconductor storage
device (SSD) of a PCI-Express (PCI-e) type. Specifically, the
present invention relates to an SSD memory disk unit having
multiple (e.g., dual) host interfaces.
BACKGROUND OF THE INVENTION
[0003] As the need for more computer storage grows, more efficient
solutions are being sought. As is known, there are various hard
disk solutions that store/read data in a mechanical manner as a
data storage medium. Unfortunately, data processing speed
associated with hard disks is often slow. Moreover, existing
solutions still use interfaces that cannot catch up with the data
processing speed of memory disks having high-speed data
input/output performance as an interface between the data storage
medium and the host. Therefore, there is a problem in the existing
area in that the performance of the memory disk cannot be property
utilized.
SUMMARY OF THE INVENTION
[0004] In general, embodiments of the present invention provide a
Semiconductor Storage Device (SSD) memory disk unit having multiple
host interface units. Specifically, in a typical embodiment, the
SSD memory disk unit comprises a plurality of host interface units
for coupling the SSD memory disk unit to at least one host; a host
interface controller unit coupled to each of the plurality of host
interface units; a DMA controller coupled to the host interface
controller unit; an ECC controller coupled to the DMA controller; a
memory controller coupled to the ECC controller; and a memory array
coupled to the memory controller, the memory array comprising at
least one SSD memory block.
[0005] A first aspect of the present invention provides a
semiconductor storage device (SSD) memory disk unit having multiple
host interface units, comprising: a plurality of host interface
units for coupling the SSD memory disk unit to at least one host; a
host interface controller unit coupled to each of the plurality of
host interface units; a DMA controller coupled to the host
interface controller unit; an ECC controller coupled to the DMA
controller; a memory controller coupled to the ECC controller; and
a memory array coupled to the memory controller, the memory array
comprising a set of SSD memory blocks.
[0006] A second aspect of the present invention provides a
semiconductor storage device (SSD) memory disk unit having multiple
host interface units, comprising: a first host interface unit and a
second host interface unit coupled to the first host interface
unit, the first host interface unit and the second host interface
unit for coupling the SSD memory disk unit to at least one host; a
host interface controller unit coupled to the first host interface
unit and the second host interface unit; a DMA controller coupled
to the host interface controller unit; an ECC controller coupled to
the DMA controller; a memory controller coupled to the ECC
controller; and a memory array coupled to the memory controller,
the memory array comprising a set of SSD memory blocks.
[0007] A third aspect of the present invention provides a method
for producing a semiconductor storage device (SSD) memory disk unit
having multiple host interface units, comprising: providing a
plurality of host interface units for coupling the SSD memory disk
unit to at least one host; coupling a host interface controller
unit to each of the plurality of host interface units; coupling a
DMA controller to the host interface controller unit; coupling an
ECC controller to the DMA controller; a memory controller coupled
to the ECC controller; and coupling a memory array to the memory
controller, the memory array comprising a set of SSD memory
blocks.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] These and other features of this invention will be more
readily understood from the following detailed description of the
various aspects of the invention taken in conjunction with the
accompanying drawings in which:
[0009] FIG. 1 is a diagram illustrating a configuration of a
storage device of a PCI-Express (PCI-e) type according to an
embodiment of the present invention.
[0010] FIG. 2 is a diagram of the high-speed SSD of FIG. 1
according to an embodiment of the present invention.
[0011] FIG. 3 is a diagram illustrating a configuration of the
controller unit in FIG. 1 having a dual host interface unit
according to an embodiment of the present invention.
[0012] The drawings are not necessarily to scale. The drawings are
merely schematic representations, not intended to portray specific
parameters of the invention. The drawings are intended to depict
only typical embodiments of the invention, and therefore should not
be considered as limiting the scope of the invention. In the
drawings, like numbering represents like elements.
DETAILED DESCRIPTION OF THE INVENTION
[0013] Exemplary embodiments will now be described more fully
herein with reference to the accompanying drawings, in which
exemplary embodiments are shown. This disclosure may, however, be
embodied in many different forms and should not be construed as
limited to the exemplary embodiments set forth therein. Rather,
these exemplary embodiments are provided so that this disclosure
will be thorough and complete and will fully convey the scope of
this disclosure to those skilled in the art. In the description,
details of well-known features and techniques may be omitted to
avoid unnecessarily obscuring the presented embodiments.
[0014] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limited to
this disclosure. As used herein, the singular forms "a", "an", and
"the" are intended to include the plural forms as well, unless the
context clearly indicates otherwise. Furthermore, the use of the
terms "a", "an", etc., do not denote a limitation of quantity, but
rather denote the presence of at least one of the referenced items.
It will be further understood that the terms "comprises" and/or
"comprising", or "includes" and/or "including", when used in this
specification, specify the presence of stated features, regions,
integers, steps, operations, elements, and/or components, but do
not preclude the presence or addition of one or more other
features, regions, integers, steps, operations, elements,
components, and/or groups thereof. Moreover, as used herein, the
term RAID means redundant array of independent disks (originally
redundant array of inexpensive disks). In general, RAID technology
is a way of storing the same data in different places (thus,
redundantly) on multiple hard disks. By placing data on multiple
disks, I/O (input/output) operations can overlap in a balanced way,
improving performance. Since multiple disks increase the mean time
between failures (MTBF), storing data redundantly also increases
fault tolerance.
[0015] Unless otherwise defined, all terms (including technical and
scientific terms) used herein have the same meaning as commonly
understood by one of ordinary skill in the art. It will be further
understood that terms such as those defined in commonly used
dictionaries should be interpreted as having a meaning that is
consistent with their meaning in the context of the relevant art
and the present disclosure, and will not be interpreted in an
idealized or overly formal sense unless expressly so defined
herein.
[0016] Hereinafter, a storage device of a PCI-Express (PCI-e) type
according to an embodiment will be described in detail with
reference to the accompanying drawings.
[0017] In general, embodiments of the present invention provide a
Semiconductor Storage Device (SSD) memory disk unit having multiple
host interface units. Specifically, in a typical embodiment, the
SSD memory disk unit comprises a plurality of host interface units
for coupling the SSD memory disk unit to at least one host; a host
interface controller unit coupled to each of the plurality of host
interface units; a DMA controller coupled to the host interface
controller unit; an ECC controller coupled to the DMA controller; a
memory controller coupled to the ECC controller; and a memory array
coupled to the memory controller, the memory array comprising at
least one SSD memory block.
[0018] The storage device of a PCI-Express (PCI-e) type supports a
low-speed data processing speed for a host by adjusting
synchronization of a data signal transmitted/received between the
host and a memory disk during data communications between the host
and the memory disk through a PCI-Express interface, and
simultaneously supports a high-speed data processing speed for the
memory disk, thereby supporting the performance of the memory to
enable high-speed data processing in an existing interface
environment at the maximum. It is understood in advance that
although PCI-Express technology will be utilized in a typical
embodiment, other alternatives are possible. For example, the
present invention could utilize Serial Attached Small Computer
System Interface (SAS)/Serial Advanced Technology Advancement
(SATA) technology in which a SAS/SATA type storage device is
provided that utilizes a SAS/SATA interface
[0019] Referring now to FIG. 1, a diagram schematically
illustrating a configuration of a PCI-Express type, RAID controlled
semiconductor storage device (e.g., for providing storage for a
serially attached computer device) according to an embodiment of
the invention is shown. As depicted, FIG. 1 shows a RAID controlled
PCI-Express type storage device 110 according to an embodiment of
the invention which includes a SSD memory disk unit 100 (referred
to herein as SSD memory disk unit, SSD, and/or SSD memory disk
unit) comprising: a plurality of memory disks having a plurality of
volatile semiconductor memories/memory units (also referred to
herein as high-speed SSD memory disk units 100); a RAID controller
800 coupled to SSD memory disk units 100; an interface unit 200
(e.g., PCI-Express host) which interfaces between the SSD memory
disk unit and a host; a controller unit 300; an auxiliary power
source unit 400 that is charged to maintain a predetermined power
using the power transferred from the host through the PCI-Express
host interface unit; a power source control unit 500 that supplies
the power transferred from the host through the PCI-Express host
interface unit to the controller unit 300, the SSD memory disk
units 100, the backup storage unit, and the backup control unit
which, when the power transferred from the host through the
PCI-Express host interface unit is blocked or an error occurs in
the power transferred from the host, receives power from the
auxiliary power source unit and supplies the power to the SSD
memory disk unit through the controller unit; a backup storage unit
600A-B that stores data of the SSD memory disk unit; and a backup
control unit 700 that backs up data stored in the SSD memory disk
unit in the backup storage unit, according to an instruction from
the host or when an error occurs in the power transmitted from the
host; and a redundant array of independent disks (RAID) controller
800 coupled to SSD memory disk unit 100, controller 300, and
internal backup controller 700.
[0020] The SSD memory disk unit 100 includes a plurality of memory
disks provided with a plurality of volatile semiconductor memories
for high-speed data input/output (for example, DDR, DDR2, DDR3,
SDRAM, and the like), and inputs and outputs data according to the
control of the controller 300. The SSD memory disk unit 100 may
have a configuration in which the memory disks are arrayed in
parallel.
[0021] The PCI-Express host interface unit 200 interfaces between a
host and the SSD memory disk unit 100. The host may be a computer
system or the like, which is provided with a PCI-Express interface
and a power source supply device.
[0022] The controller unit 300 adjusts synchronization of data
signals transmitted/received between the PCI-Express host interface
unit 200 and the SSD memory disk unit 100 to control a data
transmission/reception speed between the PCI-Express host interface
unit 200 and the SSD memory disk unit 100.
[0023] As depicted, a PCI-e type RAID controller 800 can be
directly coupled to any quantity of SSD memory disk units 100.
Among other things, this allows for optimum control of SSD memory
disk units 100. Among other things, the use of a RAID controller
800: [0024] 1. Supports the current backup/restore operations.
[0025] 2. Provides additional and improved backup function by
performing the following: [0026] a) the internal backup controller
700 determines the backup (user's request order or the status
monitor detects power supply problems); [0027] b) the internal
backup controller 700 requests a data backup to SSD memory disk
units; [0028] c) the internal backup controller 700 requests
internal backup device to backup data immediately; [0029] d) the
internal backup controller 700 monitors the status of the backup
for the SSD memory disk units and internal backup controller; and
[0030] e) the internal backup controller 700 reports the internal
backup controller's status and end-op. [0031] 3. Provides
additional and improved restore function by performing the
following: [0032] a) the internal backup controller 700 determines
the restore (user's request order or the status monitor detects
power supply problems); [0033] b) the internal backup controller
700 requests a data restore to the SSD memory disk units; [0034] c)
the internal backup controller 700 requests an internal backup
device to restore data immediately; [0035] d) the internal backup
controller 700 monitors the status of the restore for the SSD
memory disk units and internal backup controller; and [0036] e) the
internal backup controller 700 reports the internal backup
controller status and end-op.
[0037] Referring now to FIG. 2, a diagram schematically
illustrating a configuration of the high-speed SSD 100 is shown. As
depicted, SSD memory disk unit 100 comprises: a plurality of host
interface units 202A-N coupled to one another (e.g., PCI-Express
host) (which can be interface 200 of FIG. 1, or a separate
interface as shown) and for coupling/interfacing SSD memory disk
unit 100 with at least one host; a host interface controller unit
301 coupled to each host interface units 202A-N for controlling
host interface units 202A-N; a Direct Memory Access (DMA)
controller 302; an ECC controller 304; and a memory controller 306
for controlling one or more blocks 604 of memory 602 that are used
as high-speed storage. Also shown are backup controller 700 coupled
to DMA controller and backup storage unit 600A coupled to backup
controller 700.
[0038] In general, DMA is a feature of modern computers and
microprocessors that allows certain hardware subsystems within the
computer to access system memory for reading and/or writing
independently of the central processing unit. Many hardware systems
use DMA including disk drive controllers, graphics cards, network
cards, and sound cards. DMA is also used for intra-chip data
transfer in multi-core processors, especially in multiprocessor
system-on-chips, where its processing element is equipped with a
local memory (often called scratchpad memory) and DMA is used for
transferring data between the local memory and the main memory.
Computers that have DMA channels can transfer data to and from
devices with much less CPU overhead than computers without a DMA
channel. Similarly, a processing element inside a multi-core
processor can transfer data to and from its local memory without
occupying its processor time and allowing computation and data
transfer concurrency.
[0039] Without DMA, using programmed input/output (PIO) mode for
communication with peripheral devices, or load/store instructions
in the case of multi-core chips, the CPU is typically fully
occupied for the entire duration of the read or write operation,
and is thus unavailable to perform other work. With DMA, the CPU
would initiate the transfer, do other operations while the transfer
is in progress, and receive an interrupt from the DMA controller
once the operation has been done. This is especially useful in
real-time computing applications where not stalling behind
concurrent operations is critical.
[0040] Referring now to FIG. 3, the controller unit 300 of FIG. 1
is shown as comprising: a memory control module 310 which controls
data input/output of the SSD memory disk unit 100; a DMA control
module 320 which controls the memory control module 310 to store
the data in the SSD memory disk unit 100, or reads data from the
SSD memory disk unit 100 to provide the data to the host, according
to an instruction from the host received through the PCI-Express
host interface unit 200; a buffer 330 which buffers data according
to the control of the DMA control module 320; a synchronization
control module 340 which, when receiving a data signal
corresponding to the data read from the SSD memory disk unit 100 by
the control of the DMA control module 320 through the DMA control
module 320 and the memory control module 310, adjusts
synchronization of a data signal so as to have a communication
speed corresponding to a PCI-Express communications protocol to
transmit the synchronized data signal to the PCI-Express host
interface unit 200, and when receiving a data signal from the host
through the PCI-Express host interface unit 200, adjusts
synchronization of the data signal so as to have a transmission
speed corresponding to a communications protocol (for example, PCI,
PCI-x, or PCI-e, and the like) used by the SSD memory disk unit 100
to transmit the synchronized data signal to the SSD memory disk
unit 100 through the DMA control module 320 and the memory control
module 310; and a high-speed interface module 350 which processes
the data transmitted/received between the synchronization control
module 340 and the DMA control module 320 at high speed. Here, the
high-speed interface module 350 includes a buffer having a double
buffer structure and a buffer having a circular queue structure,
and processes the data transmitted/received between the
synchronization control module 340 and the DMA control module 320
without loss at high speed by buffering the data and adjusting data
clocks.
[0041] Referring back to FIG. 1, auxiliary power source unit 400
may be configured as a rechargeable battery or the like, so that it
is normally charged to maintain a predetermined power using power
transferred from the host through the PCI-Express host interface
unit 200 and supplies the charged power to the power source control
unit 500 according to the control of the power source control unit
500.
[0042] The power source control unit 500 supplies the power
transferred from the host through the PCI-Express host interface
unit 200 to the controller unit 300, the SSD memory disk unit 100,
the backup storage unit 600A-B, and the backup control unit
700.
[0043] In addition, when an error occurs in a power source of the
host because the power transmitted from the host through the
PCI-Express host interface unit 200 is blocked, or the power
transmitted from the host deviates from a threshold value, the
power source control unit 500 receives power from the auxiliary
power source unit 400 and supplies the power to the SSD memory disk
unit 100 through the controller unit 300.
[0044] The backup storage unit 600A-B is configured as a low-speed
non-volatile storage device such as a hard disk and stores data of
the SSD memory disk unit 100.
[0045] The backup control unit 700 backs up data stored in the SSD
memory disk unit 100 in the backup storage unit 600A-B by
controlling the data input/output of the backup storage unit 600A-B
and backs up the data stored in the SSD memory disk unit 100 in the
backup storage unit 600A-B according to an instruction from the
host, or when an error occurs in the power source of the host due
to a deviation of the power transmitted from the host deviates from
the threshold value.
[0046] The storage device of a serial-attached small computer
system interface/serial advanced technology attachment
(PCI-Express) type supports a low-speed data processing speed for a
host by adjusting synchronization of a data signal
transmitted/received between the host and a memory disk during data
communications between the host and the memory disk through a
PCI-Express interface, and simultaneously supports a high-speed
data processing speed for the memory disk, thereby supporting the
performance of the memory to enable high-speed data processing in
an existing interface environment at the maximum.
[0047] While the exemplary embodiments have been shown and
described, it will be understood by those skilled in the art that
various changes in form and details may be made thereto without
departing from the spirit and scope of this disclosure as defined
by the appended claims. In addition, many modifications can be made
to adapt a particular situation or material to the teachings of
this disclosure without departing from the essential scope thereof.
Therefore, it is intended that this disclosure not be limited to
the particular exemplary embodiments disclosed as the best mode
contemplated for carrying out this disclosure, but that this
disclosure will include all embodiments falling within the scope of
the appended claims.
[0048] The foregoing description of various aspects of the
invention has been presented for purposes of illustration and
description. It is not intended to be exhaustive or to limit the
invention to the precise form disclosed and, obviously, many
modifications and variations are possible. Such modifications and
variations that may be apparent to a person skilled in the art are
intended to be included within the scope of the invention as
defined by the accompanying claims.
* * * * *