U.S. patent application number 13/048023 was filed with the patent office on 2011-09-22 for semiconductor device.
This patent application is currently assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD.. Invention is credited to Hiromichi Godo, Suzunosuke Hiraishi, Takayuki Inoue, Erumu Kikuchi, Akiharu Miyanaga, Junichiro Sakata, Masashi Tsubuku, Shunpei Yamazaki.
Application Number | 20110227082 13/048023 |
Document ID | / |
Family ID | 44646532 |
Filed Date | 2011-09-22 |
United States Patent
Application |
20110227082 |
Kind Code |
A1 |
Inoue; Takayuki ; et
al. |
September 22, 2011 |
SEMICONDUCTOR DEVICE
Abstract
An oxide semiconductor layer in which "safe" traps exist
exhibits two kinds of modes in photoresponse characteristics. By
using the oxide semiconductor layer, a transistor in which light
deterioration is suppressed to the minimum and the electric
characteristics are stable can be achieved. The oxide semiconductor
layer exhibiting two kinds of modes in photoresponse
characteristics has a photoelectric current value of 1 pA to 10 nA
inclusive. When the average time .tau..sub.1 until which carriers
are captured by the "safe" traps is large enough, there are two
kinds of modes in photoresponse characteristics, that is, a region
where the current value falls rapidly and a region where the
current value falls gradually, in the result of a change in
photoelectric current over time.
Inventors: |
Inoue; Takayuki; (Isehara,
JP) ; Tsubuku; Masashi; (Atsugi, JP) ;
Hiraishi; Suzunosuke; (Atsugi, JP) ; Sakata;
Junichiro; (Atsugi, JP) ; Kikuchi; Erumu;
(Atsugi, JP) ; Godo; Hiromichi; (Isehara, JP)
; Miyanaga; Akiharu; (Hadano, JP) ; Yamazaki;
Shunpei; (Tokyo, JP) |
Assignee: |
SEMICONDUCTOR ENERGY LABORATORY
CO., LTD.
Atsugi-shi
JP
|
Family ID: |
44646532 |
Appl. No.: |
13/048023 |
Filed: |
March 15, 2011 |
Current U.S.
Class: |
257/59 ;
257/E29.273 |
Current CPC
Class: |
H01L 31/18 20130101;
H01L 27/1225 20130101; H01L 29/7869 20130101; H01L 31/032 20130101;
H01L 29/24 20130101; H01L 29/41733 20130101 |
Class at
Publication: |
257/59 ;
257/E29.273 |
International
Class: |
H01L 29/786 20060101
H01L029/786 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 19, 2010 |
JP |
2010-064751 |
Claims
1. A semiconductor device, comprising: an oxide semiconductor layer
at least a part of which overlaps with a gate electrode with a gate
insulating layer provided therebetween, wherein the oxide
semiconductor layer has a channel formation region, and wherein
photoresponse characteristics of the channel formation region of
the oxide semiconductor layer have two kinds of modes after light
irradiation is performed and a light source is turned off.
2. The semiconductor device according to claim 1, wherein the oxide
semiconductor layer has a photoelectric current value of greater
than or equal to 1 pA and less than or equal to 10 nA.
3. The semiconductor device according to claim 1, wherein the oxide
semiconductor layer comprises at least one of In, Zn, and Ga.
4. The semiconductor device according to claim 1, wherein a
photoelectric current value of the oxide semiconductor layer after
100 seconds of light irradiation is greater than or equal to 400
aA/.mu.m and less than or equal to 0.1 pA/.mu.m.
5. The semiconductor device according to claim 1, wherein the two
kinds of modes comprise a region where a photoelectric current
value of the oxide semiconductor layer falls rapidly and a region
where the photoelectric current value falls gradually, in a result
of a change in photoelectric current over time.
6. A semiconductor device comprising: a pixel porting including a
transistor, wherein a channel formation region of the transistor is
formed in an oxide semiconductor layer whose photoresponse
characteristics have two kinds of modes after light irradiation is
performed and a light source is turned off.
7. The semiconductor device according to claim 6, wherein the oxide
semiconductor layer has a photoelectric current value of greater
than or equal to 1 pA and less than of equal to 10 nA.
8. The semiconductor device according to claim 6, wherein the oxide
semiconductor layer comprises at least one of In, Zn, and Ga.
9. The semiconductor device according to claim 6, wherein a
photoelectric current value of the oxide semiconductor layer after
100 seconds of light irradiation is greater than or equal to 400
aA/.mu.m and less than or equal to 0.1 pA/.mu.m.
10. The semiconductor device according to claim 6, wherein the two
kinds of modes comprise a region where a photoelectric current
value of the oxide semiconductor layer falls rapidly and a region
where the photoelectric current value falls gradually, in a result
of a change in photoelectric current over time.
11. A semiconductor device, comprising: an oxide semiconductor
layer at least a part of which overlaps with a gate electrode with
a gate insulating layer provided therebetween, wherein the oxide
semiconductor layer has a channel formation region, and wherein
photoresponse characteristics of the channel formation region of
the oxide semiconductor layer have at least a first mode and a
second mode after light irradiation is performed and a light source
is turned off.
12. The semiconductor device according to claim 11, wherein the
first mode is a region where a photoelectric current value of the
oxide semiconductor layer falls rapidly and the second mode is a
region where the photoelectric current value of the oxide
semiconductor layer falls gradually, in a result of a change in
photoelectric current over time.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] One of embodiments of the present invention relates to a
semiconductor element such as a transistor and/or a semiconductor
device at least part of which is formed using the semiconductor
element. For example, an active element including an oxide
semiconductor is described as the semiconductor element, and a
display device including the active element is described.
[0003] 2. Description of the Related Art
[0004] Although transistors including amorphous silicon have been
used for conventional display devices typified by liquid crystal
televisions, an oxide semiconductor has attracted attention as a
material which replaces a silicon semiconductor in order to form
transistors. For example, an active matrix display device is
disclosed, in which an amorphous oxide containing In, Ga, and Zn is
used for an active layer of a transistor and the electron carrier
concentration of the amorphous oxide is less than
10.sup.18/cm.sup.3 (see Patent Document 1).
[0005] However, some problems of a transistor including an oxide
semiconductor have been pointed out. One of the problems is the
stability of the characteristics, and it is pointed out that the
electric characteristics of the transistor are changed by
irradiation with visible light and ultraviolet light.
REFERENCE
Patent Document
[0006] [Patent Document 1] Japanese Published Patent Application
No. 2006-165528
SUMMARY OF THE INVENTION
[0007] An oxide semiconductor formed of a metal oxide has a band
gap of about 3 eV and originally has a light-transmitting, property
with respect to visible light. However, it is known that a film
comprising the oxide semiconductor deteriorates when being
irradiated with strong light (the deterioration is called light
deterioration).
[0008] Any method for improving such a change in the
characteristics caused by light in a transistor including an oxide
semiconductor has not been proposed, which causes a delay in
practical use of the oxide semiconductor which is expected as a new
material.
[0009] In addition, a backlight is used in a liquid crystal display
device; when a transistor including an oxide semiconductor is
irradiated with light from the backlight, for example, leakage
current might be generated in an off state of the transistor owing
to photoexcitation, which leads to reduction in display quality, or
light deterioration might be caused. Further, it is known that a
single-layer oxide semiconductor film formed of a metal oxide has a
photoelectric current value of about 10 .mu.A.
[0010] It is an object of an embodiment of the present invention to
provide a transistor in which light deterioration is suppressed to
the minimum and the electric characteristics are stable.
[0011] The mechanism of photoelectric current will be described
below.
[0012] Carriers in a semiconductor can be described by continuity
equations, Formula 1 and Formula 2.
n t = 1 q .differential. J n .differential. x + ( G n - R n ) [
Formula 1 ] p t = - 1 q .differential. J p .differential. x + ( G p
- R p ) [ Formula 2 ] ##EQU00001##
[0013] Note that in the above two equations, t represents time, x
represents a position, and q represents a charge. Here, n and p
represent carrier density of electrons and carrier density of
holes, J.sub.n and J.sub.p represent a current value of electrons
and a current value of holes, G.sub.n and G.sub.p represent a
generation probability of electrons and a generation probability of
holes, and R.sub.n and R.sub.p represent a recombination
probability of electrons and a recombination probability of holes.
The number of hole carriers is divided into the number of hole
carriers p.sub.0 in a thermal equilibrium state and the number of
hole carriers .DELTA.p in a non-thermal equilibrium state. The
carrier density of holes can be expressed by Formula 3.
p=p.sub.0+.DELTA.P [Formula 3]
[0014] When the semiconductor is irradiated with light having an
energy of greater than or equal to the band gap, electrons in the
valence band are transferred to the conduction band while the
semiconductor absorbs the light, whereby holes are generated. When
the generation probability of holes is represented by G.sub.0p, the
recombination probability is expressed by Formula 4. Here,
.tau..sub.p represents relaxation time of holes.
R = p .tau. p = p 0 .tau. p + .DELTA. p .tau. p [ Formula 4 ]
##EQU00002##
[0015] When a device is uniformly irradiated with light, a
continuity equation represented by Formula 5 is obtained if a
diffusion term in a source direction or a drain direction can be
ignored.
( .DELTA. p ) t = G op - R = G op - .DELTA. p .tau. p [ Formula 5 ]
##EQU00003##
[0016] Formula 5 is solved with an initial photoelectric current
value at 0, which leads to a carrier concentration expressed by
Formula 6.
.DELTA. p ( t ) = G op .tau. p [ 1 - exp ( - t .tau. p ) ] [
Formula 6 ] ##EQU00004##
[0017] When the time at which a light source is turned off is
represented by t.sub.0, the carrier concentration is expressed by
Formula 7.
.DELTA. p ( t ) = .DELTA. p ( t 0 ) exp ( - t - t 0 .tau. p ) ( t
.gtoreq. t 0 ) [ Formula 7 ] ##EQU00005##
[0018] Since the photoelectric current is in proportion to the
excess carrier concentration, the current formula is expressed by
Formula 8.
I ( t ) = { I 0 [ 1 - exp ( - t .tau. p ) ] ( 0 .ltoreq. t .ltoreq.
t 0 ) I 0 [ 1 - exp ( - t 0 .tau. p ) ] exp ( - t - t 0 .tau. p ) (
t .gtoreq. t 0 ) [ Formula 8 ] ##EQU00006##
[0019] (I.sub.o depends on constant, physical property, and
structure.)
[0020] The relaxation time .tau. depends on a model of carrier
recombination. There are many types of recombination processes.
Basically, two types of processes, direct recombination and
indirect recombination (SRH recombination), can be given.
[0021] Further, for example, some traps can capture a hole but
cannot easily capture an electron, where recombination hardly
occurs. Such a trap is called a "safe" trap in this
specification.
[0022] FIG. 6A is a schematic diagram of the "safe" trap. FIG. 6B
is a schematic diagram showing a transition due to heat after
trapping.
[0023] Since the position of the "safe" trap is closer to the
valence band than the intrinsic Fermi level and an electron is not
easily captured by the "safe" trap, part of holes captured by the
"safe" traps are transferred to the valence band by heat and thus
contribute to electric conduction. A semiconductor in which the
"safe" traps exist exhibits two kinds of modes in
photoresponse.
[0024] According to an embodiment of the present invention
disclosed in this specification, an oxide semiconductor layer which
exhibits two kinds of modes in photoresponse is used, whereby a
transistor in which light deterioration is suppressed to the
minimum and the electric characteristics are stable is achieved.
Note that the oxide semiconductor layer which exhibits two kinds of
modes in photoresponse has a photoelectric current value of greater
than or equal to 1 pA, preferably greater than or equal to 10 pA
and less than or equal to 10 nA. In addition, in the oxide
semiconductor layer, a photoelectric current value after 100
seconds of light irradiation is greater than or equal to 400
aA/.mu.m and less than or equal to 0.1 pA/.mu.m at 25.degree. C.
and light deterioration can be suppressed to the minimum.
[0025] When the average time .tau..sub.1 until which carriers are
captured by "safe" traps is large enough, there are two kinds of
modes in photoresponse, that is, a region where the current value
falls rapidly and a region where the current value falls gradually,
in the result of a change in photoelectric current over time.
[0026] In consideration of the "safe" trap, the current formula
after .tau..sub.1 (when almost all excess carriers are captured by
the "safe" traps) is expressed by Formula 9. Note that .tau..sub.2
represents average time during which carriers stay at the "safe"
traps.
I ( t ) = A .tau. p ( D e D h .tau. 2 .tau. 1 ) exp ( - t .tau. 2 )
( t .gtoreq. .tau. 1 ) [ Formula 9 ] ##EQU00007##
A: constant depending on physical property or temperature
D.sub.e,D.sub.h: diffusion coefficient of electron and diffusion
coefficient of hole .tau..sub.p: relaxation time of hole in thermal
equilibrium
[0027] Estimation of trap levels corresponding to .tau..sub.1 and
.tau..sub.2 leads to evaluation of defects. Such a method for
evaluation with the use of .tau..sub.1 and .tau..sub.2 is referred
to as a photoresponse defect evaluation method (PDEM).
[0028] A liquid crystal display device in which a transistor
including an oxide semiconductor is provided in a pixel has high
reliability with respect to light deterioration.
BRIEF DESCRIPTION OF THE DRAWINGS
[0029] FIG. 1 is a graph showing photoresponse characteristics of
oxide semiconductor layers.
[0030] FIG. 2 is a graph enlarging a region in the range of 0 sec
to 100 sec in FIG. 1.
[0031] FIG. 3 is a graph showing photoresponse characteristics of
oxide semiconductor layers with the use of a logarithmic scale.
[0032] FIG. 4 is a graph showing photoresponse characteristics of
oxide semiconductor layers with the use of a linear scale.
[0033] FIG. 5 is a graph for showing a method for estimating
.tau..sub.1 with the use of data in FIG. 2.
[0034] FIGS. 6A and 6B are schematic diagrams of a "safe" trap.
[0035] FIG. 7A is a top view of an electrode and FIG. 7B is a
cross-sectional view illustrating the structure of a TEG.
[0036] FIGS. 8A to 8D are cross-sectional views each illustrating
the structure of a transistor.
[0037] FIG. 9 is a graph showing the emission spectrum of a white
LED.
DETAILED DESCRIPTION OF THE INVENTION
[0038] Hereinafter, embodiments of the present invention will be
described in detail with reference to the accompanying drawings.
However, the present invention is not limited to the description
below, and it is easily understood by those skilled in the art that
modes and details thereof can be modified in various ways.
Therefore, the present invention is not construed as being limited
to the description of the embodiments.
Embodiment 1
[0039] In this embodiment, a TEG was manufactured with the use of
an oxide semiconductor. With the use of the TEG, the photoresponse
characteristics of the oxide semiconductor before and after
irradiation with light (luminance: 17000 cd/cm.sup.2) for 600
seconds were measured. By using the result thereof, a graph of the
photoresponse characteristics (a graph showing time dependence of
photoelectric current) is made.
[0040] The structure of the TEG used for evaluation is as follows:
the channel length (L) is 200 .mu.m, the channel width (W) is 2.09
cm, the thickness of a thick portion of an In--Ga--Zn--O film is 50
nm, and the thickness of a thin portion of the In--Ga--Zn--O film
is 25 nm. The cross-sectional structure of this TEG is illustrated
in FIG. 7B. In FIG. 7B, an In--Ga--Zn--O film 102 is formed over a
glass substrate 101, and a first electrode 103 and a second
electrode 104 are formed over the In--Ga--Zn--O film 102. FIG. 7A
illustrates the top shapes of the first electrode 103 and the
second electrode 104. The space between the first electrode 103 and
the second electrode 104 is 200 .mu.m, and a region of the
In--Ga--Zn--O film 102 which overlaps with the region between the
first electrode 103 and the second electrode 104 is 25 nm, which is
thinner than a region overlapping with the first electrode 103 or
the second electrode 104 as illustrated in FIG. 7B. In addition, an
insulating layer 105 is formed over the first electrode 103 and the
second electrode 104 so as to prevent the In--Ga--Zn--O film 102
from being exposed.
[0041] A white LED (MDBL-CW100 produced by Moritex Corporation) was
used as a light source for emitting light with which the
In--Ga--Zn--O film 102 was irradiated. The emission spectrum of
this white LED is shown in FIG. 9.
[0042] In order to observe the temperature characteristics, three
samples were manufactured and the temperature characteristics were
measured at 25.degree. C., 85.degree. C., and 150.degree. C. by
using the three samples. The manufacturing process of the three
samples will be described below.
[0043] An In--Ga--Zn--O film is formed to a thickness of 50 nm by a
sputtering method with the use of an oxide target having a
composition ratio of In.sub.2O.sub.3:Ga.sub.2O.sub.3:ZnO=1:1:1
[molar ratio] over a glass substrate (126.6 mm.times.126.6 mm). The
film formation conditions of the In--Ga--Zn--O film are as follows:
the film formation temperature is room temperature, the flow of
argon is 10 sccm, the flow of oxygen is 5 sccm, the pressure is 0.4
Pa, and the power is 500 W.
[0044] Then, heat treatment is performed at 450.degree. C. for 1
hour in a nitrogen atmosphere. This heat treatment is preferably
performed in an atmosphere of nitrogen or a rare gas such as
helium, neon, or argon in which water, hydrogen, or the like is not
contained, for example, the dew point is lower than or equal to
-40.degree. C., preferably lower than or equal to -60.degree. C. It
is preferable that the purity of nitrogen or a rare gas such as
helium, neon, or argon which is introduced into a heat treatment
apparatus be set to be greater than or equal to 6N (99.9999%),
preferably greater than or equal to 7N (99.99999%) (that is, the
impurity concentration is less than or equal to 1 ppm, preferably
less than or equal to 0.1 ppm).
[0045] After the heat treatment, a layered conductive film is
formed by stacking a titanium nitride film with a thickness of 50
nm, a titanium film with a thickness of 50 nm, an aluminum film
with a thickness of 200 nm, and a titanium film with a thickness of
50 nm by a sputtering method.
[0046] A resist mask is formed over the layered conductive film
through a photolithography step, and etching is performed
selectively to form the first electrode 103 and the second
electrode 104. After that, O.sub.2 ashing is performed, whereby a
part of the In--Ga--Zn--O film which is exposed is thinned to 25
nm, and then, the resist mask is removed.
[0047] Next, by a sputtering method with the use of a silicon oxide
target, a silicon oxide film with a thickness of 300 nm is formed
over the first electrode 103 and the second electrode 104.
[0048] Then, a resist mask is formed over the silicon oxide film
through a photolithography step, and etching is performed
selectively to form the insulating layer 105. After that, heat
treatment is performed at 250.degree. C. for 1 hour in a nitrogen
atmosphere.
[0049] Finally, the glass substrate is divided into a plurality of
pieces such that one TEG is placed in each piece having an area of
10 mm.times.10 mm. After irradiation with white light having a
luminance of 17000 cd/cm.sup.2 for 600 seconds, measurement was
performed by setting the time right after the light source is
turned off to 0. FIG. 1 is a graph showing the photoresponse
characteristics of oxide semiconductor layers. In FIG. 1, the
horizontal axis indicates time and the vertical axis indicates a
current value. The light source is turned off at time 0. FIG. 2 is
a graph enlarging a region in the range of 0 sec to 100 sec in FIG.
1.
[0050] Table 1 is a list showing numerical values in FIG. 1. A
photoelectric current value per micrometer shown in Table 1 was
obtained by calculation. The photoelectric current value per
micrometer after 100 seconds of irradiation of the oxide
semiconductor layer with light at 25.degree. C. was found to be 593
pA/.mu.m.
TABLE-US-00001 TABLE 1 Ioff per Measurement 0 sec 10 sec 100 sec
500 sec 1000 sec micrometer after Temperature (A) (A) (A) (A) (A)
100 sec (A) 25.degree. C. 3.27E-10 3.33E-11 1.19E-11 6.31E-12
5.51E-12 5.93E-14 85.degree. C. 4.14E-10 7.84E-11 4.4E-11 2.56E-11
2.123E-11 2.202E-13 150.degree. C. 7.86E-10 1.95E-10 8.84E-11
3.61E-11 2.027E-11 4.422E-13
[0051] Other TEGs were manufactured under conditions partly
different from those of the above three samples. The film formation
conditions of the In--Ga--Zn--O film of a fourth sample and a fifth
sample are as follows: the film formation temperature is room
temperature, the flow of argon is 10.5 sccm, the flow of oxygen is
4.5 sccm, and the power is 100 W. Note that other film formation
conditions and the film thickness are the same as the above three
samples.
[0052] The fourth sample was subjected to heat treatment at
650.degree. C. for 1 hour in a nitrogen atmosphere. The fifth
sample was subjected to heat treatment at 650.degree. C. for 1 hour
in a nitrogen atmosphere and then heat treatment at 450.degree. C.
for 1 hour in an atmosphere containing oxygen and nitrogen.
[0053] The steps after the heat treatment are performed in the same
manner as the above three samples, so that the TEGs were
manufactured.
[0054] After irradiation with white light having a luminance of
17000 cd/cm.sup.2 for 600 seconds, the photoresponse
characteristics after the light source was turned off were
measured. The result of measuring the photoresponse characteristics
of the fourth sample is expressed by "OS film 1", and the result of
measuring the photoresponse characteristics of the fifth sample is
expressed by "OS film 2", which are shown in FIG. 3 with the use of
a logarithmic scale. In addition, after irradiation with white
light having a luminance of 17000 cd/cm.sup.2 for 600 seconds, the
light source was turned off and time right after the light source
was turned off was set to 0. The result of measuring the
photoresponse characteristics under this condition is shown in FIG.
4 with the use of a linear scale. According to FIG. 3 and FIG. 4, a
single-layer oxide semiconductor film (OS film 1) formed using a
metal oxide which was used as a comparative example has a
photoelectric current value of about greater than or equal to 1
.mu.A and less than or equal to 10 .mu.A. On the other hand, a
single-layer oxide semiconductor film (OS film 2) of this
embodiment has a photoelectric current value of about greater than
or equal to 10 pA and less than or equal to 10 nA. In the case of
the single-layer oxide semiconductor film (OS film 2) of this
embodiment, the rise and the fall of the photoresponse
characteristics are sharp, and the current value is very small.
Also in the case of using light having a wavelength of 350 nm,
which is considered to have an energy that is greater than or equal
to the band gap, a tendency similar to the above is observed.
[0055] Fitting of .tau..sub.2 can be performed using the current
formula expressed by Formula 9. A region in the range of 20 sec to
100 sec in FIG. 2 which is a graph using a logarithmic scale was
plotted with the use of a linear scale, and fitting was performed.
FIG. 5 shows a method for estimating .tau..sub.1.
[0056] Since the temporal resolution is 1 [sec], sharpness around
time 0 [sec] right after the light source is turned off cannot be
correctly measured, and .tau..sub.1 might be estimated to be larger
than the real value. Table 2 shows .tau..sub.1 and .tau..sub.2 at
following temperatures.
TABLE-US-00002 25.degree. C. 85.degree. C. 150.degree. C.
.tau..sub.1 [sec] 2.3 1.6 1.5 .tau..sub.2 [sec] 350 480 340
[0057] Since .tau..sub.1 can be regarded as substantially the same
at all temperatures in consideration of the temporal resolution for
measurement, .tau..sub.2 does not depend on the temperature,
either. This is because .tau..sub.1 and .tau..sub.2 depend on the
trap density. On the other hand, according to FIG. 2, as the
temperature is higher, the rate of reduction in current is small.
This is because the probability of thermal excitation from the
traps is higher as the temperature is higher.
[0058] The curve showing the photoresponse characteristics has two
kinds of modes because "safe" traps exist around the conduction
band or the valence band. When fitting is performed to obtain the
rapid relaxation time .tau..sub.1 and the gradual relaxation time
.tau..sub.2, it is found that these two kinds of relaxation time
(.tau..sub.1 and .tau..sub.2) less depend on the temperature but
depend on the trap density, and it can be said from the temperature
dependence of reduction in current that the traps exist at very
shallow levels.
[0059] The channel length was varied, and the measurement was
performed under the conditions shown in Table 1. The structures of
the TEGs used for evaluation are as follows: the channel length (L)
was set to 50 .mu.m, 100 .mu.m, and 200 .mu.m in respective TEGs,
and the channel width (W) was set to 2.09 cm. The measurement
results are shown in Table 3. Note that the measurement temperature
is 25.degree. C. A photoelectric current value per micrometer was
obtained by calculation and shown in Table 3. In the TEG in which
the channel length (L) is 50 .mu.m, after 100 seconds of
irradiation of the oxide semiconductor layer with light, a
photoelectric current value per micrometer of channel length is
97.7 fA/.mu.m. In the TEG in which the channel length (L) is 100
.mu.m, after 100 seconds of irradiation of the oxide semiconductor
layer with light, a photoelectric current value per micrometer of
channel length is 42.5 fA/.mu.m. In the TEG in which the channel
length (L) is 200 .mu.m, after 100 seconds of irradiation of the
oxide semiconductor layer with light, a photoelectric current value
per micrometer of channel length is 13.7 fA/.mu.m. In the TEG in
which the channel length (L) is 500 .mu.m, after 100 seconds of
irradiation of the oxide semiconductor layer with light, a
photoelectric current value per micrometer of channel length is 413
aA/.mu.m. As described above, at 25.degree. C., the oxide
semiconductor layer has a photoelectric current value of greater
than or equal to 400 aA/.mu.m and less than or equal to 0.1
pA/.mu.m after 100 seconds of light irradiation, which means that
light deterioration is suppressed to the minimum. Therefore, a
transistor whose electric characteristics are stable can be
achieved by using the oxide semiconductor layer.
TABLE-US-00003 TABLE 3 Ioff per Ioff after Ioff after Ioff after
micrometer after L (.mu.m) Ion (A) 1 sec (A) 10 sec (A) 100 sec (A)
100 sec (A) 50 3.2704E-08 6.707E-11 1.39891E-11 4.88727E-12
9.77455E-14 100 2.19308E-08 9.256E-11 1.28518E-11 4.24727E-12
4.24727E-14 200 7.1513E-09 9.15E-12 2.19636E-12 2.73364E-12
1.36682E-14 500 1.7527E-09 2.34E-12 1.25455E-12 2.06364E-13
4.12727E-16
[0060] In this embodiment, a TEG is shown as an example, but the
present invention is not limited thereto. For example, in a
transistor including the same oxide semiconductor, light
deterioration can be suppressed to the minimum and the electric
characteristics can be stable. In addition, a liquid crystal
display device in which a transistor including the same oxide
semiconductor is provided in a pixel has high reliability with
respect to light deterioration.
Embodiment 2
[0061] In this embodiment, an example of a transistor that can be
applied to a liquid crystal display device disclosed in this
specification will be described. There is no particular limitation
on the structure of a transistor which can be applied to a liquid
crystal display device disclosed in this specification. For
example, a staggered type and a planar type of a top-gate structure
or a bottom-gate structure can be used. Further, the transistor may
have a single gate structure including one channel formation
region, a double gate structure including two channel formation
regions, or a triple gate structure including three channel
formation regions. Alternatively, the transistor may have a dual
gate structure including two gate electrode layers positioned over
and below a channel region with a gate insulating layer provided
therebetween. FIGS. 8A to 8D each illustrate an example of the
cross-sectional structure of a transistor. The transistors
illustrated in FIGS. 8A to 8D each include an oxide semiconductor
as a semiconductor. An advantage of using an oxide semiconductor is
that high mobility and low off-state current can be obtained
through a relatively easy and low-temperature process.
[0062] A transistor 410 illustrated in FIG. 8A is a kind of
bottom-gate thin film transistor, and is also referred to as an
inverted-staggered thin film transistor.
[0063] The transistor 410 includes, over a substrate 400 having an
insulating surface, a gate electrode layer 401, a gate insulating
layer 402, an oxide semiconductor layer 403, a source electrode
layer 405a, and a drain electrode layer 405b. Further, an
insulating layer 407 stacked over the oxide semiconductor layer 403
is provided so as to cover the transistor 410. A protective
insulating layer 409 is formed over the insulating layer 407.
[0064] The insulating layer 407 is in contact with the oxide
semiconductor layer 403 and can be formed using a material such as
GaOx (x>0), SiOx (x>0), or nitride (except for titanium
nitride). In particular, when GaOx is used, the insulating layer
407 can function as a film for preventing electrification of a back
channel.
[0065] A transistor 420 illustrated in FIG. 8B has a kind of
bottom-gate structure referred to as a channel-protective type
(channel-stop type) and is also referred to as an
inverted-staggered thin film transistor.
[0066] The transistor 420 includes, over a substrate 400 having an
insulating surface, a gate electrode layer 401, a gate insulating
layer 402, an oxide semiconductor layer 403, an insulating layer
427 which functions as a channel protective layer covering a
channel formation region of the oxide semiconductor layer 403, a
source electrode layer 405a, and a drain electrode layer 405b.
Further, a protective insulating layer 409 is formed so as to cover
the transistor 420.
[0067] A transistor 430 illustrated in FIG. 8C is a bottom-gate
thin film transistor and includes, over a substrate 400 which is a
substrate having an insulating surface, a gate electrode layer 401,
a gate insulating layer 402, a source electrode layer 405a, a drain
electrode layer 405b, and an oxide semiconductor layer 403.
Further, an insulating layer 407 being in contact with the oxide
semiconductor layer 403 is provided so as to cover the transistor
430. A protective insulating layer 409 is formed over the
insulating layer 407.
[0068] In the transistor 430, the gate insulating layer 402 is
provided on and in contact with the substrate 400 and the gate
electrode layer 401, and the source electrode layer 405a and the
drain electrode layer 405b are provided on and in contact with the
gate insulating layer 402. Further, the oxide semiconductor layer
403 is provided over the gate insulating layer 402, the source
electrode layer 405a, and the drain electrode layer 405b.
[0069] A transistor 440 illustrated in FIG. 8D is a kind of
top-gate thin film transistor. The transistor 440 includes, over a
substrate 400 having an insulating surface, an insulating layer
437, an oxide semiconductor layer 403, a source electrode layer
405a, a drain electrode layer 405b, a gate insulating layer 402,
and a gate electrode layer 401. A wiring layer 436a and a wiring
layer 436b are provided in contact with and electrically connected
to the source electrode layer 405a and the drain electrode layer
405b, respectively.
[0070] In this embodiment, as described above, the oxide
semiconductor layer 403 is used as a semiconductor layer. As an
oxide semiconductor used for the oxide semiconductor layer 403, a
four-component metal oxide such as an In--Sn--Ga--Zn--O-based oxide
semiconductor; a three-component metal oxide such as an
In--Ga--Zn--O-based oxide semiconductor, an In--Sn--Zn--O-based
oxide semiconductor, an In--Al--Zn--O-based oxide semiconductor, a
Sn--Ga--Zn--O-based oxide semiconductor, an Al--Ga--Zn--O-based
oxide semiconductor, or a Sn--Al--Zn--O-based oxide semiconductor;
a two-component metal oxide such as an In--Zn--O-based oxide
semiconductor, a Sn--Zn--O-based oxide semiconductor, an
Al--Zn--O-based oxide semiconductor, a Zn--Mg--O-based oxide
semiconductor, a Sn--Mg--O-based oxide semiconductor, an
In--Ga--O-based oxide semiconductor, or an In--Mg--O-based oxide
semiconductor; or an In--O-based oxide semiconductor layer, a
Sn--O-based oxide semiconductor, or a Zn--O-based oxide
semiconductor, or the like can be used. Further, SiO.sub.2 may be
contained in the above oxide semiconductor. Here, for example, the
In--Ga--Zn--O-based oxide semiconductor means an oxide containing
at least In, Ga, and Zn, and the composition ratio of the elements
is not particularly limited. The In--Ga--Zn--O-based oxide
semiconductor may contain an element other than In, Ga, and Zn.
[0071] In addition, as the oxide semiconductor layer 403, a thin
film of a material represented by a chemical formula,
InMO.sub.3(ZnO).sub.m (m>0), can be used. Here, M represents one
or more metal elements selected from Ga, Al, Mn, and Co. For
example, M can be Ga, Ga and Al, Ga and Mn, Ga and Co, or the
like.
[0072] In the case where an In--Zn--O-based material is used as the
oxide semiconductor, a target to be used has a composition ratio of
In:Zn=50:1 to 1:2 in an atomic ratio (In.sub.2O.sub.3:ZnO=25:1 to
1:4 in a molar ratio), preferably In:Zn=20:1 to 1:1 in an atomic
ratio (In.sub.2O.sub.3:ZnO=10:1 to 1:2 in a molar ratio), more
preferably In:Zn=15:1 to 1.5:1 in an atomic ratio
(In.sub.2O.sub.3:ZnO=15:2 to 3:4 in a molar ratio). For example,
when a target used for forming the In--Zn--O-based oxide
semiconductor has a composition ratio of In:Zn:O X:Y:Z in an atomic
ratio, Z>(1.5X+Y).
[0073] The oxide semiconductor layer 403 in each of the transistors
410, 420, 430, and 440 is preferably heated at a temperature of
higher than or equal to 450.degree. C. in an atmosphere which does
not contain moisture and hydrogen. For example, heat treatment is
performed at 650.degree. C. for 1 hour in a nitrogen atmosphere and
then heat treatment is performed at 450.degree. C. for 1 hour in an
atmosphere containing nitrogen and oxygen. The heat treatment may
be performed with the use of ultra-dry air (in which the dew point
is lower than or equal to -40.degree. C., preferably lower than or
equal to -60.degree. C.) as an atmosphere containing nitrogen and
oxygen. With this heat treatment, light deterioration can be
suppressed to the minimum, and a transistor whose electric
characteristics are stable can be provided.
[0074] In the transistors 410, 420, 430, and 440 each including the
oxide semiconductor layer 403, the amount of current in an off
state (off-state current) can be small. Therefore, by using the
transistor including the oxide semiconductor layer 403 in a pixel
portion of a liquid crystal display device, an electric signal such
as image data can be held for a longer period and a writing
interval can be set longer. Accordingly, frequency of refresh
operation can be reduced, which leads to an effect of suppressing
power consumption.
[0075] In addition, the transistors 410, 420, 430, and 440 each
including the oxide semiconductor layer 403 can have relatively
high field-effect mobility and thus can operate at high speed.
Therefore, by using any of the above transistors in a pixel portion
of a liquid crystal display device, a high-quality image can be
provided. In addition, since a driver circuit portion and the pixel
portion can be manufactured over one substrate with the use of the
transistor including the oxide semiconductor layer 403, the number
of components of the liquid crystal display device can be
reduced.
[0076] Although there is no particular limitation on a substrate
that can be used as the substrate 400 having an insulating surface,
a glass substrate made of barium borosilicate glass,
aluminoborosilicate glass, or the like can be used.
[0077] In the bottom-gate transistors 410, 420, and 430, an
insulating film serving as a base film may be provided between the
substrate and the gate electrode layer. The base film has a
function of preventing diffusion of impurity elements from the
substrate, and can be formed to have a single-layer structure or a
layered structure using one or more of a silicon nitride film, a
silicon oxide film, a silicon nitride oxide film, and a silicon
oxynitride film.
[0078] The gate electrode layer 401 can be formed to have a
single-layer structure or a layered structure using a metal
material such as molybdenum, titanium, chromium, tantalum,
tungsten, aluminum, copper, neodymium, or scandium, or an alloy
material which contains any of these materials as its main
component.
[0079] The gate insulating layer 402 can be formed with a
single-layer structure or a layered structure using one or more of
a silicon oxide layer, a silicon nitride layer, a silicon
oxynitride layer, a silicon nitride oxide layer, an aluminum oxide
layer, an aluminum nitride layer, an aluminum oxynitride layer, an
aluminum nitride oxide layer, and a hafnium oxide layer by a plasma
CVD method, a sputtering method, or the like. For example, by a
plasma CVD method, a silicon nitride layer (SiN.sub.y (y>0))
with a thickness of greater than or equal to 50 nm and less than or
equal to 200 nm is formed as a first gate insulating layer, and a
silicon oxide layer (SiO.sub.x (x>0)) with a thickness of
greater than or equal to 5 nm and less than or equal to 300 nm is
formed as a second gate insulating layer over the first gate
insulating layer, so that a gate insulating layer with a total
thickness of 200 nm is formed.
[0080] As a conductive film used for the source electrode layer
405a and the drain electrode layer 405b, for example, a film of an
element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, a film of an
alloy containing any of these elements as its component, a film of
an alloy containing any of these elements in combination, or the
like can be used. The conductive film may have a structure in which
a high-melting-point metal layer of Ti, Mo, W, or the like is
stacked over and/or below a metal layer of Al, Cu, or the like.
When an Al material to which an element (e.g., Si, Nd, or Sc) which
prevents generation of hillocks and whiskers in an Al film is added
is used, heat resistance can be increased.
[0081] A material similar to that for the source electrode layer
405a and the drain electrode layer 405b can be used for a
conductive film used for the wiring layer 436a and the wiring layer
436b which are respectively connected to the source electrode layer
405a and the drain electrode layer 405b.
[0082] Alternatively, the conductive film used for the source
electrode layer 405a and the drain electrode layer 405b (including
a wiring layer formed using the same layer as the source electrode
layer 405a and the drain electrode layer 405b) may be formed using
a conductive metal oxide. As the conductive metal oxide, indium
oxide (In.sub.2O.sub.3), tin oxide (SnO.sub.2), zinc oxide (ZnO),
indium oxide-tin oxide alloy (In.sub.2O.sub.3--SnO.sub.2;
abbreviated to ITO), indium oxide-zinc oxide alloy
(In.sub.2O.sub.3--ZnO), or any of these metal oxide materials in
which silicon oxide is contained can be used.
[0083] As the insulating layers 407, 427, and 437, an inorganic
insulating film, typically, a silicon oxide film, a silicon
oxynitride film, an aluminum oxide film, or an aluminum oxynitride
film, can be used.
[0084] For the protective insulating layer 409, an inorganic
insulating film such as a silicon nitride film, an aluminum nitride
film, a silicon nitride oxide film, or an aluminum nitride oxide
film can be used.
[0085] Further, a planarization insulating film may be formed over
the protective insulating layer 409 so that surface roughness due
to the transistor can be reduced. For the planarization insulating
film, an organic material such as polyimide, acrylic, or
benzocyclobutene can be used. Other than such organic materials, it
is also possible to use a low-dielectric constant material (a low-k
material) or the like. Alternatively, the planarization insulating
film may be formed by stacking a plurality of insulating films
formed from these materials.
[0086] As described above, in this embodiment, a high-performance
liquid crystal display device can be provided by using the
transistor including the oxide semiconductor layer.
[0087] This application is based on Japanese Patent Application
serial no. 2010-064751 filed with Japan Patent Office on Mar. 19,
2010, the entire contents of which are hereby incorporated by
reference.
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