U.S. patent application number 13/116282 was filed with the patent office on 2011-09-15 for method for fabricating semiconductor memoery device.
This patent application is currently assigned to Hynix Semiconductor Inc.. Invention is credited to Song Hyeuk IM.
Application Number | 20110220993 13/116282 |
Document ID | / |
Family ID | 42264773 |
Filed Date | 2011-09-15 |
United States Patent
Application |
20110220993 |
Kind Code |
A1 |
IM; Song Hyeuk |
September 15, 2011 |
METHOD FOR FABRICATING SEMICONDUCTOR MEMOERY DEVICE
Abstract
A method for manufacturing a semiconductor device comprises
forming a first spacer layer at sidewalls of one or more gate
electrodes, forming a trench by etching an isolation insulating
layer exposed between the gate electrodes, forming a second spacer
layer on sidewalls of the gate electrodes and an inner surface of
the trench and forming an interlayer insulating layer between the
gate electrodes.
Inventors: |
IM; Song Hyeuk;
(Cheongju-si, KR) |
Assignee: |
Hynix Semiconductor Inc.
Icheon-si
KR
|
Family ID: |
42264773 |
Appl. No.: |
13/116282 |
Filed: |
May 26, 2011 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
12493069 |
Jun 26, 2009 |
7977188 |
|
|
13116282 |
|
|
|
|
Current U.S.
Class: |
257/330 ;
257/E29.242 |
Current CPC
Class: |
H01L 21/76224 20130101;
H01L 27/10823 20130101; H01L 27/10876 20130101 |
Class at
Publication: |
257/330 ;
257/E29.242 |
International
Class: |
H01L 29/772 20060101
H01L029/772 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 23, 2008 |
KR |
10-2008-0132417 |
Claims
1 -11. (canceled)
12. A semiconductor device, comprising: a substrate including an
active region and a field isolation region adjacent to the active
region; a first recess gate electrode formed in the active region
and a second recess gate electrode formed in the field isolation
region; a first spacer formed over sidewalls of the first recess
gate electrode and the second recess gate electrode; a trench
formed at side of the second recess gate electrode in the field
isolation region; and a second spacer over the first spacer in the
active region, over the first spacer in the field isolation region,
and over surfaces of the trench.
13. The semiconductor device according to claim 12, wherein the
trench exposes a lower sidewall of the second recess gate
electrode, and the second spacer covers the exposed lower sidewall
of the second recess gate electrode.
14. The semiconductor device according to claim 12, the
semiconductor device further comprising: a first contact hole
defined by the second spacer, the first contact hole exposing a
surface of the active region; and a second contact hole defined by
the second spacer in the field isolation region.
15. The semiconductor device according to claim 14, the
semiconductor device further comprising: a first conductive contact
formed in the first contact hole; and a second conductive contact
formed in the second contact hole.
16. The semiconductor device according to claim 14, wherein the
first conductive contact is a bit line contact or a storage node
contact.
17. The semiconductor device according to claim 12, wherein the
trench has a protruding bottom end extending laterally to the
sidewall of the second recess gate electrode.
18. The semiconductor device according to claim 12, wherein the
trench is formed to a depth of about 300.ANG. to about 1000.ANG..
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The priority based on Korean patent application No.
10-2008-0132417 filed on Dec. 23, 2008, the disclosure of which is
hereby incorporated in its entirety by reference, is claimed.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a method for fabricating a
highly-integrated semiconductor device, and more specifically, to a
method for forming a unit cell capable of making a semiconductor
device operate faster and more stable.
[0003] A semiconductor memory chip includes a plurality of unit
cells each of which includes a capacitor and a transistor. A double
capacitor has been used to temporarily store data. A transistor
transmits data between a bit line and a capacitor according to a
control signal (word line). The transistor has three regions
including a gate, a source and a drain, and electrical charges move
between the source and the drain in response to a control signal
which is applied to the gate. The electrical charges move through a
channel region formed between the source and the drain.
[0004] A gate is formed on a semiconductor substrate, and
impurities are doped on the substrate at both sides of the gate to
form a source and a drain. To meet requirements for enhanced data
capacity and integration in a semiconductor memory apparatus, unit
cell size needs to be smaller. It makes the design rule applied for
the capacitor and the transistor decreased. As a result, channel
length becomes shorter, causing a short channel effect and a drain
induced barrier lower (DIBL) effect that hinders normal operation.
For preventing the short channel effect and the DIBL effect, the
doping concentration of the channel region has been increased to
meet a threshold voltage required in the cell transistor. However,
as the design rule becomes less than 100 nm, the highly doped
channel region causes electric field of a storage node (SN)
junction increased, therefore deteriorating a refresh
characteristic of the semiconductor memory apparatus. In order to
prevent the degradation of refresh characteristic, a cell
transistor with a three-dimensional structure is suggested. Such
structure may secure long channel length for the cell transistor
under low design rule. Moreover, if long channel length is secured,
the doping concentration on the channel region can be adjusted to
such a low level that would not degrade refresh characteristic.
Hereinafter, a process for forming a recess-gate transistor with a
three-dimensional structure is described.
[0005] FIGS. 1 to 7 are cross-sectional views illustrating a method
for fabricating a general semiconductor device.
[0006] Referring to FIG. 1, a recess 104 for forming either a
recess gate or a fin gate is formed on a semiconductor substrate
100 where an isolation insulating layer 102 defining an active
region is formed. In this case, since either the recess gate or the
fin gate is arranged in a cell array in the direction extending
across the active region, the recess 104 for forming either the
recess gate or the fin gate is formed in both the active region and
the isolation insulating layer 102.
[0007] Thereafter, as shown in FIG. 2, a gate material is provided
in the recess 104 so that a gate electrode 106 is formed.
[0008] Referring to FIG. 3, a first spacer layer 108, e.g., a
nitride spacer, is deposited on the substrate and on the gate
electrode 106. The first spacer nitride layer 108 is deposited to a
predetermined thickness on the gate electrode 106. An oxide layer
110 is deposited on the first spacer nitride layer 108 so that a
core region and a peripheral region of the semiconductor substrate
100 are covered with the oxide layer 110.
[0009] Referring to FIG. 4, after a photoresist layer (not shown)
is deposited on the oxide layer 110, the photoresist layer formed
on the core region is etched using a cell open mask in order to
expose the core region including the cell array, so that the oxide
layer 110 in the core region is exposed. Thereafter, the oxide
layer 110 covering the core region is removed by a wet etching
process so that a first spacer layer 108 is exposed.
[0010] Referring to FIG. 5, a second spacer layer 112, e.g., a
nitride spacer, is deposited on the exposed first spacer layer 108
in the core region. The second spacer layer 112 is formed to
electrically isolate the gate electrode 106 from other conductive
elements like a bit line contact or a storage node contact, which
will be formed between gate electrodes 106 during post processes.
In order to completely isolate the contact from the gate electrodes
106, the second spacer layer 112 is generally formed with a
thickness of 50.about.150.ANG..
[0011] Referring to FIG. 6, an insulation material having superior
gap-fill properties is deposited on the second spacer layer 112,
and a chemical mechanical polishing (CMP) process is performed
until the second spacer layer 112 is exposed. As a result, an
interlayer insulating layer 114 is formed at a fine space between
the gate electrodes 106.
[0012] Referring to FIG. 7, the interlayer insulating layer 114
formed in a region where a bit line contact or storage node contact
in the core region will be formed is removed by an etch-back
process so that a contact hole 116 is formed. The contact hole 116
is for forming a contact for connecting an active region to either
a capacitor or a bit line which will be formed in a subsequent
step. After the etch-back process is performed, partial portions of
first and second spacer layers 108 and 112 formed at sidewalls of
the gate electrode 106 still remain unetched, but the first and
second spacer layers 108 and 112 formed on the active region and
the isolation insulating layer 102 are completely removed. If the
first and second spacer layers 108 and 112 remain on the active
region, it would hinder the contact formed in the contact hole 116
from being connected to a source/drain region of a transistor.
Thus, the etch-back process should be performed to a sufficient
depth so as to prevent the above-mentioned problem. However, when
an over etch is performed, the substrate in the active region and
the isolation insulating layer 102 are attacked and damaged.
[0013] As the size of the semiconductor device shrinks gradually,
an insulation material with poor gap-fill properties is not
compatible with a high density plasma (HDP) deposition process to
form the isolation insulating layer 102 because it results in voids
within the isolation insulating layer 102. Accordingly, the
isolation insulating layer 102 filling a trench (not shown) is
generally composed of two insulating layers, i.e., one is with
superior gap-fill properties so as to be compatible with a
Spin-On-Dielectric (SOD) deposition process and the other
compatible with a HDP deposition process. However, since most of
insulation material subject to the HDP deposition process do not
have superior gap-fill properties, it is hard to prevent the
aforementioned problem.
[0014] Accordingly, a method of using insulation material that is
compatible with a SOD deposition process without using insulation
material compatible with a HDP deposition process for forming the
isolation insulating layer 102 has been developed. However, pattern
collapse or distortion is occurred because an exposed region is
easily attacked due to an extremely high etch rate of the
insulation material. Further, it forms a layer with irregular
surface, thus causing a defect in a product. In order to overcome
the above-mentioned problems, a method was recently developed for
forming the isolation insulating layer 102 using both an insulation
material compatible with the SOD deposition process and a
Sub-Atmospheric Tetra-Ethyl Ortho Silicate (SATEOS) layer. However,
some process steps for that method are so complicated and the
number of process steps increases, resulting in longer Turn Around
Time (TAT).
[0015] In addition, if the isolation insulating layer 102 is formed
of both the insulation layer compatible with the SOD deposition
process and the SATEOS layer, partial portions of the isolating
layer 102 can be undesirably etched and removed by not only a first
cleaning process performed after the recesses 104 are formed but
also a second cleaning process performed after the interlayer
insulating layer 114 and the first and second spacer layers 108 and
112 are removed. Since the recess 104 formed on the isolation
insulating layer 102 can be formed wider than another recess 104
formed on the active region because of the first cleaning process,
the distance between gate electrodes 106 which is formed on the
isolation insulating layer 102 is reduced, resulting in a reduction
of process margin. Also, due to the second cleaning process, the
isolation insulating layer 102 exposed between gate electrodes 106
formed on the isolation insulating layer 102 is excessively etched
so that the contact can be in electrical short with the gate
electrode 106. Particularly, this electrical short causes a serious
problem threatening operational stability of the semiconductor
device.
[0016] FIG. 8 is a scanning electron microscope (SEM) image
illustrating shortcomings of the semiconductor device manufactured
by the aforementioned processes shown in FIGS. 1 to 7.
[0017] As shown, both a recess gate formed on the isolation
insulating layer and a contact formed between the recess gates are
electrically interconnected, so that the operational stability of
the semiconductor device is deteriorated. Particularly, when a high
voltage (Vpp) higher than a power-supply voltage (VDD) is supplied
to each recess gate used as the word line in a semiconductor memory
device while a logic low signal of a ground voltage (Vss)
corresponding to data "0" are sustained in the contact, data can be
unexpectedly distorted by an electrical connection between the
contact and the recess gate.
BRIEF SUMMARY OF THE INVENTION
[0018] Various embodiments of the present invention are directed to
providing a semiconductor memory device and a method for
fabricating the same. In the semiconductor memory device of the
present invention, when a spacer is formed at sidewalls of the
recess gates in an active region of a high-integration
semiconductor device, an etching prevention layer is formed even on
an inactive region so as to prevent the inactive region from being
excessively etched by a cleaning process, so that electrical
collision or poor connection between the contact and the recess
gate is reduced, resulting in a guarantee of a process margin.
[0019] In an embodiment of the present invention, a method for
manufacturing a semiconductor device comprises forming a first
spacer layer at sidewalls of one or more gate electrodes, forming a
trench by etching an isolation insulating layer exposed between the
gate electrodes, forming a second spacer layer on sidewalls of the
gate electrodes and an inner surface of the trench and forming an
interlayer insulating layer between the gate electrodes.
[0020] The present invention provides a method for manufacturing a
semiconductor memory device, comprising forming a first spacer
layer at sidewalls of one or more gate electrodes, forming a trench
by etching an isolation insulating layer exposed between the gate
electrodes, forming a second spacer layer not only on sidewalls of
the gate electrodes but also on sidewalls and the bottom of the
trench, burying an interlayer insulating layer between the gate
electrodes, forming a contact hole between the gate electrodes, and
forming a contact by burying a conductive material in the contact
hole.
[0021] The present invention provides a semiconductor device,
comprising an isolation insulating layer to define an active region
on a semiconductor substrate, one or more gate electrodes formed on
the active region and the isolation insulating layer, a spacer
layer formed at sidewalls of the gate electrodes, and a contact
formed between the gate electrodes, wherein the contact is formed
on an inner surface of a trench in the isolation insulating layer,
and the inner surface is covered with the spacer layer over.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] FIGS. 1 to 7 are cross-sectional views illustrating a method
for manufacturing a general semiconductor device.
[0023] FIG. 8 is a scanning electron microscope (SEM) image
illustrating shortcomings of the semiconductor device manufactured
by processes shown in FIGS. 1 to 7.
[0024] FIGS. 9 to 15 are cross-sectional views illustrating a
method for manufacturing a semiconductor device according to an
embodiment of the present invention.
DESCRIPTION OF EMBODIMENTS
[0025] Description will now be made in detail in reference to the
embodiment of the present invention and accompanying drawings.
Wherever possible, the same reference numbers will be used
throughout the drawings to refer to the same or like elements.
[0026] FIGS. 9 to 15 are cross-sectional views illustrating a
method for manufacturing a semiconductor device according to an
embodiment of the present invention.
[0027] Referring to FIG. 9, a recess 904 for forming a recess gate
or a fin gate are formed on a semiconductor substrate 900 where an
isolation insulating layer 902 for defining an active region is
formed. The recess 904 for forming the recess gate or the fin gate
is formed in both the active region and the isolation insulating
layer 902.
[0028] Thereafter, as shown in FIG. 10, a gate material is provided
in the recess 904 so that a gate electrode 906 is formed.
[0029] Referring to FIG. 11, a first spacer layer 908, e.g., a
nitride layer, is deposited on the substrate and the gate electrode
906. In this case, the first spacer layer 908 is deposited with a
predetermined thickness on the gate electrode 906 and its
sidewalls. Then, an oxide layer 910 is deposited on the first
spacer layer 908, so that a core region and peripheral regions on
the semiconductor substrate 900 are covered with the oxide layer
910. In order to expose the core region and the cell array region,
after a photoresist layer (not shown) is deposited on the oxide
layer 910, the photoresist layers formed on the core region and the
cell array region are etched using a cell open mask, so that the
oxide layer 910 is exposed. Thereafter, the oxide layers 910
covering the core region and the cell array region are removed by a
wet etching process so that the first spacer layers 908 are
exposed.
[0030] Referring to FIG. 12, a first spacer layer 908 remains at
sidewalls of the gate electrode 906 even after an etch-back
process, whereas the first spacer layer 908 on the top surface of
the gate electrode 906, the semiconductor substrate 900, and an
isolation insulating layer 902 are removed. Although FIG. 12 shows
only the core region and the cell array region in which the oxide
layer is completely removed, peripheral regions (not shown) are
still covered with the oxide layer. Referring to FIG. 12, some
parts of the first spacer layer 908 are not completely etched so
that the first spacer layer 908 is apt to be partially left on the
semiconductor substrate 900 and the isolation insulating layer 902.
Then, the isolation insulating layer 902 exposed between the first
spacer layers 908 is additionally etched to a depth of 500.ANG. or
less using a hydro-fluoric (HF) wet etching process, so that a
trench 911 is formed in the isolation insulating layer 902.
[0031] Thereafter, referring to FIG. 13, a second spacer layer 912,
e.g., a nitride layer, is deposited on the exposed gate electrode
906, the first spacer layer 908, and the trench 911 in the core
region. In this case, a Low Pressure Chemical Vapor Deposition
(LPCVD) nitride layer with a superior step coverage property may be
used as the second spacer layer 912. In the etch-back process for
removing the first spacer layer 908, if the first spacer layer 908
formed on the semiconductor substrate 900 and the isolation
insulating layer 902 is not completely removed, another first
spacer layer 908 formed at sidewalls of the gate electrode 906
formed on the isolation insulating layer 902 and the second spacer
layer 912 are partially protruded, and an upper part of the trench
911 is partially covered with the second spacer layer 912.
[0032] In this case, when a contact (such as a bit line contact or
a storage node contact) formed between gate electrodes 906 is
formed in a post-process, the second spacer layer 912 is formed to
insulate and isolate the gate electrode 906 from either the bit
line contact or the storage node contact, and is formed even in the
trench 911 formed on the isolation insulating layer 902, so that
excessive etching of the isolation insulating layer 902 may be
prevented. In order to completely isolate the contact from the gate
electrode 906, a second spacer layer 912 may be generally formed
with a thickness of 50-150.ANG..
[0033] Referring to FIG. 14, an insulation material having gap-fill
characteristics is deposited on the second spacer layer 912, and is
then planarized by a chemical mechanical polishing (CMP) process or
the like until the second spacer layer 912 is exposed. As a result,
an interlayer insulating layer 914 may be formed not only in a fine
space between gate electrodes but also in the trench 911 formed on
the isolation insulating layer 902.
[0034] Referring to FIG. 15, an interlayer insulating layer 914
which is formed in a region where a bit line contact or storage
node contact contained in the core region is removed by an
etch-back process so that a contact hole 916 is formed. In this
case, the contact hole 916 may be used to form a contact for
connecting a capacitor or bit line which is subsequently formed to
an active region. Through the above-mentioned etch-back process,
first and second spacer layers 908 and 912 formed at sidewalls of
the gate electrode 906 remain un-etched, but the second spacer
layer 912 formed on the active region is completely removed. In
this case, one second spacer layer 912 formed on the active region
is completely removed by controlling the etching depth of the
etch-back process, but another second spacer layer 912 formed in
the trench 911 disposed at a position, which is lower than that of
the one second spacer layer 912 by a depth of 500.ANG., is not
removed. Accordingly, a conductive material is buried in the
contact hole 916, so that the gate electrode 906 and the conductive
material are not electrically short-circuited with each other by
the second spacer layer 912.
[0035] The second spacer layer 912 is formed on the inner surface
of the trench 911 formed on the exposed isolation insulating layer
902, so that it prevents the isolation insulating layer 902 from
being excessively etched in an etching process for forming the
contact hole 916 through a self-aligning etching process.
Consequently, the present invention prevents the gate electrode 906
from being exposed when the contact hole 916 is formed, thereby
preventing the occurrence of poor self-aligned contact (SAC). In
addition, a process margin increases in a fabrication process of
the semiconductor device, and the reliability of elements contained
in the semiconductor device also increases.
[0036] As described above, a method for manufacturing a
semiconductor device according to an embodiment of the present
invention includes forming a first spacer layer at sidewalls of
gate electrodes, forming a trench by etching an isolation
insulating layer exposed between the gate electrodes, forming a
second spacer layer at sidewalls of the gate electrodes and the
trench, and forming an interlayer insulating layer between the gate
electrodes.
[0037] Particularly, the semiconductor device according to the
present invention exposes a core region using a cell open mask,
removes the first spacer layer 908 using an etch-back process, and
etches some parts of the exposed isolation insulating layer 902 to
a depth of 500.ANG. using a wet etching process, thereby forming
the trench 911. In this case, the isolation insulating layer 902
may be formed of an insulation material used for the SOD deposition
process, or may be an SATEOS layer. The present invention is
applicable even when the isolation insulating layer 902 is
configured in the form of a single-layer structure or a
double-layer structure. Thereafter, the second spacer layer 912
having superior gap-fill properties may be formed in the trench 911
formed on the isolation insulating layer 902, and the trench 911
may be covered with parts protruded from sidewalls of the gate
electrode 902. In this case, the semiconductor device of the
present invention may acquire the same effect as in a
double-layered second spacer layer 912 formed on the isolation
insulating layer 902 such that it may prevent the isolation
insulating layer 902 from being etched in the etch-back process for
forming the contact hole 916.
[0038] As apparent from the above description, in a process for
forming contacts after forming recess gates, the semiconductor
device of the present invention prevents the isolation insulating
layer formed in the inactive region from being excessively etched
by a post-process such as cleaning or the like, such that the
recess gate and the contact are not electrically short-circuited.
In addition, the semiconductor device of the present invention
easily prevents the occurrence of the short-circuiting between the
recess gate formed in the inactive region and the contact.
Therefore, the semiconductor device of the present invention need
not simultaneously apply two or more materials (for example, an
insulation material used for the SOD deposition process and an
SATEOS layer) to an insulation layer of the inactive region, so
that it prevents process steps from being complicated and also
prevents a Turn Around Time (TAT) from being deteriorated.
[0039] The above embodiments of the present invention are
illustrative and not limitative. Various alternatives and
equivalents are possible. The invention is not limited by the type
of deposition, etching polishing, and patterning steps described
herein. Nor is the invention limited to any specific type of
semiconductor device. For example, the present invention may be
implemented in a dynamic random access memory (DRAM) device or non
volatile memory device. Other additions, subtractions, or
modifications are obvious in view of the present disclosure and are
intended to fall within the scope of the appended claims.
* * * * *