U.S. patent application number 13/066127 was filed with the patent office on 2011-09-01 for method and apparatus for phostonic stack system for vehicle control/sense.
Invention is credited to Paul Stoner, Wilbur C. Vogley.
Application Number | 20110211845 13/066127 |
Document ID | / |
Family ID | 38957067 |
Filed Date | 2011-09-01 |
United States Patent
Application |
20110211845 |
Kind Code |
A1 |
Vogley; Wilbur C. ; et
al. |
September 1, 2011 |
Method and apparatus for phostonic stack system for vehicle
control/sense
Abstract
An avionics system for a plane includes a plurality of nodes
disposed throughout the plane, each node performing a function. The
system includes an optical network in communication with the nodes
and through which the nodes communicate. The system includes at
least one of the nodes having a hardwired interpreter that
interprets the information transmitted from another one of the
nodes via the optical network. A method for operating a plane
includes the steps of communicating information through an optical
network between a plurality of nodes disposed throughout the plane,
each node performing a function. There is the step of interpreting
with at least one of the nodes having a hardwired interpreter the
information transmitted from another one of the nodes via the
optical network. A phostonic stack.
Inventors: |
Vogley; Wilbur C.;
(Cranberry Township, PA) ; Stoner; Paul; (Powell,
OH) |
Family ID: |
38957067 |
Appl. No.: |
13/066127 |
Filed: |
April 7, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11647828 |
Dec 28, 2006 |
7925166 |
|
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13066127 |
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60831996 |
Jul 19, 2006 |
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Current U.S.
Class: |
398/165 ;
398/140; 700/23 |
Current CPC
Class: |
H04B 10/25891
20200501 |
Class at
Publication: |
398/165 ;
398/140; 700/23 |
International
Class: |
H04B 10/00 20060101
H04B010/00; G05B 15/02 20060101 G05B015/02 |
Claims
1. A phostonic stack interface system to a network comprising: an
FPGA; a floating Faraday cage; a driver for transferring
information to the network; a photo sensor to receive information
from the network; a connector for communication to the network; and
a power source to power the FPGA.
2. A method for operating a vehicle comprising the steps of:
communicating information through an optical network between a
plurality of nodes disposed throughout the vehicle, each node
performing a function; and interpreting with at least one of the
nodes the information transmitted from another one of the nodes via
the optical network.
3. A hardwired interpreter comprising: a local link; local
interface state machine in communication with the local link; a
pseudo-memory block in communication with the local interface state
machine; a main central state machine in communication with memory
block; and a link control in communication with the main control
state machine.
4. A control system for a vehicle comprising: a plurality of nodes
disposed throughout the vehicle, each node performing a function;
an optical network in communication with the nodes and through
which the nodes communicate; and at least one of the nodes having a
hardwired interpreter that interprets the information transmitted
from another one of the nodes via the optical network.
5. A system as described in claim 4 wherein the hardwired
interpreter includes a dedicated circuit within a chip.
6. A system as described in claim 5 wherein the hardwired
interpreter has no software.
7. A system as described in claim 6 wherein the hardwired
interpreter includes a local link to another one of the nodes
associated with the hardwired interpreter.
8. A system as described in claim 7 wherein the hardwired
interpreter includes a link control in communication with the other
nodes of the plurality of nodes.
9. A system as described in claim 8 wherein at least one of the
other nodes is a sensor.
10. A system as described in claim 9 wherein the vehicle is either
a car, truck, bus, plane, train or boat and may be manned or
unmanned.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This is a divisional of U.S. patent application Ser. No.
11/647,828 filed Dec. 28, 2006, which claims priority from U.S.
provisional patent application Ser. No. 60/831,996 filed Jul. 19,
2006.
FIELD OF THE INVENTION
[0002] The present invention is related to the operation of a
vehicle having an optical network through which nodes that perform
a function communicate. More specifically, the present invention is
related to the operation of a vehicle having an optical network
through which nodes that perform a function communicate where at
least one of the nodes is a hardwired interpreter.
BACKGROUND OF THE INVENTION
[0003] Currently, the sensors and control of vehicles are
mechanical links or electrical wires. They may also be systems with
microprocessors and software to determine sensor input, relate the
input, interpret the sensors for mean, min, and max for those
sensors in order to give readings and warnings. It uses the same
technology to issue commands and control to the vehicle. Some of
these electrical links are analog information and yet other links
are defined bus or interface architectures. Many times, one must go
through several adapters to connect the correct information.
BRIEF SUMMARY OF THE INVENTION
[0004] The present invention pertains to an avionics system for a
plane. The system comprises a plurality of nodes disposed
throughout the plane, each node performing a function. The system
comprises an optical network in communication with the nodes and
through which the nodes communicate. The system comprises at least
one of the nodes having a hardwired interpreter that interprets the
information transmitted from another one of the nodes via the
optical network.
[0005] The present invention pertains to a method for operating a
plane. The method comprises the steps of communicating information
through an optical network between a plurality of nodes disposed
throughout the plane, each node performing a function. There is the
step of interpreting with at least one of the nodes having a
hardwired interpreter the information transmitted from another one
of the nodes via the optical network.
[0006] The present invention pertains to a phostonic stack
interface system to a network. The stack comprises an FPGA. The
stack comprises a Faraday cage, a driver for transferring
information to the network, a photo sensor to receive information
from the network, a connector for communication to the network, and
a power source to power the FPGA.
[0007] The present invention replaces current technology with a
unique system that communicates through the entire vehicle's field
replaceable units (FRUs). This is done through unique chip-to-chip
optical links. This lightens the equipment by eliminating devices
and boxes as well as increase security and removes vulnerability
through photonics versus electrical interfaces. The information is
replicated in a unique method of memory address links that are in
update mode at all times.
[0008] Current technology uses an electrical interface or
mechanical link to relay information about the vehicle as well as
control the vehicle. The current technology may include a
microprocessor, mechanical, and/or electrical linked system. Most
vehicles have a CPU that controls fuel mixtures, and monitors
conditions to determine correct engine operation as well as provide
warning information.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0009] In the accompanying drawings, the preferred embodiment of
the invention and preferred methods of practicing the invention are
illustrated in which:
[0010] FIG. 1 shows various vehicles which utilize the system of
the present invention.
[0011] FIG. 2a shows a system of the present invention utilized
with a drive control and accelerator.
[0012] FIG. 2b shows the system of the present invention utilized
with a control wheel and throttle.
[0013] FIG. 3 is a block diagram of a hardwired interpreter of the
present invention.
[0014] FIG. 4a shows a portion of the system of the present
invention utilized with a brake pedal.
[0015] FIG. 4b shows a portion of the system of the present
invention utilized with a yoke.
[0016] FIG. 5a shows a portion of the system of the present
invention utilized with a brake actuator.
[0017] FIG. 5b shows a portion of the system of the present
invention utilized with an elevator actuator.
[0018] FIG. 6 is a block diagram of the hardwired interpreter for a
brake.
[0019] FIG. 7 shows an optical position sensor.
[0020] FIG. 8 shows a Faraday cage.
DETAILED DESCRIPTION OF THE INVENTION
[0021] Referring now to the drawings wherein like reference
numerals refer to similar or identical parts throughout the several
views, and more specifically to FIG. 1 thereof, there is shown a
control system 50 for a vehicle 16. The system 50 comprises a
plurality of nodes 52 disposed throughout the vehicle 16, each node
performing a function. The system 50 comprises an optical network
54 in communication with the nodes 52 and through which the nodes
52 communicate. The system 50 comprises at least one of the nodes
52 having a hardwired interpreter 56 that interprets the
information transmitted from another one of the nodes 52 via the
optical network 54.
[0022] Preferably, the hardwired interpreter 56 includes a
dedicated circuit within a chip. The hardwired interpreter 56
preferably has no software. Preferably, the interpreter has no
software. The interpreter preferably includes a local link to
another one of the nodes associated with the hardwired interpreter.
The hardwired interpreter preferably includes a link control in
communication with the other nodes of the plurality of nodes.
Preferably, at least one of the other nodes is a sensor. The
vehicle is either a car, truck, bus, plane, train or boat and may
be manned or unmanned.
[0023] The present invention pertains to a method for operating a
vehicle 16. The method comprises the steps of communicating
information through an optical network 54 between a plurality of
nodes 52 disposed throughout the vehicle 16, each node performing a
function. There is the step of interpreting with at least one of
the nodes 52 having a hardwired interpreter 56 the information
transmitted from another one of the nodes 52 via the optical
network 54.
[0024] The present invention pertains to a phostonic stack 58
interface system 50 to a network 54. The stack 58 comprises an FPGA
74. The stack 58 comprises a Faraday cage 76, a driver 78 for
transferring information to the network 54, a photo sensor to
receive information from the network 54, a connector for
communication to the network, and a power source 80 to power the
FPGA 74.
[0025] In the past, control systems, such as in aircraft, were
cables, hydraulics, and analog gauges to sensors for things like
oil pressure, engine RPM, altitude, etc. As electronic circuits
developed, the electronics moved into the aircraft a little at a
time with radios, electric tachometers, and now fly-by-wire.
Computers control nearly all information transferred within an
aircraft. New challenges have come forward, such as lightning and
aggressive disruptive electronic noise generation.
[0026] This invention replaces the existing cables with a plastic
optical fiber that connects all the systems in a vehicle 16, such
as an aircraft. In the process of developing the optical links, the
processor has been eliminated and its latency by implementing
hardwired state machines to do all of the control and monitor task
done by processors previously.
[0027] The innovation of the phostonic stack 58 vehicle 16 control
system 50 is: [0028] 1) Eliminating the control harness. [0029] 2)
Eliminating complex control interface. [0030] 3) Eliminate multiple
adapters between standards. [0031] 4) Adding speed and reliability.
[0032] 5) Linking sensors, control, and feedback with predetermined
allocated space. [0033] 6) Introducing the single device "floating"
Faraday cage 76 for integrity. [0034] 7) Eliminating mechanical
linkages in many instances. [0035] 8) Reduction in overall
maintenance cost.
[0036] This system 50 is based on taking the control interface and
reducing the possible commands to a series of memory locations that
are simultaneously updated at .about.1000 times a second throughout
the vehicle 16. The updates can be targeted to those units with a
need to know, or update all of the units on the link.
[0037] See FIG. 1. It demonstrates the link between hardware,
controls, and sensors 64. FIGS. 2a and 2b show the links are
coherent. FIG. 3 demonstrates a typical device layout using a
Xilinx FPGA 74 that can be made into an ASIC.
[0038] In FIG. 2a, the sensors 64 for the drive control and the
accelerator alter the memory at the sending end, the information is
sent to the other SCs on the link, and the units at those locations
look at the memory address assigned to them and receive the
updates.
[0039] In FIG. 2b, the sensors 64 for the drive control and the
accelerator alter the memory at the sending end, the information is
sent to the other SCs on the link, and the units at those locations
look at the memory address assigned to them and receive the
updates.
[0040] FIG. 3 is a representation of the Software-Less System with
a visual sensation of the allocation on the device for its various
components. This is merely a pictorial and may have no relationship
to actual locations.
[0041] Using the FPGA 74/ASIC in FIG. 3 eliminates the need for an
operating system and microprocessor. The functions of the
microprocessor are replicated in the ASIC VIA hardwired logic to
perform the necessary functions. All of the necessary information
can be incorporated on a single device, including both the local
and link interface.
[0042] In FIG. 3, the local link 60 referred to at the top of the
block is the Mimic Memory interface to whatever device actually
being talked with as opposed to the link control 62 which is the
interface used to get data between this device and the other
equipment on the vehicle 16. An example of this interface is
FireWire, IP, AFDX, etc. Any of these interface protocols can be
used. Data is then sent on an internal bus to location either set
in the device by default or by a state machine direction. Many of
the current systems know where they are by the plug at the
location. The optical system 50 here can be operated in a similar
fashion. The location can be either code by a mechanical indicator
such as a plug extension location on the surface provided of the
"box" or by an optical sensor 64 on the device that reads a code
for the location, or identifies an extrusion and its position to
the connector.
[0043] The hardwired phostonic stack 58 system 50 is much faster as
there is no instruction load time and no lookup time involved in
its operation.
[0044] Once a command is given with a microprocessor, if it is not
in the subroutines for the request, it must acquire the program or
subroutine, execute it, and then issue the commands. This can take
many, many clock cycles. With hardwired logic, it can only take as
long as the longest state sequence in this phostonic stack 58
solution.
[0045] Control has more information to cover urgency and priority
of the request and its interpretation. These can all be managed by
the phostonic stack 58 solution, and updated through the IOI
optical links.
[0046] The local link 60 referred to at the top of the block is the
Mimic Memory interface to the unit at this location. This "link" is
defined by the unit and may be from 1 to 128 bits wide. The link
will be designed for the unit or be logically assigned by the local
interface state machine.
[0047] If it is designed for a specific unit, the information
received from the unit will be directly mapped to a local memory
location. The information to the unit will be sent directly from a
memory location defined by the specific detail for the unit
attached.
[0048] If the unit is a logic assignment, the local interface state
machine is implemented. It can determine the unit by a code
submitted from the unit at power up, a keyed local bus plug, an
enquiry from the state machine, an assignment from another node,
etc. It will then assign a memory location to link to for both to
and from the unit.
[0049] This information to and from the memory locations reside in
the Pseudo-Memory Block. It is named pseudo-memory block as it may
be memory, or temporary logic storage.
[0050] The main control state-machines have the function to do the
operations that were preformed by the obsolete software and
processors of the older systems. They take the information off the
link control 62 and put it in the correct local pseudo memory
locations as well as take information from the local memory and
give it to the link control 62 for forwarding to the correct node.
The main control is much faster than a processor for two reasons,
1) there are no software cycles involved, and 2) there is virtually
no limit on the number of process being acted on in a true parallel
fashion.
[0051] The link control 62 sends and receives information off the
node links. The node links are links between nodes 52, and at this
time are current standards such as Ethernet/FireWire/10G-E/AFDX.
While these are current, it does not exclude future links, some of
which may be proprietary. The linked system 50 has its own buffer
and repeater system to transfer current input to the output for
doing its own add/drop function as well as handling priority
injection for emergencies.
[0052] Many of the current systems know where they are by the plug
at the location. The present invention can be operated in a similar
fashion. The location can be either code by a mechanical indicator
such as a plug extension location on the surface provided of the
"box" or by an optical sensor 64 on the device that reads a code
for the location, or identifies an extrusion and it position to the
connector. If it is to be routed by a state-machine, it will get
the location from the incoming data stream by doing a compare to
see which locations in the "memory" the information should reside.
This would be the case for nodes 52 serving more than one local
entity.
[0053] Operation:
[0054] The operation will be similar for all sensors and commands
even though the sensors will vary in type and style. The system 50
will accommodate legacy equipment and sensors as well as drive
legacy motors and actuators. This includes, but not limited to,
Engine Control, Engine Monitors, Fuel Level, Fuel Tank Switching,
Brake Control, Dash Lighting, Lights, Radio Links, Onboard
Audio/Video Systems, and GPS, just to name a few.
[0055] As an example, a command from the brake pedal 66 to the
brakes will be followed.
[0056] In FIG. 4a, the brake pedal 66 may be pushed to engage
brakes. The sensor 64 determines where the brake pedal 66 is
located by the optical sensors. It is given to the phostonic stack
58 module in terms of 100s or 1000ths of increment movement. It is
monitored similar to the measurements taken in a micrometer or
vernier caliper, with the exception in this example, it is measured
by optical refraction on the extension of the brake pedal 66
shaft.
[0057] When the shaft is moved, the digital number is sent to the
phostonic stack 58 module. The phostonic stack 58 module is aware
of the sending device by the location of the connection on the bus
and the type of sensor/device. One method of defining the type of
sensor/device is to ground/short a combination of pins for the
location. For example, pin 1 and 5 of the 6 pin ID block that is
the first 6 pins of the connector. Pins 12, 13, 14, 15, 16 could be
input to the phostonic stack 58 module from the brake pedal 66
sensor at the brake pedal 66.
[0058] The state machine in the SC is set to modify the locations
in memory by the ID block and locations of the data pins coming in.
It will modify the locations at 7000 through 7FFF.
[0059] The state machine in the Link Drive loop is directed to put
the data from location 7000 to 7FFF on the link line to all the
modules on the link.
[0060] The module in FIG. 5 has loaded the data in its addresses
7000 to 7FFF. The local bus state machine's memory loaded bit is
set and it reads the memory location and sends the data to the
actuator as well as verifies the feedback of the physical location
of the brake actuator.
[0061] The brake pistons 68 are moved appropriately. They in turn
send a feedback signal to the back pressure unit on the brake pedal
66 arm, thus giving the impression the pedal is actually pushing a
mechanical linked brake pedal 66. This is accomplished through a
small cylinder with hydraulic fluid and a tiny control valve
between chambers.
[0062] One method of the sensor 64 in FIG. 4a is to use a hole or
reflectors in the shaft of the break pedal with optical drive and
pickup for the sensor 64 operation. The holes or reflectors are
located in such a fashion as shown in FIG. 7. There is a total
count of 128 positions in this example. The presentation
demonstrates triple redundancy for safety in commercial
vehicles.
[0063] As the reflector/hole plate travels horizontally, the
light/sensor post determines how many of the 6 vertical positions
"see" light and relates that information to the correct memory
locations.
[0064] The information is saved here in FIG. 5a from the sensors 64
in FIG. 4a to locations in the area for brake pressure/position.
This is done through storing the information in the proper location
in this section as specified in the manual for this vehicle 16. As
this becomes practice, there may be an ideal location and increment
for all vehicles. Location feedback may be handled by the same
method as the brake sensor 64.
[0065] In another example, a command from the yoke 70 to the
elevator 72 in a plane is followed.
[0066] In FIG. 4b, the yoke 70 may be moved to the right or left to
change the elevator 72. The sensor 64 determines where the yoke 70
is located by the optical sensors. It is given to the phostonic
stack 58 module in terms of 100s or 1000ths of increment movement.
It is monitored similar to the measurements taken in a micrometer
or vernier caliper, with the exception in this example, it is
measured by optical refraction on the extension of the yoke 70
shaft.
[0067] When the shaft is moved, the digital number is sent to the
phostonic stack 58 module. The phostonic stack 58 module is aware
of the sending device by the location of the connection on the bus
and the type of sensor/device. The type of sensor/device is
grounded pin 1 and 5 of the 6 pin ID block that is the first 6 pins
of the connector. Pins 12, 13, 14, 15, 16, and 17 are the input to
the phostonic stack 58 module from the elevator 72 sensor 64 at the
yoke 70.
[0068] The state machine in the SC is set to modify the locations
in memory by the ID block and locations of the data pins coming in.
It will modify the locations at 7000 through 7FFF.
[0069] The state machine in the Link Drive loop is directed to put
the data from location 7000 to 7FFF on the link line to all the
modules on the link.
[0070] One method of the sensor 64 in FIG. 4b is to use a hole or
reflectors in the shaft of the break pedal with optical drive and
pickup for the sensor 64 operation. The holes or reflectors are
located in such a fashion as shown in FIG. 7. There is a total
count of 128 positions in this example. The presentation
demonstrates triple redundancy for safety in commercial
vehicles.
[0071] As the reflector/hole plate travels horizontally, the
light/sensor post determines how many of the 6 vertical positions
"see" light and relates that information to the correct memory
locations.
[0072] The module in FIG. 5a has loaded the data in its addresses
7000 to 7FFF. The local bus state machine's memory loaded bit is
set and it reads the memory location and sends the data to the
actuator as well as verify the feedback of the physical location of
the elevator 72 actuator.
[0073] The elevator 72 is moved appropriately.
[0074] The information is saved here in FIG. 5b from the sensors 64
in FIG. 4b to locations in the area for brake pressure/position.
This is done through storing the information in the proper location
in this section as specified in the manual for this vehicle 16. As
this becomes practice, there may be an ideal location and increment
for all vehicles. Location feedback may be handled by the same
method as the brake sensor 64.
[0075] In another example, take the action of a turn signal:
[0076] For this example, assign the memory locations of 7000 to
7000F for the right turn signal and 70F0 for the left turn signal.
This allows for a 16 bit word to command the turn signal. Depending
on the desired command, it could be from "ON" to "ON with a timer",
etc. At this point, assume only turn on and turn off. Indicating a
right turn through deflecting the turn signal lever or even a
finger gesture for a right hand turn will change the local module
that it is time to turn on the right turn signal. The actual signal
from the actuator will set a local bit at 7001 to "ON". The device
senses this "memory change, reads the control device memory
locations to the interface, and transfers 16 bits to the other
memory devices on the network 54. The only receivers that will use
these locations will be the turn indicators in each of the four
corners of the car. These memory locations will sort the new
information and look at those locations to determine what to do.
The front and rear external indicators will implement "ON" function
as well as change the memory location at 7010 to a "1" to indicate
the signal is on. If the signal cannot come on due to a failure of
some type, it will send an additional bit (7011) to indicate it had
received the command, but there is trouble and rapidly flash the
signal location at the instrument panel as well as record the
information to the system memory for read out at a garage.
[0077] The Phostonic Stack 58 interface system 50 comprises at
least one PLD or FPGA 74, a grounded or floating Faraday cage 76,
at least one laser driver 78 and at least one photo sensor (PIN), a
connector(s), and at least one photocell sheet. The PLD or FPGA 74
contains the logic and state-machines to do the determinations, for
sending and receiving information to both the network 54 and to the
local unit. The Faraday cage 76 prevents erroneous electrical noise
from entering or leaving the internal circuits. The laser driver(s)
78 transfer information form the local unit to the network 54, and
possibly to the local unit as well. The photo sensor(s) receive
information generated by another node on the network 54 and passed
to this node via the network 54 and generate an electrical pulse to
be handled by the PLD or FPGA 74. The connector(s) contain the
optical link to and from the network 54, as well as to and from the
unit which can also be optical. The photocell sheet contains a
number of photocells to supply the PLD/FPGA 74 and lasers with
enough power to function with a surplus to charge a storage device
such as a super cap that is designed to handle any interment
shortcomings of the power source 80. The number of photocells tied
in series is defined by the voltage needed by the devices; the
number of series blocks in parallel is determined by the amount of
power required by the devices at this location.
[0078] There may be redundant FPGAs 74 as dictated by the governing
agency such as the DOT for land vehicles, Coast Guard for seaworthy
craft, or FAA for aircraft. The one encompassed here is a full
duplex switched Ethernet, a MAC, and an I/O system to handle a
local parallel memory address capability. The Ethernet link will be
through the laser and PIN. The photocell sheet will be powered by
the light from a power source 80 or the white light power system as
described in U.S. patent application Ser. No. ______, having
attorney docket number VOGLEY-2 and contemporaneously filed with
this application. The photocell sheet is attached to the bottom of
the FPGA 74 forming connections to the + and - of the FPGA 74.
Since each photocell produces approximately 0.5 volts, the cells
will be linked in series to produce 1.5 volts for the circuits in
the FPGA 74.
[0079] The floating Faraday cage 76 will completely encompass the
FPGA 74, photocell sheet, and the I/O for external drive.
[0080] Xilinx, Altera, and Actel are manufacturers of FPGAs, with
Actel leading in radiation-hardened products. The triple redundancy
allows for integrity by continually checking all three paths for
matching information. If there is a difference, the two that match
are considered having the correct information and operation
continues (this is called a voting system). Once each FPGA 74 is
certified, the circuit can be hardwired in an ASIC providing
further integrity.
[0081] The system 50 is based on an FPGA 74 (Field Programmable
Gate Array) that can be made into an ASIC (Application Specific
Integrated Circuit) by the manufacturer. Once it is an ASIC, it can
no longer be updated, hence the term "Hardwired". During the
initial phases, the FPGA 74 is coded to respond to preferred
protocol such as FireWire or IP. It is through this protocol that
the FPGA 74 will communicate with its peers.
[0082] Each FPGA 74 will have hardwired state-machines that do the
work of a processor. The state-machine operates on a series of
operations at clock speed. A state-machine can do a function,
branch to another state-machine, etc. For example: [0083] 1. State
Machine Brake Control [0084] 2. Check brake feedback for
entry--update console [0085] 3. Update counter [0086] 4. Check
brake command entry--issue send update [0087] 5. Loop back to 1
[0088] All commands are similar to this scenario and step through
the states as commanded. When a change in the memory area is logged
in the check requester, the state-machines can detect by a single
bit check if its area has been changed and request the update to be
posted while resetting the register bit. This state-machine
completes its cycle 7 million times a second. Should it go a second
without updating, an update will be forced. The second timeout is
conditioned by the update counter overflow.
[0089] Also called "finite state machine," it is a computing device
designed with the operational states required to solve a specific
problem. The circuits are minimized, specialized and optimized for
the application. For example, chips in audio, video and imaging
controllers are often designed as state machines, because they can
provide faster performance at lower cost than a general-purpose
CPU. Automatic ticket dispensing machines are another example.
There are countless special-purpose devices built as state
machines.
[0090] In order to conserve memory space, the device can be keyed
by its location to use only the memory locations allocated for this
location and can be modified by an offset in the addressing
register. For example, in FIG. 6, this location is actually
starting at 1000, not 7000. But the system 50 thinks it is at 7000
because that is where the brake sensor 64 and control are located.
The Loc key subtracts 6000 and therefore starts the real location
at 1000.
[0091] This is only necessary if after all state-machines are
allocated, there is not enough memory left to cover the need for
all locations. The Loc key is needed to identify which
state-machines to use as well as define the memory allocations.
[0092] The local interface mimics SRAM memory in that it has an
address bus and a data path to read in and read out of memory. This
is described in detail within the Memory Mimic application. The I/O
to the local entity is as a memory device. All sensors 64 send
information to the memory device, and the entity reads from the
memory device to acquire instructions or commands. This information
then gets shared with its peers that record the information for
their local interface to use.
[0093] All references to the link for this document have been
centered on the IP or FireWire as they are the current standard
interfaces for higher speed interconnects. The protocol does not
matter, this interface link could be any other protocol preferred
by any vehicle manufacture.
[0094] FIG. 8 shows the inside of the Redundant(O) Box. It is not
susceptible to lightning and EMI due to non-electrical connections
between inside and outside the box.
[0095] Although the invention has been described in detail in the
foregoing embodiments for the purpose of illustration, it is to be
understood that such detail is solely for that purpose and that
variations can be made therein by those skilled in the art without
departing from the spirit and scope of the invention except as it
may be described by the following claims.
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