U.S. patent application number 13/104501 was filed with the patent office on 2011-09-01 for semiconductor storage device.
This patent application is currently assigned to PANASONIC CORPORATION. Invention is credited to Hidenari Kanehara, Tsuyoshi KOIKE.
Application Number | 20110211408 13/104501 |
Document ID | / |
Family ID | 40431676 |
Filed Date | 2011-09-01 |
United States Patent
Application |
20110211408 |
Kind Code |
A1 |
KOIKE; Tsuyoshi ; et
al. |
September 1, 2011 |
SEMICONDUCTOR STORAGE DEVICE
Abstract
A voltage of a bit line connected to a memory cell is stepped up
to a power supply voltage by a precharge circuit. Before data is
read from the memory cell, the voltage of the bit line is stepped
down to a voltage level lower than the power supply voltage by a
step-down circuit. A precharge switching element controls a
connection between a high-potential-side power supply and the
precharge circuit and a connection between a low-potential-side
power supply and the precharge circuit. A power supply connecting
circuit is provided between the precharge switching element and the
high-potential-side power supply. A ground connecting circuit is
provided between a connecting point at which the precharge
switching element is connected to the power supply connecting
circuit and the low-potential-side power supply.
Inventors: |
KOIKE; Tsuyoshi; (Kyoto,
JP) ; Kanehara; Hidenari; (Kyoto, JP) |
Assignee: |
PANASONIC CORPORATION
Osaka
JP
|
Family ID: |
40431676 |
Appl. No.: |
13/104501 |
Filed: |
May 10, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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12201384 |
Aug 29, 2008 |
7965569 |
|
|
13104501 |
|
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Current U.S.
Class: |
365/203 |
Current CPC
Class: |
G11C 11/413 20130101;
G11C 7/12 20130101 |
Class at
Publication: |
365/203 |
International
Class: |
G11C 7/12 20060101
G11C007/12 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 6, 2007 |
JP |
2007-231208 |
Claims
1-4. (canceled)
5. A semiconductor storage device comprising: a memory cell, a
first bit line connected to the memory cell, a precharge circuit
for stepping up a voltage of the first bit line, and a power supply
connecting circuit for supplying a high-potential-side power to the
precharge circuit, a ground connecting circuit for supplying a
low-potential-side power to the precharge circuit, wherein the pre
charge circuit steps up a voltage of the bit line by supplying the
high-potential-side power to the first bit line, the precharge
circuit steps down a voltage of the bit line by supplying the
low-potential-side power to the first bit line, and the precharge
circuit comprises a first PMOS transistor of which source is
supplied one of the high-potential-side power from the power supply
connecting circuit and the low-potential-side power from the ground
connecting circuit, and of which drain supplies one of the
high-potential-side power and the low-potential-side power to the
first bit line.
6. The semiconductor storage device as claimed in claim 5, further
comprises: a second bit line connected to the memory cell, wherein
the pre charge circuit further comprises a second PMOS transistor
of which source is supplied one of the high-potential-side power
from the power supply connecting circuit and the low-potential-side
power from the ground connecting circuit, and of which drain
supplies one of the high-potential-side power and the
low-potential-aide power to the second bit line.
7. The semiconductor storage device as claimed in claim 6, wherein
the memory cell is an SRAM.
8. The semiconductor storage device as claimed in claim 6, wherein
the power supply connecting circuit comprises a third transistor of
which source is supplied the high-potential-side power from a high
potential-side power supply and drain supplies the
high-potential-side power to the precharge circuit, and the ground
connecting circuit comprises a fourth transistor of which source is
supplied the low-potential-side power from a low-potential-side
power supply and drain supplies the low-potential-side power to the
precharge circuit.
9. The semiconductor storage device as claimed in claim 6, further
comprises: an equalizing circuit for equalizing a voltage of the
first bit line and a voltage of the second bit line.
10. The semiconductor storage device as claimed in claim 9, wherein
the equalizing circuit comprises a fifth transistor of which source
and drain are connected to the first bit line and the second bit
line respectively, and gates of the first transistor, the second
transistor, and fifth transistor are controlled by a common control
signal.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor storage
device comprising a memory cell, a bit line connected to the memory
cell, a precharge circuit which steps up a voltage of the bit line
up to a power supply voltage, and a step-down circuit which steps
down the voltage of the bit line to a voltage level lower than the
power supply voltage before data is read from the memory cell.
[0003] 2. Description of the Related Art
[0004] In the field of a semiconductor storage device, there is a
conventional technology for improving a data reading speed by
stepping down a bit line precharged with a power supply voltage to
a voltage level lower than the power supply voltage before data is
read so that the power supply voltage level in the bit line can
change to a ground level sooner. The change from the power supply
voltage level to the ground level in the bit line is detected by a
PMO transistor at a subsequent gate. However, when a step-down
level in the bit line is below an operation region of a transistor
for detection, through current and a data-read error may occur. A
similar data-read error also occur in the case where a sense
amplifier or a PMOS cross driver is connected to the bit line.
Therefore, it is necessary to keep a step-down level of the bit
line around a threshold voltage of the PMOS transistor.
[0005] In a SRAM circuit where the bit line is precharged with the
power supply voltage, charges of the power supply voltage level of
the bit line flow into a node at which "L" data of SRAM is retained
as soon as a word line is activated, in a non-selected column in
which reading or writing is being performed. The inflow of too many
charges at the time results in the generation of a data-write
error. An indicator called a static noise margin shows a level of
resistance against the data-write error. The static noise margin
has been reduced in recent years as the semiconductor is
increasingly miniaturized, and the data-write error is more likely
to occur. In order to respond to the recent trend, there is a
technology wherein a potential of the power supply voltage level of
the bit line is stepped down so as to reduce the current flow into
the node of the memory cell at which "L" data is stored when the
word line is activated. When the voltage step-down level in the bit
line at that time is not enough, the data-write error occurs due to
the reason described above. When the voltage step-down level in the
bit line is excessive, an data-write error is caused by charges of
"L" level of the bit line which flow into the node at which "H"
data of the SRAM is retained. Therefore, it is necessary to step
down the voltage of the bit line to such a voltage level that can
assure the static noise margin.
[0006] Below is described a technology for stepping down the
voltage of the bit line in a conventional semiconductor storage
device referring to FIGS. 7A and 7B. FIG. 7A is a circuit diagram
illustrating a constitution of a conventional semiconductor storage
device, and FIG. 7B is a timing chart illustrating an operation of
the semiconductor storage device. In FIG. 7A, 11 denotes a SRAM
memory cell, 12 denotes a precharge circuit, 13 denotes an
equalizing circuit, 14 denotes a reading circuit, 15 denotes a
step-down circuit, BL and /BL are complementary bit lines, WL
denotes a word line, PC denotes a precharge control signal, DEC
denotes a step-down/equalizing control signal, QP31, QP32 and QP33
denote PMOS transistors constituting the precharge circuit 12, QP34
denotes a PMOS transistor constituting the equalizing circuit 13,
QN31 and QN32 denote NMOS transistors constituting the step-down
circuit 15, and Inv0 denotes an inverter.
[0007] The step-down circuit 15 comprising the step-down
transistors QN31 and QN32 is additionally provided in order to
step-down voltages of the bit lines BL and /BL prior to the
activation of the word line WL. Sources of the step-down
transistors QN31 and QN32 are connected to the ground, drains
thereof are directly connected to the bit lines BL and /BL, and
gates thereof are connected to a gate of the equalizing transistor
QP34 via the inverter Inv0. The gates of the step-down transistors
QN31 and QN32 are driven by the step-down/equalizing control signal
DEC.
[0008] As shown in FIG. 7B, prior to the activation of the word
line WL, the precharge control signal PC is negated and turns to
"H" level at a timing t31, the precharge transistors QP31 and QP32
and the equalizing transistor QP33 are turned off, which leaves the
bit lines BL and /BL in a floating state.
[0009] At a timing t32, the step-down/equalizing control signal DEC
is asserted and turns to "H" level, and the step-down transistors
QN31 and QN32 in the step-down circuit 15 are turned on. Further,
the equalizing transistor QP34 in the equalizing circuit 13 is
turned on, charges of the bit line BL and /BL are then discharged,
and potentials of the bit lines BL and /BL are stepped down to a
predetermined voltage level. A possible example of the
predetermined voltage level is VDD-Vth. VDD is a power supply
voltage used for the precharge, and Vth is a threshold voltage of
the MOS transistors.
[0010] When the step-down/equalizing control signal DEC is negated
and turns to "L" level at a timing t33, the step-down transistors
QN31 and QN32 are turned off, and the equalizing transistor QP34 is
turned off. As a result, the step-down and equalizing operations
for the bit lines BL and /BL are halted.
[0011] At a timing t34, the word line WL is asserted, and data is
read from the memory cell 11. In the case where "0" is stored in
the memory cell 11, current flows from the bit line BL into the
memory cell 11, and the potential of the bit line BL is lowered;
however, the potential of the complementary bit line /BL is not
stepped down. The state in which the bit line BL="L" level and the
complementary bit line /BL="H" level is judged by the reading
circuit 14 as "0" data. In the case where "1" is stored in the
memory cell 11, the current flows from the complementary bit line
/BL into the memory cell 11, and the potential of the complementary
bit line /BL is lowered, however, the potential of the bit line BL
is not stepped down. The bit line BL="H" level and the
complementary bit line /BL="L" level is judged by the reading
circuit 14 as "1" data. Broken lines denoting the potentials of the
bit lines BL and /BL illustrate the potential reduction
irrespective of whether the reduction occurs in the bit line BL or
the complementary bit line /BL.
[0012] At a timing t35, the word line WL is at "L" level, and the
data reading operation is terminated. At a timing t36, the
precharge control signal PC is asserted and turns to "L" level, and
the precharge transistors QP31 and QP32 and the equalizing
transistor QP33 are turned on. Then, the bit lines BL and /BL are
precharged with the power supply voltage.
[0013] In the foregoing description, the step-down levels of the
bit lines BL and /BL are adjusted in accordance with a pulse width
of the step-down/equalizing control signal DEC. Provided that the
step-down level is .DELTA.V, and the pulse width of the
step-down/equalizing control signal DEC is Tw, .DELTA.V.varies.Tw,
which means that the step-down level .DELTA.V is substantially in
proportion with the pulse width Tw of the step-down/equalizing
control signal DEC.
[0014] In the conventional technology, since the step-down
transistors QN31 and QN32 of the step-down circuit 15 are directly
connected to the bit lines BL and /BL, load capacities of the bit
lines BL and /BL are increased, which results in the deterioration
of a reading time in a data cycle of reading data from the memory
cell.
[0015] Further, a timing of the termination of the step-down
control is likely to vary when the load capacities of the bit lines
BL and /BL are increased. As a result, the step-down levels of the
bit lines BL and /BL also vary, which may result in a data-read
error.
SUMMARY OF THE INVENTION
[0016] Therefore, a main object of the present invention is to
provide a semiconductor storage device capable of reliably
preventing the deterioration of a reading speed at the time when
data is read from a memory cell by providing a bit line with a
step-down circuit without any increase of a load capacity of the
bit line, and capable of unfailingly preventing a data-read error
by executing a stable step-down control.
[0017] In order to solve the foregoing problems, a semiconductor
storage device according to the present invention comprises [0018]
a memory cell; [0019] a bit line connected to the memory cell;
[0020] a precharge circuit for stepping up a voltage of the bit
line to a power supply voltage; [0021] a step-down circuit for
stepping down the voltage of the bit line to a voltage level lower
than the power supply voltage before data is read from the memory
cell; [0022] a high-potential-side power supply and a
low-potential-side power supply respectively connected to the
precharge circuit; and [0023] a precharge switching element for
controlling a connection between the high-potential-side power
supply and the precharge circuit and a connection between the
low-potential-side power supply and the precharge circuit, wherein
[0024] a power supply connecting circuit is provided between the
precharge switching element and the high-potential-side power
supply, and [0025] a ground connecting circuit is provided between
a connecting point at which the precharge switching element is
connected to the power supply connecting circuit and the
low-potential-side power supply.
[0026] The present invention exerts the following effect. When the
precharge circuit is in assert state, the step-down circuit is in
negate state. When the step-down circuit is in assert state, the
precharge circuit is in negate state. Thus, the precharge circuit
and the step-down circuit are in the trade-off relationship in
their operation states. In the present invention wherein the
relationship is utilized, the precharge circuit is interposed
between the step-down circuit and the bit line when the step-down
circuit is connected to the bit line. More specifically, the
precharge switching element which is turned on at the time of the
precharge is provided in the precharge circuit, and one end of the
precharge switching element is connected to the bit line, while the
other end thereof is connected to the high-potential-side power
supply. Then, the power supply connecting circuit is interposed
between the precharge switching element and the high-potential-side
power supply so that the precharge switching element and the
high-potential-side power supply are not constantly connected to
each other. Further, the connecting point at which the precharge
switching element and the power supply connecting circuit are
connected to each other is used as a control node, and the ground
connecting circuit is interposed between the control node and the
low-potential-side power supply. Accordingly, the control node and
the low-potential-side power supply are not constantly connected to
each other. The power supply connecting circuit is interposed
between the control node and the high-potential-side power supply.
The ground connecting circuit is interposed between the control
node and the low-potential-side power supply so that the
high-potential-side power supply and the low-potential-side power
supply will not be electrically short-circuited to each other. The
power supply connecting circuit and the ground connecting circuit
are turned on and off in the trade-off manner.
[0027] At the time of the precharge, the power supply connecting
circuit is turned on while the ground connecting circuit is kept in
the OFF position. Accordingly, the bit line is connected to the
high-potential-side power supply via the control node and the power
supply connecting circuit, and the bit line is thereby precharged.
At the time, the precharge switching element is ON.
[0028] In the step-down operation, the power supply connecting
circuit is turned off, and the ground connecting circuit is turned
on. Accordingly, the bit line is connected to the
low-potential-side power supply via the control node and the ground
connecting circuit, and the voltage of the bit line is stepped
down. At the time, the precharge switching element is ON.
[0029] As described, the ground connecting circuit constituting the
step-down circuit is connected to the node (control node) of the
precharge switching element on the side of the high-potential-side
power supply (side of the power supply connecting circuit). The
ground connecting circuit is not directly connected to the bit
line. The precharge switching element is interposed between the
ground connecting circuit and the bit line. Accordingly, a load
capacity of the bit line is prevented from increasing. As a result,
it becomes possible to shorten the time which requires for carrying
out charge and discharge of the bit line at the time of data read.
Thereby, the data reading speed improves.
[0030] In the semiconductor storage device thus constituted, the
power supply connecting circuit and the ground connecting circuit
may be integrally constituted as an inverter which is turned on and
off by a common precharge/step-down control signal. Because the
precharge/step-down control signal serves as a control signal of
the power supply connecting circuit and a control signal of the
ground connecting circuit, an area reduction can be improved.
Further, there are the following advantages: The on-off control of
the power supply connecting circuit and the on-off control of the
ground connecting circuit can be performed at the same time, which
makes it difficult for through current to flow; and the influence
of setup on input signals in the precharge circuit and the
step-down circuit can be lessened because the precharge/step-down
control signal serves as a control signal of the precharge circuit
and a control signal of the step-down circuit.
[0031] In the semiconductor storage device thus constituted, the
power supply connecting circuit and the ground connecting circuit
may be equally connected to a group of bit lines for a plurality of
columns corresponding to memory cells for a plurality of columns.
Thus constituted, the sharing of the constituent elements can be
realized, and a layout size can be largely reduced.
[0032] According to the present invention, the load capacity of the
bit line can be prevented from increasing. Further, the speed at
which the data is read from the memory cell can be prevented from
deteriorating, and data-read errors can be reliably prevented from
happening.
[0033] The technology according to the present invention can
control the increase of the load capacity of the bit line and
prevent the speed at which the data is read from the memory cell
from deteriorating. Therefore, the technology is advantageously
applied to a semiconductor storage device such as SRAM for which a
higher reading speed is strongly demanded.
BRIEF DESCRIPTION OF THE DRAWINGS
[0034] These and other objects as well as advantages of the
invention will become clear by the following description of
preferred embodiments of the invention and be specified in the
claims attached hereto. A number of benefits not recited in this
specification will come to the attention of the skilled in the art
upon the implementation of the present invention.
[0035] FIG. 1 is a circuit diagram illustrating a constitution of a
semiconductor storage device according to a preferred embodiment 1
of the present invention.
[0036] FIG. 2 is a circuit diagram specifically illustrating a
power supply connecting circuit and a ground connecting circuit
according to the preferred embodiment 1.
[0037] FIG. 3 is a timing chart illustrating an operation of the
semiconductor storage device according to the preferred embodiment
1.
[0038] FIG. 4A is a circuit diagram illustrating a constitution of
a semiconductor storage device according to a preferred embodiment
2 of the present invention.
[0039] FIG. 4B is a timing chart illustrating an operation of the
semiconductor storage device according to the preferred embodiment
2.
[0040] FIG. 5 is a circuit diagram illustrating an equivalent
circuit according to the preferred embodiment 2.
[0041] FIG. 6 is a circuit diagram illustrating a constitution of a
semiconductor storage device according to a preferred embodiment 3
of the present invention.
[0042] FIG. 7A is a circuit diagram illustrating a constitution of
a semiconductor storage device according to the conventional
technology.
[0043] FIG. 7B is a timing chart illustrating an operation used in
the conventional technology.
DETAILED DESCRIPTION OF THE INVENTION
[0044] Hereinafter, preferred embodiments of the present invention
are described referring to the drawings.
Preferred Embodiment 1
[0045] FIG. 1 is a circuit diagram illustrating a constitution of a
semiconductor storage device according to a preferred embodiment 1
of the present invention. Bit lines BL and /BL are connected to
sources of a pair of access transistors in a memory cell 1 of SRAM
(Static Random Access Memory) activated by access from a word line
WL. A precharge circuit 2, an equalizing circuit 3 and a reading
circuit 4 are connected to the bit lines BL and /BL. The equalizing
circuit 3 comprises an equalizing transistor QP3. A PMOS transistor
constitutes the equalizing transistor QP3. A source and a drain of
the equalizing transistor QP3 are connected to the bit lines BL and
/BL, and an equalizing control signal EQ is applied to a gate
thereof. The precharge circuit 2 comprises switching transistors
QP1 and QP2, which are PMOS transistors serving as precharge
switching elements, and a power supply connecting circuit 5. A
ground connecting circuit 6, which is a step-down circuit, is
connected to the bit lines BL and /BL with the precharge circuit 2
interposed therebetween. A source of the precharge transistor QP1
is connected to the bit line BL, and a source of the precharge
transistor QP2 is connected to the bit line /BL. A gate of the
precharge transistor QP1 and a gate of the precharge transistor QP2
are connected to each other, and further connected to the gate of
the equalizing transistor QP3. A drain of the precharge transistor
QP1 and a drain of the precharge transistor QP2 are connected to
each other, thereby serving as a control node Nc. The control node
Nc is connected to a high-potential-side power supply (VDD) via the
power supply connecting circuit 5, and further connected to a
low-potential-side power supply (GND) via the ground connecting
circuit 6. The power supply connecting circuit 5 is turned on and
off by a precharge control signal PC to thereby connect/disconnect
the control node Nc with respect to the high-potential-side power
supply. The ground connecting circuit 6 is turned on and off by a
step-down control signal DC to thereby connect/disconnect the
control node Nc with respect to the low-potential-side power
supply. The ON-OFF control by the power supply connecting circuit 5
and the ON-OFF control by the ground connecting circuit 6 are
related to each other in a trade-off manner.
[0046] The ground connecting circuit 6 constitutes a main
constituent of a step-down function. The main constituent of the
step-down function is not directly connected to the bit lines BL
and /BL, but is connected to the bit lines BL and /BL with the
switching transistors QP1 and QP2 interposed therebetween. The
present invention is characterized in that the main constituent of
the step-down function is thus provided in the bit lines BL and /BL
with the switching transistors QP1 and QP2 interposed therebetween.
Because of the constitution thus described, load capacities of the
bit lines BL and /BL can be prevented from increasing.
[0047] FIG. 2 is a circuit diagram specifically illustrating the
power supply connecting circuit 5 and the ground connecting circuit
6 shown in FIG. 1. A PMOS precharge transistor QP0 constitutes the
power supply connecting circuit 5, and an NMOS step-down transistor
QN0 constitutes the ground connecting circuit 6. A source of the
precharge transistor QP0 in the power supply connecting circuit 5
is connected to the high-potential-side power supply, a drain
thereof is connected to the control node Nc, and the precharge
control signal PC is applied to a gate thereof. A source of the
step-down transistor QN0 in the ground connecting circuit 6 is
connected to the low-potential-side power supply, a drain thereof
is connected to the control node Nc, and the step-down control
signal DC is applied to a gate thereof.
[0048] An operation of the semiconductor storage device thus
constituted according to the present preferred embodiment is
described referring to a timing chart shown in FIG. 3. At a timing
t0, the low-active precharge control signal PC is in assert state,
the step-down control signal DC is in negate state, and the
low-active equalizing control signal EQ is in assert state. Because
the precharge control signal PC is at "L" level, the precharge
transistor QP0 is in the ON state, and a potential of the control
node Nc is the power supply voltage VDD. Further, the equalizing
control signal EQ is at "L" level; therefore, the switching
transistors QP1 and QP2 and the equalizing transistor QP3 is in the
ON state. Accordingly, the power supply voltage VDD of the control
node Nc is applied to the bit lines BL and /BL, and the bit lines
BL and /BL are thereby precharged.
[0049] Prior to the activation of the word line WL (t3), at a
timing t1, the precharge control signal PC is negated to turn to
"H" level, and the precharge transistor QP0 is thereby turned off.
Then, the control node Nc is disconnected from the power supply
voltage VDD, which leaves the bit lines BL and /BL in a floating
state. At the time, the switching transistors QP1 and QP2 remain in
the ON state.
[0050] At a timing t2, the step-down control signal DC is asserted
to turn to "H" level. Then, the step-down transistor QN0 in the OFF
state so far is turned on, and a potential of the control node Nc
is stepped down to the ground level. Because the switching
transistors QP1 and QP2 are in the ON state at the time, the
voltages of the bit lines BL and /BL are stepped down in response
to the potential drop in the control node Nc. The potentials of the
bit lines BL and /BL are stepped down along with a certain time
constant and to a predetermined voltage level. A possible example
of the predetermined voltage level is VDD-Vth. Vth is a threshold
voltage of the MOS transistors. At the time, a step-down speed in
the bit line is lower as the voltage is closer to the predetermined
voltage. Therefore, variability in a time length from the time when
the step-down transistor QN0 is turned on to the time when the
switching transistors QP1 and QP2 are turned on and variability in
the step-down level resulting from the characteristic variability
of the step-down transistor QN0 can be controlled.
[0051] At a timing t3, the equalizing control signal EQ is negated
to turn to "H" level. At the time, the switching transistors QP1
and QP2 are turned off, and the step-down transistor QN0 is thereby
completely disconnected from the bit lines. Immediately after that,
the word line WL is activated to turn to "H" level. When the
equalizing control signal EQ turns to at "H" level, the switching
transistors QP1 and QP2 are turned off and thereby disconnected
from the ground, which stops the step-down operation for the bit
lines BL and /BL. Further, the equalizing transistor QP3 is turned
off, which stops the equalizing operation for the bit lines BL and
/BL. Since the word line WL is at "H" level, data is read from the
memory cell 1. The reading operation at the time is similar to that
of the conventional technology.
[0052] According to the present preferred embodiment, the step-down
transistor QN0, which is the main constituent of the step-down
function, is not directly connected to the bit lines BL and /BL,
and the switching transistors QP1 and QP2 are interposed
therebetween. Accordingly, the load capacities of the bit lines BL
and /BL can be prevented from increasing. Further, during the
reading operation, the time constant used when the bit lines BL and
/BL shift from the power supply voltage VDD to the ground level is
lessened so that the data can be read at a high speed. Provided
that an amount of time necessary for the data read in the
conventional technology is Tu and an amount of time necessary for
the data read according to the present invention is Ta,
Ta<Tu.
[0053] The PMOS transistors are used as the switching transistors
QP1 and QP2. Accordingly, during the step-down operation, when the
voltages of the bit lines BL and /BL are stepped down, source-drain
voltages in the switching transistors QP1 and QP2 are reduced, and
the step-down capacities of the PMOS transistors QP1 and QP2 are
lessened. As a result, variability of the step-down levels in the
bit lines can be effectively alleviated in the case where a timing
of terminating the step-down control varies.
Preferred Embodiment 2
[0054] FIG. 4A is a circuit diagram illustrating a constitution of
a semiconductor storage device according to a preferred embodiment
2 of the present invention. FIG. 5 is a circuit diagram
illustrating an equivalent circuit shown in FIG. 4A. The gate of
the precharge transistor QP0 and the gate of the step-down
transistor QN0 are connected to each other, and these transistors
QP0 and QN0 constitute an inverter Inv. The precharge transistor
QP0 and the step-down transistor QN0 are controlled by a
precharge/step-down control signal PDC which is a control signal
common to them.
[0055] An operation of the semiconductor storage device thus
constituted according to the present preferred embodiment is
described referring to a timing chart shown in FIG. 4B. At a timing
t10, the precharge/step-down control signal PDC is at "L" level,
and the low-active equalizing control signal EQ is in assert state.
Because the precharge/step-down control signal PDC is at "L" level,
the precharge transistor QP0 is in the ON state, while the
step-down transistor QN0 is in the OFF state, and the potential of
the control node Nc is accordingly the power supply voltage VDD.
Because the equalizing control signal EQ is at "L" level, the
switching transistors QP1 and QP2 and the equalizing transistor QP3
is in the ON state. Accordingly, the power supply voltage VDD of
the control node Nc is applied to the bit lines BL and /BL, and the
bit lines BL and /BL are precharged.
[0056] Prior to the activation of the word line WL (t12), at a
timing t11, the precharge/step-down control signal PDC turns to "H"
level, and as soon as the precharge transistor QP0 is turned off,
the step-down transistor QN0 is turned on. Accordingly, the control
node Nc is disconnected from the power supply voltage VDD and
connected to the ground at the same time. At the time, the
switching transistors QP1 and QP2 are in the ON state; therefore,
the voltages of the bit lines BL and /BL are stepped down in
response to the potential drop of the control node Nc. The
potentials of the bit lines BL and /BL are stepped down along with
a certain time constant and to a predetermined voltage level
(VDD-Vth).
[0057] At a timing t12, the equalizing control signal EQ is negated
to turn to "H" level, and the word line WL is activated to turn to
"H" level. When the equalizing control signal EQ is at "H" level,
the switching transistors QP1 and QP2 are turned off, and thereby
disconnected from the ground, which stops the step-down operation
for the bit lines BL and /BL. Further, the equalizing operation for
the bit lines BL and /BL also stops since the equalizing transistor
QP3 is turned off. Since the word line WL is at "H" level, data is
read from the memory cell 1.
[0058] At a timing t13, the word line WL is at "L" level, and the
data reading operation is terminated. At a timing t14, the
precharge/step-down control signal PDC turns to "L" level, and the
control node Nc is precharged with the power supply voltage. At the
same time, the equalizing control signal EQ is asserted, and the
switching transistors QP1 and QP2 and the equalizing transistor QP3
are turned on. Accordingly, the bit lines BL and /BL are precharged
with the power supply voltage.
[0059] According to the present preferred embodiment, the
precharge/step-down control signal PDC is shared for the control
signal for the power supply connecting circuit 5 (precharge
transistor QP0) and the control signal for the ground connecting
circuit 6 (step-down transistor QN0), which improves an area
reduction. Further, the on-off control of the power supply
connecting circuit 5 and the ground connecting circuit 6 is
performed at the same time. Therefore, variability in the step-down
level and through current can be controlled even if there is a
variation in the timing between the turn-off of the power supply
connecting circuit 5 and the turn-on of the ground connecting
circuit 6 or between the turn-on of the power supply connecting
circuit 5 and the turn-off of the ground connecting circuit 6.
[0060] In the preferred embodiment 1, the control signals for the
precharge circuit 2 are the precharge control signal PC and the
step-down control signal DC. In the present preferred embodiment,
however, only the precharge/step-down control signal PDC is used.
As a result, in the precharge circuit 2, the influence of setup on
input signals is lessened.
Preferred Embodiment 3
[0061] FIG. 6A is a circuit diagram illustrating a constitution of
a semiconductor storage device according to a preferred embodiment
3 of the present invention. The inverter Inv is connected equally
to the control nodes Nc in the precharge circuits 2 provided with
the step-down function which are provided in a group of bit lines
BL and /BL in a plurality of memory cells 1 parallel-arranged in a
column direction. More specifically describing the constitution,
the power supply connecting circuit 5 (precharge transistor QP0),
ground connecting circuit 6 (step-down transistor QN0) and
precharge/step-down control signal PDC are shared among the group
of bit lines BL and /BL. An operation according to the present
preferred embodiment is similar to that of the preferred embodiment
2. According to the present preferred embodiment, wherein the
constituent elements are shared, a layout size can be largely
reduced.
[0062] While there has been described what is at present considered
to be preferred embodiments of this invention, it will be
understood that various modifications may be made therein, and it
is intended to cover in the appended claims all such modifications
as fall within the true spirit and scope of this invention.
* * * * *