U.S. patent application number 13/098568 was filed with the patent office on 2011-08-25 for flash memory device capable of improving read performance.
This patent application is currently assigned to SAMSUNG ELECTRONICS CO., LTD.. Invention is credited to Dong-Hyuk CHAE.
Application Number | 20110208903 13/098568 |
Document ID | / |
Family ID | 39398797 |
Filed Date | 2011-08-25 |
United States Patent
Application |
20110208903 |
Kind Code |
A1 |
CHAE; Dong-Hyuk |
August 25, 2011 |
FLASH MEMORY DEVICE CAPABLE OF IMPROVING READ PERFORMANCE
Abstract
A flash memory device, related system ad method are disclosed.
The memory device includes a memory cell array a page buffer
receiving read data, wherein the page buffer includes a main
register transferring read data to a cache register during an read
operation, and a control logic block controlling operation of the
page buffer during the read operation, such that initialization of
the main register continuously extends beyond a time period during
which read data is transferred from the main register to the cache
register.
Inventors: |
CHAE; Dong-Hyuk; (Seoul,
KR) |
Assignee: |
SAMSUNG ELECTRONICS CO.,
LTD.
Suwon-si
KR
|
Family ID: |
39398797 |
Appl. No.: |
13/098568 |
Filed: |
May 2, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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12044179 |
Mar 7, 2008 |
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13098568 |
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Current U.S.
Class: |
711/103 ;
711/E12.008 |
Current CPC
Class: |
G06F 2212/2022 20130101;
G06F 12/0893 20130101; G11C 16/26 20130101 |
Class at
Publication: |
711/103 ;
711/E12.008 |
International
Class: |
G06F 12/00 20060101
G06F012/00 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 19, 2007 |
KR |
10-2007-0026658 |
Claims
1. A flash memory device comprising: a memory cell array configured
to store N-bit read data, where N is a positive integer; a page
buffer circuit comprising a page buffer configured to receive read
data from the memory cell array during a read operation, wherein
the page buffer comprises a main register transferring read data to
a cache register during the read operation; and a control logic
block configured to control operation of the page buffer during the
read operation such that initialization of the main register
continuously extends beyond a time period during which read data is
transferred from the main register to the cache register.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This U.S. non-provisional patent application is a
continuation of U.S. patent application Ser. No. 12/044,179 filed
on Mar. 7, 2008, which claims priority under 35 U.S.C. .sctn.119 to
Korean Patent Application No. 10-2007-0026658 filed on Mar. 19,
2007, the collective subject matter of which is hereby incorporated
by reference.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to semiconductor memory
devices. More particularly, the invention relates to flash memory
devices executing cache read functions.
[0003] Driven by ever-growing demands for higher performance
contemporary memory systems including flash memory devices have
incorporated a cache read functionality. During a cache read
operation, previous read data stored in a cache register is output
to an external circuit while current read data is read from memory
through a main register. An exemplary cache read operation will be
described with reference to FIG. 1.
[0004] Referring to FIG. 1, a read command, a corresponding read
data address, and a read operation start indication are provided to
a memory system incorporating flash memory (hereafter, "a flash
memory system") according to a predetermined timing sequence. In
the constituent flash memory device, after receiving the read start
command, a ready/busy signal R/nB transitions from logically "high"
to a logically "low" state (i.e., "goes low"). Operation of the
main register is initiated after the ready/busy signal R/nB goes
low during a first time period P1. The read data identified by the
address is read from memory by operation of the main register
during a second time period P2. Then, current read data stored in
the main register are transferred to a cache register during a
third time period P3. After the current read data is transferred to
the cache register from the main register, the ready/busy signal
R/nB goes high.
[0005] In response to the ready/busy signal R/nB going high, a
cache read command is provided to the flash memory device by an
external device (e.g., a memory controller in the flash memory
system). Upon receiving the cache read command, the ready/busy
signal R/nB in the flash memory device goes low during a fourth
time period P4 and then returns high. During the fourth time period
P4 defined by the transition of the ready/busy signal R/nB, current
read data is transferred to the cache register from the main
register. Following this read data transfer, the ready/busy signal
R/nB goes high. Then, operation of the main register is initiated
after the ready/busy signal R/nB goes high beginning a fifth time
period P5. Thus, read data is output from memory through the main
register and read data stored in the cache register is output to
the external device during the fifth and sixth time periods P5 and
P6.
[0006] According to this sequence of steps in the cache read
operation, previous read data is output to the external circuit
from the cache register when the main register is initiated during
the fifth time period P5. However, noise commonly associated with
the provision of power voltages within the flash memory system
occur during the output of the previous read data to the external
circuit from the cache register. In addition, noise associated with
the initiation of main register operation is also apparent during
this time frame. Thus, the simultaneous generation of noise by the
initialization of main register operation and output of previous
read data from the cache register, may generally degrade channel
conditions and cause data errors to arise in the read data being
transferred.
SUMMARY OF THE INVENTION
[0007] In one embodiment, the invention provides a flash memory
device comprising; a memory cell array configured to store N-bit
read data, where N is a positive integer, a page buffer circuit
comprising a page buffer configured to receive read data from the
memory cell array during a read operation, wherein the page buffer
comprises a main register transferring read data to a cache
register during the read operation, and a control logic block
configured to control operation of the page buffer during the read
operation such that initialization of the main register
continuously extends beyond a time period during which read data is
transferred from the main register to the cache register.
[0008] In another embodiment, the invention provides a method of
performing a read operation in a flash memory device comprising a
memory cell array; and a page buffer circuit comprising a page
buffer, wherein the page buffer comprises a main register and a
cache register, the method comprising; initiating operation of the
main register, after transferring read data to the cache register,
deactivating the main register, receiving a cache read command
after deactivation of the main register, reactivating the main
register in response to receiving the cache read command,
transferring read data from the main register to the cache register
upon reactivation of the main register, and maintaining activation
of the main register during a delay period following complete
transfer of the read data from the main register to the cache
register.
[0009] In another embodiment, the invention provides a memory
system comprising; a memory controller configured to control a
flash memory device in response to a read command and a cache read
command provide by an external circuit. The flash memory device
comprises; a memory cell array configured to store N-bit read data,
where N is a positive integer, a page buffer circuit comprising a
page buffer configured to receive read data from the memory cell
array during a read operation, wherein the page buffer comprises a
main register transferring read data to a cache register during the
read operation, and a control logic block configured to control
operation of the page buffer during the read operation such that
initialization of the main register continuously extends beyond a
time period during which read data is transferred from the main
register to the cache register.
BRIEF DESCRIPTION OF THE FIGURES
[0010] FIG. 1 is a timing diagram illustrating a conventional cache
read operation;
[0011] FIG. 2 is a block diagram of a flash memory device operating
within a memory system according to an embodiment of the
invention;
[0012] FIG. 3 is a block diagram further illustrating the page
buffer shown in FIG. 2;
[0013] FIG. 4 is a timing diagram illustrating a cache read
operation for a flash memory device within a memory system
according to an embodiment of the invention;
[0014] FIG. 5 is a conceptual diagram further illustrating an
exemplary flow of read data during a cache read operation according
to an embodiment of the invention; and
[0015] FIG. 6 is a block diagram of a general computational system
incorporating a flash memory system according to an embodiment of
the invention.
DESCRIPTION OF EMBODIMENTS
[0016] Embodiments of the invention will now be described with
reference to the accompanying drawings. The invention may, however,
be variously embodied and should not be constructed as being
limited to only the illustrated embodiments. Rather, the
embodiments are provided as teaching examples.
[0017] FIG. 2 is a block diagram of a flash memory device adapted
for use within a memory system according to an embodiment of the
invention. In the illustrated embodiment, a NAND flash memory
device is assumed for purposes of description, but those skilled in
the art will understand that this is merely one example of a class
of flash memory devices that might be used within embodiments of
the invention.
[0018] Referring to FIG. 2, the flash memory device comprises a
memory cell array 100 of conventional arrangement storing N-bit
data, where N is a positive integer. A row selector 200 operates
under the control of control logic block 600 to select and drive
one or more rows within memory cell array 100. A page buffer
circuit 300 is configured to read data from memory cell array 100
during a reading operation and drive columns during with one or
more defined voltages during a programming operation. As is
conventional, page buffer circuit 300 may be composed of multiple
page buffers (PB) arranged in relation to the columns within memory
cell array 100.
[0019] Each page buffer PB within page buffer circuit 300, (see,
e.g., FIG. 3), may include a main register 301 and a cache register
302. According to this illustrated embodiment, during a cache read
operation, main register 301 is used to read data from memory cell
array 100 and cache register 302 is used to store data transferred
from main register 301. In various embodiments of the invention, a
page buffer (PB) may be variously configured according to the cache
read operation intended. Exemplary page buffer structure capable of
implementing a cache read function are disclosed, for example, in
U.S. Pat. Nos. 7,180,783; 7,042,770; and 6,996,014, the collective
subject matter of which is hereby incorporated by reference.
[0020] Returning to FIG. 2, a column selector 400 also operates
under the control of control logic block 600 to select a page
buffer within page buffer circuit 300 according to a defined data
unit size (e.g., byte or word). During the reading operation, read
data received in individual page buffer(s) selected by column
selector 400 are output to an external circuit (e.g., a memory
controller) by way of input/output (I/O) interface 500 also
controlled by control logic block 600.
[0021] During a programming operation, write data applied through
I/O interface 500 by control logic block 600 is loaded into
individual page buffer(s) selected by column selector 400. Control
logic block 600 operates to control overall functions of the flash
memory device, and may be implemented using well understood design
principals. In particularly relevant part to the illustrated
embodiments, control logic block 600 functions to control the
activation/deactivation of the ready/busy signal R/nB such that
initialization of one or more main register(s) 301 does not
coincide with the output of read data from one or more cache
register(s) 302. In other words, control logic block 600
deactivates the ready/busy signal R/nB following initialization of
main register(s) 301. After deactivating the ready/busy signal
R/nB, read data is output to the external circuit from cache
register(s) 302, as will be described in some additional detail
hereafter.
[0022] FIG. 4 is a timing diagram showing a cache read operation
performed by a flash memory device within a memory system according
to an embodiment of the invention. FIG. 5 is a related conceptual
diagram showing an exemplary flow of data during the cache read
operation. For convenience of description only a single page buffer
(PB) operation will be described with an understanding that cache
read operations enabled by embodiments of the invention may involve
more than one page buffer.
[0023] First, as shown in FIG. 4, a read command, a corresponding
address, and a read start indication are provided to a flash memory
device designed and operated in accordance with an embodiment of
the invention. Upon receiving the read start indication, control
logic block 600 activates (e.g., causes a high to low transition
of) the ready/busy signal R/nB to begin a first time period P10.
During the first time period P10, control logic block 600 initiates
operation of main register 301 using the ready/busy signal R/nB
(1.sup.st step indicated in FIG. 5 by the circled number 1). During
a following second period P20, the read data identified by the
address is read from a memory cell array 100 through main register
301 under the control of control logic block 600 (2.sup.nd step in
FIG. 5). Then, during a third period P30, read data is transferred
to cache register 302 from main register 301 by control logic block
600 (3.sup.rd step in FIG. 5). After transferring the read data to
cache register 302, control logic block 600 deactivates the
ready/busy signal R/nB.
[0024] In response to the deactivation of the ready/busy signal
R/nB, a cache read command is applied to the flash memory device
from the external circuit (4.sup.th step in FIG. 5). After
application of the cache read command, control logic block 600
reactivates the ready/busy signal R/nB.
[0025] The reactivation of the ready/busy signal R/nB begins a
fourth period P40 and read data is transferred to cache register
302 from main register 301 by control logic block 600 (5.sup.th
step in FIG. 5). Although the transfer of read data to cache
register 302 from main register 301 is complete, as shown in FIG.
4, the ready/busy signal R/nB is maintained in an activated state
for a delay period (i.e., a fifth time period P50) beyond the
completion of read data transfer cycle, and main register 301
remains initiated (6.sup.th step in FIG. 5). Only after the delay
period is complete will control logic block 600 deactivate the
ready/busy signal R/nB. In response to the deactivation of the
ready/busy signal R/nB, read data is output to the external circuit
from cache register 302 (7.sup.th step in FIG. 5) during a sixth
time period P60 and read data is provided from memory cell array
100 via main register 301 (7.sup.th step in FIG. 5).
[0026] As can be seen from the above description, the
initialization period for main register 301 does not overlap with
the output of read data from cache register 302. In other words,
noise generated by the initialization of main register 301 will be
non-coincident with noise generated by the output of read data from
cache register 302. Thus, it is far less likely that channel
transmission characteristics will be degraded to the point where
data errors occur.
[0027] As a result of these improved data transfer properties, a
flash memory devices and related memory system incorporating a
nonvolatile memory according to an embodiment of the invention, are
very well suited to mobile electronic devise such as cellular
phones, personal digital assistants (PDA), digital cameras,
portable gaming consoles, digital versatile disks (DVDs), routers,
global positioning systems (GPS), MP3 players, HD TVs, flash
storage devices, etc.
[0028] FIG. 6 is a general block diagram of a computational system
susceptible to the incorporation of a flash memory device or a
flash memory system according to an embodiment of the invention.
The computing system comprises a microprocessor 710, a user
interface 720, a modem 760 such as a baseband chipset, a memory
controller 740, and the flash memory device 750, all of which are
electrically connected to a bus 701. Flash memory device 750 may be
configured as described above in relation to FIG. 2.
[0029] In flash memory device 750, N-bit data, where N is a
positive integer processed or to be processed by microprocessor
710, is stored by the operative means of memory controller 740. If
the computational system shown in FIG. 6 is a mobile apparatus, it
will further comprise a battery 730 supplying power. Although not
shown in FIG. 6, the computational system may further comprise an
application chipset, a camera image processor (e.g., CMOS image
sensor; CIS), a mobile DRAM, etc. Further, the flash memory device
and/or associated memory controller may be configured on a memory
card with the flash memory system.
[0030] As described above, since the initialization period for a
main register does not overlap with the output of read data from a
cache register, data communication reliability and performance is
improved for data read operations performed by a flash memory
device according to an embodiment of the invention.
[0031] The above-disclosed subject matter is to be considered
illustrative, and not restrictive, and the appended claims are
intended to cover all such modifications, enhancements, and other
embodiments, which fall within the scope of the invention. Thus, to
the maximum extent allowed by law, the scope of the present
invention is to be determined by the broadest permissible
interpretation of the following claims and their equivalents.
* * * * *