U.S. patent application number 12/672404 was filed with the patent office on 2011-08-18 for light emitting diode with metal piles and multi-passivation layers and its manufacturing method.
Invention is credited to Jong Hyeob Baek, Jung-In Kang, Gang Ho Kim, Sang Mook Kim, Hong Seo Yom, Young Moon Yu.
Application Number | 20110198635 12/672404 |
Document ID | / |
Family ID | 40341914 |
Filed Date | 2011-08-18 |
United States Patent
Application |
20110198635 |
Kind Code |
A1 |
Kim; Sang Mook ; et
al. |
August 18, 2011 |
Light Emitting Diode With Metal Piles and Multi-Passivation Layers
and Its Manufacturing Method
Abstract
The present invention relates to a light emitting diode with
metal piles and one or more passivation layers and a method for
making the diode including a first steps of performing mesa etching
respectively on a first semiconductor layer and a second
semiconductor layer belonging to stacked layers formed on a
substrate in sequence! a second step of forming a reflector layer
on the mesa-etched upper and side face! a third step of contacting
one or more first electrodes with the first semiconductor layer and
one or more second electrodes through the reflector layer with the
second semiconductor layer; a fourth step of forming a first
passivation layer on the reflector layer and the contacted
electrodes; and a fifth step of connecting the first electrodes to
a first bonding pad through one or more first electrode lines,
bring one ends of vertical extensions having the shape of a metal
pile into contact with one or more second electrodes, and
connecting the other ends of the vertical extensions to a second
bonding pad through one or more second electrode lines. As effects
of the present invention, the loss of light emitting area decreases
and current diffusion efficiency increases.
Inventors: |
Kim; Sang Mook; (Gwangju,
KR) ; Baek; Jong Hyeob; (Daejeon, KR) ; Kim;
Gang Ho; (Gwangju, KR) ; Kang; Jung-In;
(Gwangju, KR) ; Yom; Hong Seo; (Seoul, KR)
; Yu; Young Moon; (Seoul, KR) |
Family ID: |
40341914 |
Appl. No.: |
12/672404 |
Filed: |
August 7, 2008 |
PCT Filed: |
August 7, 2008 |
PCT NO: |
PCT/KR08/04607 |
371 Date: |
April 6, 2011 |
Current U.S.
Class: |
257/98 ;
257/E33.072; 438/27 |
Current CPC
Class: |
H01L 24/05 20130101;
H01L 2224/05573 20130101; H01L 2224/1703 20130101; H01L 2224/13
20130101; H01L 2933/0016 20130101; H01L 2924/00014 20130101; H01L
24/02 20130101; H01L 33/46 20130101; H01L 2224/05548 20130101; H01L
24/06 20130101; H01L 2224/05568 20130101; H01L 2224/02375 20130101;
H01L 2224/06102 20130101; H01L 2224/49107 20130101; H01L 2224/13024
20130101; H01L 33/385 20130101; H01L 2924/00014 20130101; H01L
2224/05599 20130101 |
Class at
Publication: |
257/98 ; 438/27;
257/E33.072 |
International
Class: |
H01L 33/60 20100101
H01L033/60 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 8, 2007 |
KR |
10-2007-0079741 |
Claims
1-24. (canceled)
25. A method for making a light emitting diode, comprising; a first
step of performing mesa-etching to reveal a designated area of a
first semiconductor layer after forming the first semiconductor
layer, an active layer and a second semiconductor layer on a
substrate in sequence; a second step of forming a reflector layer
on the top of the second semiconductor layer left after the
mesa-etching; a third step of forming a first electrode(s) on the
first semiconductor layer revealed by mesa-etching and a second
electrode(s) on the upper face of the reflector layer; a fourth
step of forming a first passivation layer on the area excluding the
first electrode(s) and the second electrode(s) to reveal the first
electrode(s) and the second electrode(s); and a fifth step of
forming a first bonding pad and a second bonding pad in the
designated area on the top of the first passivation layer,
connecting the first electrodes with a first bonding pad through
one of more first electrode lines, and vertical extensions, in the
shape of a metal pile, and connecting the second electrodes with a
second bonding pad through one or more second electrode lines.
26. The method according to claim 25, wherein the first passivation
layer is formed with two films made of same or different
material.
27. The method according to claim 25, further comprising a sixth
step of forming a second passivation layer on the part except the
first electrodes, the second electrodes, the first bonding pad and
the second bonding pad area.
28. The method according to claim 27, further comprising a step of
removing the substrate of the first step, thus exposing membrane
shape after the sixth step.
29. The method according to claim 25, wherein the total thickness
of the formed passivation layer is equal to or greater than 1
um.
30. The method according to claim 25, further comprising a step of
removing the substrate, thus exposing membrane shape after the
fifth step.
31. The method according to claim 25, wherein the first
semiconductor layer is n type; the second semiconductor layer is p
type; and the first passivation layer is formed with one material
or more selected from the group consisting of polyimide, epoxy
resin and SOG.
32. The method according to claim 25, wherein the first
semiconductor layer is n type and the second semiconductor layer is
p type, further comprising a step of forming the second passivation
layer made of glass or ceramic film in addition to the first
passivation layer.
33. The method according to claim 25, wherein the first
semiconductor layer is n type and the second semiconductor layer is
p type, further comprising a step of forming glass or fluorescent
layer after removing the substrate after the fifth step.
34. The method according to claim 25, wherein the first
semiconductor layer is n type and the second semiconductor layer is
p type, further comprising a step of texturing one side of the
substrate to have regular or irregular prominence and depression
after the fifth step.
35. The method according to claim 25, wherein the first
semiconductor layer is n type and the second semiconductor layer is
p type, further comprising a step of texturing one side of the
semiconductor layer that was once adhered to the substrate to have
regular or irregular prominence and depression after the fifth
step.
36. The method according to claim 25, further comprising a step of
texturing regularly or irregularly the second electrode contacted
directly with the second semiconductor layer under the reflector
layer.
37. A method for making a light emitting diode, comprising the step
of: making one or more holes regularly or irregularly to the upper
side of a semiconductor layer belonging to a stacked layer sequence
formed on one side of a substrate; forming vertical extensions in
the shape of a metal pile through the holes; and contacting one end
of each vertical extension with the semiconductor layer, and the
other end of each vertical extension with a bonding pad through one
or more electrode lines.
38. A light emitting diode, comprising; semiconductor layers with a
designated area of a first semiconductor layer revealed by
mesa-etching after forming the first semiconductor layer, an active
layer and a second semiconductor layer on a substrate in sequence;
a reflector layer formed on the top of the second semiconductor
layer left after the mesa-etching; one or more first electrodes
formed on the top of the first semiconductor layer revealed by the
mesa-etching; one or more second electrodes formed on the top of
the reflector layer; a first passivation layer on the area
excluding the first electrode(s) and the second electrode(s) to
reveal the first electrode(s) and the second electrode(s); and a
first bonding pad and a second bonding pad formed in the designated
area on the top of the first passivation layer, connecting
electrically the first electrodes with the first bonding pad
through one of more first electrode lines, and vertical extensions
in the shape of a metal pile with the same polarity, and connecting
electrically the second electrodes with a second bonding pad
through one or more second electrode lines with the same
polarity.
39. The light emitting diode according to claim 38, wherein the
first electrode line and the second electrode line are respectively
a first bonding pad and a second bonding pad.
40. The light emitting diode according to claim 38, further
comprising a first bonding pad gathering the first electrode lines
and a second bonding pad gathering the second electrode lines
respectively.
41. The light emitting diode according to claim 38, further
comprising; holes formed regularly or irregularly through the first
passivation layer; and one or more vertical extensions in the shape
of a metal pile in the holes, wherein one ends of the extensions
are contacted with the first semiconductor layer and the other ends
of extensions are exposed on the passivation layer and contacted
with one or more first electrode lines.
42. The light emitting diode according to claim 38, wherein the
first semiconductor layer is n type; the second semiconductor layer
is p type; the first passivation layer is formed with two films
made of same or different material: and the total thickness of the
passivation layers is equal to or greater than 1 um.
43. The light emitting diode according to claim 38, wherein the
first semiconductor layer is n type; the second semiconductor layer
is p type; the first passivation layer is formed with one material
or more selected from the group consisting of polyimide, epoxy
resin and SOG; and the total thickness of the passivation layer is
equal to or greater than 1 um.
44. The light emitting diode according to claim 38, wherein the
first semiconductor layer is n type and the second semiconductor
layer is p type, further comprising a second passivation layer
formed on the area except the first and second bonding pad area and
made of glass or ceramic film in addition to the first passivation
layer.
45. The light emitting diode according to claim 44, wherein the
total thickness of the passivation layer is equal to or greater
than 1 um.
46. The light emitting diode according to claim 38, wherein the
first semiconductor layer is n type and the second semiconductor
layer is p type, further comprising prominence and depression
formed by regular or irregular texturing on the one side of the
substrate.
47. The light emitting diode according to claim 38, wherein the
first semiconductor layer is n type and the second semiconductor
layer is p type, further comprising prominence and depression
formed by regular or irregular texturing on the one side of the
semiconductor layer that was once adhered to the substrate.
48. The light emitting diode according to claim 38, wherein the
first semiconductor layer is n type and the second semiconductor
layer is p type, further comprising prominence and depression
formed by regular or irregular texturing of one or more second
electrodes in directly contact with the second semiconductor layer
under the reflector layer.
Description
TECHNICAL FIELD
[0001] The present invention relates to a light emitting diode and
its manufacturing method to enhance luminous efficiency by
rearrangement of metal pads adopting metal piles and
multi-passivation layers.
[0002] In addition, the present invention of pad rearrangement
relates to chip scale package of light emitting diode and its
manufacturing method. In detail, the present invention may be
embodied as a light emitting diode with n type and p type
semiconductor layers on a substrate and its manufacturing method,
particularly including a primary electrode provided on a
semiconductor layer, and a secondary electrode, which is
electrically connected to the primary electrode, with a first
passivation interposed between the electrodes.
BACKGROUND ART
[0003] Conventional flip chip semiconductor light emitting diodes
are generally used because of high current diffusion efficiency and
optical extraction efficiency, and excellent thermal
characteristics with a silicon sub mount (see FIG. 1).
[0004] However, the flip chip semiconductor light emitting diodes
have problems such as loss of active layer area caused by
mesa-etching and drop of reflector layer efficiency caused by metal
pads formed with big size.
[0005] In addition, though vertical type chip structure, which is
recently developed by removing a sapphire substrate, has advantages
of brightness enhancement due to increased light emitting area as
compared with a lateral type light emitting diode, there are
problems such as degradation of electrical characteristics and
reliability due to a problem of ohmic contact formed between a N
contact pad and a n type semiconductor layer at the area where the
substrate is removed.
[0006] In addition, conventional nitride semiconductor light
emitting diodes generally have a sapphire substrate, and on that, a
layer sequence of a buffer layer, a n type nitride semiconductor
layer, an active layer of multiple quantum well(MQW), a p type
nitride semiconductor are formed in sequence. The p type nitride
semiconductor layer and the active layer have the structure that a
part of their area is eliminated with processes such as etching,
thus exposing a part of the upper side of the n type nitride
semiconductor. An n type electrode is formed on the exposed n type
nitride semiconductor layer, and a p type bonding electrode is
formed after a transparent electrode is formed to make ohmic
contact on the p type nitride semiconductor layer.
[0007] A light emitting diode made with a conventional
manufacturing process may be bonded on sub mount substrate made of
silicon or ceramic as a package type for practical use or mounted
on other types of packages.
[0008] Processes such as die bonding to bond the light emitting
diode with these package materials and wire bonding for injecting
electrons and holes are essential to a conventional light emitting
diode manufacturing method.
[0009] FIG. 10 shows a sectional diagram of a light emitting diode
stacked in the conventional light emitting diode manufacturing
process, and the picture of electrons and holes movement.
[0010] Referring to FIG. 10, on a sapphire substrate 1100, an n
type nitride semiconductor layer 1101, an active layer 1102 of
multiple quantum well, a p type nitride semiconductor 1103 are
formed in sequence. A p type electrode 1104 is located on the p
type nitride semiconductor layer 1103, and an n type electrode is
located on an exposed area, formed after etching, of the n type
nitride semiconductor layer 1101.
[0011] The p type electrode and the n type electrode has a
structure for being connected to PCB or other packages with wire
1106.
[0012] Generally, a buffer layer working as a buffer may be
included between a substrate and a semiconductor layer in a
conventional structure.
[0013] Referring to FIG. 10, electrons and holes from different
semiconductor areas come together in the active layer, thus
emitting light and generating it outside.
[0014] Due to the module structure made according to a conventional
light emitting diode manufacturing method, the total thickness of a
package gets thicker to cause problems of low optical extraction
efficiency and performance, and also problems of yield and
productivity related to complex processing.
[0015] Changing these package types may means a cost burden such as
establishing a new production line. Therefore, it has been required
to suggest improved structure of a light emitting diode module
while maintaining current package types and processes.
DISCLOSURE
Technical Problem
[0016] The present invention has an object to provide a light
emitting diode and its manufacturing method of a pad rearrangement
structure including one or more metal piles and one or more
passivation layers to enhance brightness, electrical
characteristics and thermal characteristics by decreasing the
mesa-etched area for n contact and relieving design restrictions
applied to p contact to solve current diffusion problems of the
conventional technology.
[0017] In addition, another object of the present invention is to
apply a pad rearrangement structure, for solving efficiency and
productivity problems of a conventional light emitting diode, to
light emitting chips or light emitting diodes so as to finish the
first half of entire packaging processes and be ready for mounting
at the steps of making light emitting chips.
[0018] Another object of the present invention relates to applying
a pad rearrangement structure to chip scale package based light
emitting diodes having decreased package thickness with a flexible
structure.
[0019] Another object of the present invention relates to applying
the invention of a pad rearrangement structure to a light emitting
diode manufacturing method for eliminating conventional wire
bonding and die bonding to simplify light emitting diode
manufacturing process, and thus save manufacturing cost and improve
productivity.
Technical Solution
[0020] To achieve the objects, the light emitting diode and it
manufacturing method of a pad rearrangement structure includes the
step of forming mesa etching face of semiconductors and a first
electrode line for current diffusion, forming a first passivation
layer to insulate the line, and forming a second electrode line for
bonding and thus improves the efficiency of the light emitting
diode.
[0021] The present invention includes a first step of performing
mesa etching on a first semiconductor layer and a second
semiconductor layer which are stacked in sequence, a second step of
forming a reflector layer on the mesa etched upper and side face,
and a third step of contacting one or more first electrodes with
the first semiconductor layer and one or more second electrodes
through the upper face of the reflector layer. In addition, it is
preferable to include a fourth step of forming a first passivation
layer on the area except the first and second electrodes contacted
respectively, and a fifth step of connecting the first electrodes
with a first bonding pad through one or more first electrode lines,
and a vertical extension, in the shape of a metal pile, of one or
more second electrodes with a second bonding pad through one or
more second electrode lines. On this occasion, the thickness of the
passivation layer needs to be equal to or greater than 1 um,
preferably 100 um to achieve the device rigidity required in case
that the substrate is removed.
[0022] It is preferable that the first passivation layer is formed
with two films made of same or different material. On this
occasion, the thickness of the passivation layer needs to be 1 um
or more, preferably 100 um to achieve the rigidity of the device
required in case that the substrate is removed.
[0023] It is preferable to include a step of forming a second
passivation layer on the area except the first and second bonding
pad area formed in the fifth step. On this occasion, the thickness
of the passivation layer needs to be 1 um or more, preferably 100
um to achieve the rigidity of the device required in case that the
substrate is removed. If surface roughening is applied to the
second passivation layer, optical extraction efficiency can be
increased.
[0024] It is preferable that the first and second bonding pads are
formed with ion beam deposition or plating in the present
invention.
[0025] It is preferable in the present invention that one or more
holes are formed regularly or irregularly to a semiconductor layer
belonging to a stacked layer sequence formed on one side of a
substrate; one end of each electrode formed through the holes
contacts with the semiconductor layer; and the other end of each
electrode contacts with a bonding pad through one or more electrode
lines.
[0026] It is preferable that the present invention comprises a
reflector layer formed on the upper and side faces of mesa-etched
semiconductor layers belonging to a layer sequence stacked on one
side of a substrate, one or more first electrodes being contacted
directly with the first semiconductor layer as a mesa-etched
lowered layer, and one or more second electrodes, being preferably
textured regularly or irregularly, contacted directly with the
second semiconductor layer under the reflector layer. In addition,
it is preferable that the present invention includes one or more
first electrode lines, formed on the upper side of the reflector
layer, connected with the first electrodes in sequence, one or more
second electrode lines connected with the second electrodes via
vertical extensions, in the shape of a metal pile, of the second
electrodes in sequence, and a first bonding pad gathering the first
electrode lines and a second bonding pad gathering the second
electrode lines respectively.
[0027] It is preferable in the present invention that the first
electrode, the first electrode lines and the first bonding pad have
same polarity.
[0028] It is preferable in the present invention that the second
electrode, the second electrode lines and the second bonding pad
have same polarity.
[0029] It is preferable in the present invention that the first
electrode and the second electrode have different polarity.
[0030] The present invention may be embodied in the structure of a
light emitting diode including a first semiconductor layer and a
second semiconductor layer, belonging to a layer sequence stacked
on a substrate in sequence, being mesa-etched respectively; a
reflector layer formed on upper and lateral surfaces of the mesa
etched second semiconductor layer; one or more first electrodes
contacted directly with the mesa etched first semiconductor layer
as a lowered layer; one or more second electrodes contacted
directly with the mesa etched second semiconductor layer under the
reflector layer; a first passivation layer formed on the upper side
of the reflector layer; one or more first electrode lines formed on
the first passivation layer; and one or more second electrode lines
contacted with one or more vertical extensions, in the shape of a
metal pile and exposed on the passivation layers, of one or more
second electrodes. In case that only one first electrode line and
only one second electrode line exist, each electrode line may be
prepared to be used as a bonding pad (see FIG. 19).
[0031] As another embodiment of the present invention, in case that
the light emitting diode has one or more first electrode lines, the
first electrodes lines may gather together into any one line among
the lines and the only one first electrode line may act as a
bonding pad. In the same manner, one or more second electrode lines
may gather together into any one line among the lines and the only
one second electrode line may act as a bonding pad. On this
occasion, the first electrode and the second electrode have
different polarity.
[0032] As another embodiment of the present invention, the light
emitting diode may further include a first bonding pad gathering
the first electrode lines, and a second bonding pad gathering the
second electrode lines respectively. As one of advantages according
to this embodiment, bonding pad design may be easier in comparison
with the previous embodiment of the first electrode lines or the
second electrode lines gathering to any one line among the lines
respectively. On this occasion, the first electrode and the second
electrode have different polarity.
[0033] Another embodiment of the present invention may further
includes holes formed regularly or irregularly on the first
passivation layer of the light emitting diode, and one or more
vertical extensions having the shape of a metal pile in the holes,
wherein one ends of the parts are contacted with the first
semiconductor layer and other ends of the parts are exposed on the
passivation layer and contacted with one or more first electrode
lines. In the same manner, the second electrodes may have vertical
extensions having the shape of a metal pile like that of the first
electrodes. This structure enhances the degree of evenness.
[0034] The present invention of pad rearrangement may be applied to
chip scale package of light emitting diodes and its manufacturing
method. In particular, it may be applied to a light emitting diode
chip and its manufacturing method having an n type semiconductor
layer and a p type semiconductor on a substrate includes n type
electrodes and p type electrodes placed on semiconductor layers, n
type electrode line extensions and p type electrode line extensions
electrically connected with the n type electrodes and the p type
electrodes through interposed first passivation layer and they may
be acting as bonding pads.
[0035] In case that the construction of pad rearrangement applies
to chip scale package based light emitting diodes, it is possible
to simplify light emitting diode manufacturing process, save the
manufacturing cost due to eliminating conventional wire bonding and
die bonding, and enhance luminous efficiency with decreased
thickness of package. In addition, the light emitting diode formed
with the construction has advantages of being ready to be mounted
to other packages and PCBs without additional preparation.
[0036] To achieve the effect as an object of the present invention,
the embodiment of the present invention of a light emitting diode
including an n type semiconductor layer and a p type semiconductor
on a substrate may comprise n type electrodes on an n type
semiconductor layer and p type electrodes on a p type semiconductor
layer, n type electrode line extensions electrically connected with
the n type electrodes and p type electrode line extensions
electrically connected with the p type electrodes passing through
interposed first passivation layer.
[0037] The first passivation layer may be formed with one or more
materials selected from the group consisting of polyimide, epoxy
resin and SOG (Spin on glass).
[0038] The p type second electrodes formed on the p type
semiconductor layer may be placed on a reflector layer made of
materials to enhance optical reflection. The reflector layer is
preferably a metal reflector layer made of metal.
[0039] Another embodiment of the present invention may further
comprise a second passivation layer, made of glass or ceramic film,
separating the first electrodes from the second electrodes.
[0040] To achieve the construction, a method of manufacturing a
light emitting diode, in particular including an n type
semiconductor layer and a p type semiconductor on a substrate, may
comprise steps of forming n type electrodes on an n type
semiconductor layer and p type electrodes on a p type semiconductor
layer, and forming n type electrode line extensions electrically
connected with the n type electrodes and p type electrode line
extensions electrically connected with the p type electrodes
passing through interposed first passivation layer.
[0041] The first passivation layer may be made of polyimide, epoxy
resin, and SOG.
[0042] In the embodiment of manufacturing method of the present
invention, the n type electrode line extension and p type electrode
line extension may be formed on a second passivation layer, not the
first passivation layer, made of glass of ceramic film.
[0043] Another embodiment of the present invention may further
comprise a step of etching the first passivation layer or
depositing after patterning to expose the part of the first
electrodes to connect electrically the n type electrodes and n type
electrode line extensions, and the p type electrodes and p type
electrode line extensions respectively.
[0044] Another embodiment of the present invention may further
comprise a step of forming glass or fluorescent layer after
eliminating the substrate from the light emitting diode processed
with the above mentioned steps.
[0045] Another embodiment of the present invention may further
comprise a step of texturing one side of the substrate of the light
emitting diode processed with the above mentioned steps, thus
having regular or irregular prominence and depression.
[0046] Another embodiment of the present invention may further
comprise a step of forming a metal reflector layer on the
semiconductor layers for optical reflection before forming n type
electrodes and p type electrodes on the semiconductor layers.
[0047] The semiconductor layers may be compound semiconductor,
preferably nitride compound semiconductor layers.
[0048] The present invention may be applied to a light emitting
diode having the construction to finish the first half processes of
packaging at the level or step of chip making processes belonging
to manufacturing method of a light emitting diode.
[0049] The light emitting diode according to the embodiment of the
present invention is ready to be mounted on PCBs without additional
preparation, which decreases thickness of a package and makes it
possible to obtain a package with flexible structure.
[0050] In another embodiment of the present invention of a light
emitting diode manufacturing method, a layer for n type electrodes
and p type electrodes is deposited in the first place for the
contact of the p type semiconductor layer and the contact of the n
type semiconductor layer after mesa etching performed for the
contact of the n type semiconductor layer.
[0051] On this occasion, a layer formed of material to enhance
optical reflection around the contact area of the p type
semiconductor layer is a reflector layer. The reflector layer,
preferably a metal reflector layer, may be made of metal layer. The
layer may be formed not only just around the contact area of the p
type semiconductor layer but also broadly around outer stacked
surface of the light emitting diode.
[0052] After performing the processes, a first passivation layer is
formed before depositing the n type electrode line extensions and
the p type electrode line extensions. The material for first
passivation layer may be chosen from various material such as
polyimide, epoxy, and SOG but not limited to the listed
materials.
[0053] The shape of the n type electrode line extensions and the p
type electrode line extensions is preferably rectangular form, but
not limited to any specific shape.
[0054] On this occasion, etching or patterning processes are need
to expose the upper part of the n type electrodes and the p type
electrodes to the outside for making contact between the n type
electrode line extensions and the n type electrodes on the n type
semiconductor layer, and contact between the p type electrode line
extensions and the p type electrodes on the p type semiconductor
layer, respectively.
[0055] While depositing the first passivation layer after forming
the n type electrodes and the p type electrodes, it is possible to
open the area of the n type electrodes and the p type electrodes
with patterning. Otherwise, after depositing the first passivation
layer on the formed the n type electrodes and the p type
electrodes, it is possible to open the area of the n type
electrodes and the p type electrodes with etching the first
passivation layer.
[0056] Because the n type electrode line extension and the p type
electrode line extension respectively contacted with the n type
electrode and the p type electrode through the vertical extensions
having the shape of a metal pile may perform a role of bonding
pads, it is preferable to decide the size and position of the pads
in advance to be immediately mounted on other packages.
[0057] As occasion demands, a second passivation layer may be
formed after forming the first electrode. As a second passivation
layer, glass or ceramic film with high thermal conductivity may be
adhered.
[0058] As a ceramic film, materials such as Boron nitride(BN),
Alumina, Aluminum nitride(AlN), Beryllium oxide(BeO) or the like
may be used.
[0059] In another embodiment of the present invention of a pad
rearrangement construction, a light emitting element (chip) or a
light emitting diode may be mounted without wire bonding or die
bonding and the structure of prominence and depression may be
formed on the one side of the substrate to enhance performance of
the diode while layers are stacked on the other side of the
substrate, In addition, the structure of prominence and depression
may be made on the semiconductor layer after eliminating the
substrate.
[0060] The structure of prominence and depression is formed with
texturing processes. There are methods of using regular patterns or
random patterns in texturing processes. As a method of using
regular patterns, it is preferable to use nano imprinting, electron
beam lithography and laser holograph. After forming the regular
patterns, dry etching processes may be applied to form a texturing
structure on the substrate or the semiconductor layer.
[0061] As a method of using random patterns, a texturing structure
of random patterns may be formed with dry etching processes after
forming cluster of nano size through heat treatment processes of
metals such as Ag, Ni, Pt, Pd, or the like.
[0062] In addition, random texturing may be formed with wet
chemical etching processes. In detail, random texturing structure
may be formed on the substrate or the semiconductor layer after
etching with a KOH solution.
[0063] A light emitting diode(chip) according to another embodiment
of present invention may have additional layer such as glass or
fluorescent layers to enhance optical extraction efficiency after
eliminating a substrate with the method of LLO (Laser Lift Off) or
the like.
[0064] The light emitting diode (chip) made with the method as
described above may be separated to be used respectively with usual
cutting methods which are generally available to a person having
ordinary skill in the art. It may be preferably separated into
pieces through dicing or scribing processes.
[0065] To package finished light emitting diodes of various
embodiments according to the present invention, the diodes may be
mounted directly, without additional preparations, to the solders
formed on package materials such as PCBs, or other types of
packages.
Advantageous Effects
[0066] According to the present invention, there is no need to add
secondary bonding pads in addition to the pads already formed on
mesa etched face because electrodes are formed on a same plane.
Therefore, the number of pads decreases, and light absorption by
the pads is prevented, thus enhancing optical power as a
result.
[0067] Further, there is no direct contact between a reflector
layer and bonding pads, thus resulting in the effect of decreasing
the loss of the reflector layer.
[0068] Furthermore, an ohmic contact problem of vertical type chip
is settled and similar performance to that of the vertical type
chip is obtained in case of adding the process of eliminating a
substrate.
[0069] In addition, as described above, the construction of the
present invention of pad rearrangement may be applied to light
emitting diodes, resulting in remarkably improved effect in
productivity and manufacturing cost saving due to skipping wire
bonding and die bonding processes by performing chip making and
packaging processes at the same time directly on a substrate.
[0070] In addition, the construction of the present invention of
pad rearrangement adopts processes of LLO, thus resulting in light
emitting diodes having combined merits of a vertical integration
type light emitting diodes and a lateral growth type light emitting
diode and flexible structure with thin thickness.
[0071] In addition, the construction of the present invention of
pad rearrangement may be applied to backlight units and compact
lighting field requiring minimum size packaging, and further, light
emitting diodes having various structures can made easily and
simply through processes such as forming additional glass or
fluorescent layer at the wafer processing level, thus generating
economic value due to productivity and yield improvement.
DESCRIPTION OF DRAWINGS
[0072] FIG. 1 is a cross-sectional view of a conventional light
emitting diode;
[0073] FIG. 2 is a flowchart illustrating a method of manufacturing
a light emitting diode using pad rearrangement according to an
embodiment of the present invention;
[0074] FIGS. 3, 4, 5, 6, 7 and 8 are schematic diagrams
illustrating a method of manufacturing a light emitting diode using
pad rearrangement according to an embodiment of the present
invention;
[0075] FIG. 9 is a cross-sectional view of a light emitting diode
using pad rearrangement according to an embodiment of the present
invention;
[0076] FIG. 10 is a cross-sectional view schematically illustrating
an example of light emitting diodes according to conventional
art;
[0077] FIGS. 11 to 14 are schematic diagrams illustrating in
sequence a method of manufacturing a light emitting diode with pad
rearrangement according to another embodiment of the present
invention;
[0078] FIGS. 15 and 16 are schematic diagrams illustrating in
sequence a method of manufacturing a light emitting diode with pad
rearrangement according to another embodiment of the present
invention;
[0079] FIG. 17 is a cross-sectional view schematically illustrating
a light emitting diode with pad rearrangement according to another
embodiment of the present invention;
[0080] FIG. 18 is a cross-sectional view schematically illustrating
a shape that a substrate is eliminated from a light emitting diode
according to another embodiment with pad rearrangement of the
present invention; and
[0081] FIG. 19 is a cross-sectional view of a light emitting diode
using pad rearrangement according to another embodiment of the
present invention.
[0082] Numerals of drawings are explained as follows; [0083] 100: a
substrate, [0084] 110: a first semiconductor layer [0085] 120: an
active layer, [0086] 130: a second semiconductor layer [0087] 140:
a reflector layer, [0088] 150: a first electrode [0089] 160: a
second electrode, [0090] 300: a first passivation layer [0091] 310:
a first electrode line, [0092] 320: a second electrode line [0093]
330: a first bonding pad, [0094] 340: a second bonding pad [0095]
350: a second passivation layer [0096] 1100, 1200, 1300, 1400,
1500: a substrate [0097] 1101, 1201, 1301, 1401, 1501: an n type
semiconductor layer [0098] 1102, 1202, 1302, 1402, 1502: an active
layer [0099] 1103, 1203, 1303, 1403, 1503: a p type semiconductor
layer [0100] 1104, 1204, 1304, 1404, 1504: a p type electrode (a
second electrode) [0101] 1105, 1205, 1305, 1405, 1505: a n type
electrode (a first electrode) [0102] 1106: wire [0103] 1206, 1306,
1406, 1506: a metal reflector layer [0104] 1207, 1307, 1407, 1507:
a first passivation layer [0105] 1208, 1308, 1408, 1508: a second
passivation layer [0106] 1209, 1309, 1409, 1509: a p type electrode
line extension (a second electrode line extension) [0107] 1210,
1310, 1410, 1510: an n type electrode line extension (a first
electrode line extension)
BEST MODE
[0108] Embodiments of the present invention will be described in
detail in reference to the drawings. Applying the numerals to the
elements of the respective drawings, detailed description on
conventional structure and function is abridged because that may be
an obstacle to understanding of the spirit of the present
invention.
[0109] FIG. 2 is a flowchart illustrating a method of manufacturing
a light emitting diode according to an embodiment of the present
invention, and FIGS. 3 to 8 are schematic diagrams illustrating a
method of manufacturing a light emitting diode according to an
embodiment of the present invention.
[0110] Referring to FIG. 2, it may be preferable to use a sapphire
substrate or a wafer for a substrate 100, and also to use nitride
semiconductor for the semiconductor.
[0111] Mesa etching is performed on narrow area instead of
conventional wide area etching when mesa etching (S200) is
performed to form a first electrode 150 in a semiconductor layer
sequence stacked with a first semiconductor layer 110, an active
layer 120, and a second semiconductor layer 130 in sequence on the
substrate 100 (see FIG. 3).
[0112] After mesa etching, a reflector layer 140 for ohmic contact
and reflection is formed (S210) on the upper face of the second
semiconductor layer 130 (see FIG. 4).
[0113] A first electrode 150 is directly connected with the upper
face of the first semiconductor layer 110 and a second electrode
160 on the upper face of the reflector layer 140 is directly
connected with the second semiconductor layer 130 (S220) (see FIG.
5).
[0114] On this occasion, the number of the first electrode 150 and
the second electrode 160 may be a plurality of one or more. The
electrodes are formed with very small size. Effective radiation
area is increased with regular of irregular texturing as compared
to a conventional chip, and optical power is enhanced.
[0115] After performing the contact processes of the first
electrodes 150 and the second electrodes 160 respectively, a first
passivation layer 300 is formed (S230) on the area except the
contact area of the first electrodes 150 and the second electrodes
160 (see FIG. 6).
[0116] The first passivation layer 350 may be formed of one
passivation film or two passivation films. In case of forming the
layer with two films, they may be made of same or different
material.
[0117] One or more first electrodes 150 exposed on the upper face
of the first passivation 350 is connected to a first bonding pad
with one or more first electrode lines 310. One or more second
electrodes 160 have vertical extensions (not shown in FIG. 7, refer
to connection part between 1209 and 1204 of FIG. 14) having the
shape of a metal pile, passing through the first passivation layer,
which are exposed on the upper face of the first passivation layer.
The extensions are connected (S240) to a second bonding pad 340
with the second electrode lines 320 (see FIG. 7).
[0118] On this occasion, the size of the bonding pads 330, 340 is
not limited because it is irrelevant to luminous efficiency of a
light emitting diode. The pads 330, 340 are formed with e-beam
deposition or plating.
[0119] In stacked semiconductor layers formed according to the
above mentioned processes, a second passivation layer 350 may be
formed (S250) on the other area except the area of the first and
second bonding pads 330,340 (see FIG. 8).
MODE FOR INVENTION
[0120] FIG. 9 is a cross-sectional view of a light emitting diode
with pad rearrangement according to an embodiment of the present
invention.
[0121] FIG. 9 shows a substrate 100, a first semiconductor layer
110, an active layer 120, a second semiconductor layer 130, a
reflector layer 140, a first electrode 150, a second electrode 160,
a first passivation layer 300, a first electrode line 310, a second
electrode line 320, a first bonding pad 330, and a second bonding
pad 340 (see FIG. 19).
[0122] The first semiconductor layer 110 and the second
semiconductor layer 130 are made of GaN, and the layers are stacked
on the substrate 100.
[0123] The active layer 120 is formed between the first
semiconductor layer 110 and the second semiconductor layer 130.
[0124] The reflector layer 140 is formed on a part of stacked
semiconductor layers which are formed of a first semiconductor
layer 110, an active layer 120, and a second semiconductor layer
130 in sequence, except the lowered face prepared with mesa
etching.
[0125] On this occasion, the lowered face formed with mesa etching
belongs to a first semiconductor layer 110.
[0126] When electrical energy inputted to semiconductor layers is
transformed into optical energy as output, the reflector layer 140
increases optical efficiency by reflecting light not to leak to the
outside.
[0127] Particularly, because the second electrodes 160 are etched
to be small size and connected to a second bonding pad 340, there
is no direct contact between the reflector layer 140 and the
bonding pad, which prevents the reflector layer 140 from being
damaged.
[0128] The first electrode 150 and the second electrode 160 have
opposite polarity each other, and the first electrode 150 is
directly connected to the first semiconductor layer 110 exposed by
the mesa etching.
[0129] The second electrode 160 may be located in holes formed in
parts of the reflector layer 140 to directly contact the second
semiconductor layer 130 placed under the reflector layer 140.
[0130] On this occasion, one or more first and second electrodes
150, 160 may be formed with small size, and textured regularly or
irregularly.
[0131] A first passivation layer 300 protects a exposed first
semiconductor layer 110 and the reflector layer 140, the area
except the first and the second electrodes 150, 160 in other words,
from external electrical influence when the first and the second
electrodes 150, 160 are formed.
[0132] According to the structure, there is effect of enhanced
optical power as effective light emitting area increases in
contrast with a conventional light emitting diode.
[0133] The first electrode line 310 contacts one or more first
electrodes, and the second electrode line 320 contacts one or more
second electrodes through contacting with the vertical extensions
having the shape of a metal pile.
[0134] The first bonding pad 330 electrically may combine one or
more first electrodes 150 through contacting with the first
electrode lines 310, and the second bonding pad 340 electrically
may combine one or more second electrodes 160 through contacting
with the second electrode lines 320.
[0135] Accordingly, one bonding pad may be placed on a
semiconductor layer according to polarity, regardless of the size
of the semiconductor area, thus preventing optical absorption and
resulting in enhanced optical power.
[0136] In addition, there is no need to additionally form bonding
pads on the first semiconductor layer 110 because the first
electrode lines 310 are used.
[0137] While observing from the outside a light emitting diode chip
with pad rearrangement according to another embodiment of the
present invention, a metal reflector layer formed on the upper face
of the light emitting diode and p type electrode line extensions
contacted with p type second electrodes are shown.
[0138] A light emitting diode chip with pad rearrangement according
to another embodiment of the present invention discloses the
structure of n type electrode line extensions formed on a upper
face, electrically connected to the n type first electrodes on an n
type nitride semiconductor layer.
[0139] Therefore, after forming the n type electrode line
extensions electrically connected to the n type first electrodes,
chips may be are divided for obtaining respective light emitting
diode. The divided chips may be directly mounted, which provides
merits in processes.
[0140] A plurality of respective light emitting diode chips may be
obtained after stacking in sequence layers of light emitting diode
chips over large area, and chips with texturing structure on one
side of themselves may be produced as occasion demands.
[0141] FIGS. 11 and 12 are cross-sectional views illustrating in
sequence a method of manufacturing a light emitting diode according
to another embodiment of the present invention.
[0142] FIG. 11 shows that electrodes are formed on respective
semiconductor layers after exposing an n type semiconductor layer
1201 with etching some part of light emitting diode chips which are
formed of an n type GaN compound semiconductor layer 1201, an
active layer 1202 and a p type GaN compound semiconductor layer
1203 in sequence on the substrate 1200.
[0143] On this occasion, a first electrode as an n type electrode
1205 is formed on an n type GaN compound semiconductor layer 1201
and a second electrode as an p type electrode 1204 is formed on a p
type GaN compound semiconductor layer 1203.
[0144] The light emitting diode may include a buffer layer
additionally.
[0145] Further, the light emitting diode may include additionally a
metal reflector layer 1206 to increase optical reflection between a
second electrode and a p type GaN compound semiconductor layer.
[0146] At the next step shown in FIG. 12, a first passivation layer
1207 is stacked on the upper face of the whole light emitting diode
including a second electrode 1204, a metal reflector layer 1206, a
first electrode 1205, and semiconductor layers. The first
passivation layer may be made of highly polymerized organic
compounds and particularly epoxy resin may be used. On this
occasion, the thickness of the passivation layer needs to be equal
to or greater than 1 um, preferably 100 um for the rigidity of the
device in case of eliminating a substrate.
[0147] A first passivation layer of the present invention may be
preferably formed with two films made of same or different
material. On this occasion, the whole thickness of the passivation
layer needs to be equal to or greater than 1 um, preferably 100 um
for the rigidity of the device in case of eliminating a
substrate.
[0148] It may be preferable to have the step of forming a second
passivation layer on the part except the first and second bonding
pad area, following the fifth step of the present invention. On
this occasion, the whole thickness of the passivation layer needs
to be equal to or greater than 1 um, preferably 100 um for the
rigidity of the device in case of eliminating a substrate. Optical
extraction efficiency may be increased in case of applying surface
roughening on the second passivation layer (see FIG. 19).
[0149] Referring to FIG. 13, a second passivation layer 1208 is
formed on a first passivation layer 1207. Glass, silicon material,
or the like may be used to the second passivation layer and this
process may be skipped.
[0150] FIG. 14 shows that parts of the first electrodes and the
second electrodes are exposed due to etching processes for
respective electrical connect of the first electrodes 1205 and the
second electrodes 204. Then, one ends of vertical extensions having
the shape of a metal pile are respectively connected to the first
electrodes and the second electrodes, and the other ends of the
vertical extensions are respectively connected to the first
electrode line extension and the second electrode line extension
having the shape of a pad on the second passivation layer 1208. In
other words, a p type electrode line extension 1209 is connected to
the second electrode 1204 as a p type electrode, and a n type
electrode line extension 1210 is connected to the first electrode
1204 as an n type electrode, respectively.
[0151] Light emitting diode chips formed in this way may be divided
into respective chips by scribing or dicing processes according to
required dimension and shape.
[0152] Each light emitting chip may be mounted to a package
directly using the p type electrode line extension 1209 and the n
type electrode line extension 1210 as contact points, that is to
say or bonding pads.
[0153] FIGS. 15 and 16 are schematic diagrams illustrating in
sequence a method of manufacturing a light emitting diode according
to another embodiment of the present invention.
[0154] Processes up to forming a first passivation layer 1307 and a
second passivation layer 1308 of light emitting diode chips are
similar to the overall processes of FIGS. 6 through 14.
[0155] FIG. 15 shows a method of etching to expose a first
electrode 1305. According to FIG. 15, a light emitting diode is
formed with mesa etching up to a first electrode 1305 which is
formed relatively widely, thus having gradient of slope on the side
face.
[0156] Next, referring to FIG. 16, the area that a second electrode
1304 is formed is etched and a p type electrode line extension 1309
is formed and connected to the second electrode 1304 through the
etched area.
[0157] An n type electrode line extension 1310, being connected to
the first electrode as n type, is formed along the slanted side
face of the light emitting structure up to the upper face of a
second passivation layer.
[0158] It is reasonable that the second electrode line extension
1309 as p type and the first electrode 1310 as n type are separated
not to contact each other.
[0159] The above mentioned embodiment of the present invention
shows dividing with scribing or dicing processes along the first
electrode part as a boundary, thus making respective chips.
[0160] FIG. 17 schematically shows a light emitting diode chips,
according to another embodiment of the present invention, having
the structure of prominence and depression formed with texturing on
the substrate processed as illustrated in FIGS. 6 through 16.
[0161] As illustrated FIG. 17, regular texturing structure may be
applied, or roughening of random shape may be formed also.
[0162] As another embodiment of the present invention, FIG. 18
shows texturing of the semiconductor layer exposed after a
substrate is eliminated by processes such as LLO from a completed
light emitting diode.
[0163] A method of eliminating substrate is not limited to LLO and
any conventional arts, related to the method, a person having
ordinary skill in the art will use may be applied.
[0164] As described above, the present invention is explained
referring to various preferable embodiments; however, a person
having ordinary skill in the art will appreciate that various
modifications, additions and substitutions are possible, without
departing from the scope and spirit of the invention as disclosed
in the following claims.
* * * * *