U.S. patent application number 13/079577 was filed with the patent office on 2011-07-21 for method of fabricating a semiconductor device.
This patent application is currently assigned to Hynix Semiconductor Inc.. Invention is credited to Tae Un Youn.
Application Number | 20110177685 13/079577 |
Document ID | / |
Family ID | 41607429 |
Filed Date | 2011-07-21 |
United States Patent
Application |
20110177685 |
Kind Code |
A1 |
Youn; Tae Un |
July 21, 2011 |
Method of Fabricating a Semiconductor Device
Abstract
The present invention discloses a method of fabricating a
semiconductor memory device including forming sequentially a gate
insulating layer and a first conductive pattern on a semiconductor
substrate; forming a protective layer on surfaces of the first
conductive pattern and the gate insulating layer; performing an
etching process to form a trench, the etching process being
performed such that the protective layer remains on side walls of
the first conductive pattern to form a protective pattern; forming
an isolation layer in the trench; etching the isolation layer;
removing the protective pattern above a surface of the isolation
layer; and forming sequentially a dielectric layer and a second
conductive layer on surfaces of the isolation layer, the protective
pattern and the first conductive pattern.
Inventors: |
Youn; Tae Un; (Cheongju-si,
KR) |
Assignee: |
Hynix Semiconductor Inc.
Icheon-si
KR
|
Family ID: |
41607429 |
Appl. No.: |
13/079577 |
Filed: |
April 4, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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12406821 |
Mar 18, 2009 |
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13079577 |
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Current U.S.
Class: |
438/592 ;
257/E21.158 |
Current CPC
Class: |
H01L 27/11521 20130101;
H01L 21/76224 20130101 |
Class at
Publication: |
438/592 ;
257/E21.158 |
International
Class: |
H01L 21/28 20060101
H01L021/28 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 1, 2008 |
KR |
10-2008 75749 |
Claims
1. A method of fabricating a semiconductor memory device, the
method comprising: sequentially forming a gate insulating layer and
a first conductive pattern on a semiconductor substrate; forming a
protective layer along surfaces of the first conductive pattern and
the gate insulating layer; performing an etching process to form a
trench and a gate insulating pattern such that the protective layer
remains on side walls of the first conductive pattern to form a
protective pattern; forming an isolation layer in the trench;
etching the isolation layer to a level below the top surface of the
first conductive pattern, and the protective layer of side walls of
the first conductive pattern to expose a portion of the protective
layer; removing the portion of the protective pattern above a
surface of the isolation layer; and sequentially forming a
dielectric layer and a second conductive layer on surfaces of the
isolation layer, the protective pattern and the first conductive
pattern.
2. The method of fabricating a semiconductor memory device of claim
1, wherein sequentially forming the gate insulating layer and the
first conductive pattern on the semiconductor substrate comprises:
forming a gate insulating layer on the semiconductor substrate;
forming a first conductive layer on the gate insulating layer; and
patterning the first conductive layer to form the first conductive
pattern on the gate insulating layer.
3. The method of fabricating a semiconductor memory device of claim
2, comprising forming the first conductive layer by sequentially
laminating an undoped polysilicon layer and a doped polysilicon
layer.
4. The method of fabricating a semiconductor memory device of claim
1, comprising forming the second conductive layer of a doped
polysilicon layer.
5. The method of fabricating a semiconductor memory device of claim
1, comprising forming the protective layer of a nitride layer.
6. The method of fabricating a semiconductor memory device of claim
5, comprising forming the nitride layer using a deposition process
or a nitrification process.
7. The method of fabricating a semiconductor memory device of claim
1, further comprising performing an oxidation process after the
trench is formed to compensate for damage to a surface of the
trench.
8. The method of fabricating a semiconductor memory device of claim
1, comprising forming the protective layer to a thickness in a
range of 50 .ANG. to 100 .ANG..
9. The method of fabricating a semiconductor memory device of claim
1, comprising etching the isolation layer is to a level above the
top surface of the gate insulating layer to prevent the gate
insulating layer from being exposed.
10. The method of fabricating a semiconductor memory device of
claim 1, comprising removing the portion of the protective pattern
above a surface of the isolation layer by a dry etching process or
a wet etching process.
11. The method of fabricating a semiconductor memory device of
claim 10, wherein the wet etching process is performed by utilizing
phosphoric acid (H.sub.3PO.sub.4) solution as an etchant.
12. The method of fabricating a semiconductor memory device of
claim 1, further comprising performing an oxidation process after
performing the etching process to form a trench.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This is a division of U.S. application Ser. No. 12/406,821
filed Mar. 18, 2009, which claims the priority benefit under USC
119 of KR 10-2008-0075749, filed on Aug. 1, 2008, the entire
respective disclosures of which are incorporated herein by
reference.
BACKGROUND OF THE INVENTION
[0002] The present invention relates generally to a semiconductor
memory device and a method of fabricating the same, and more
particularly relates to a semiconductor memory device capable of
inhibiting generation of etching damage caused during a process of
fabricating a semiconductor memory device, and a method of
fabricating the same.
[0003] In semiconductor memory devices, a flash memory device
comprises a plurality of strings. In each string, memory cells are
disposed in serial. The string is formed on an active region, and
an isolation layer is formed between the strings so that the
strings are electrically isolated from each other.
[0004] A method for fabricating a flash memory device is
illustrated in detail as follows.
[0005] On a semiconductor substrate, a gate insulating layer, a
first conductive layer to be used for forming a floating gate, a
dielectric layer, a second conductive layer to be used for forming
a control gate and a gate mask pattern are sequentially formed. An
etching process is performed according to the gate mask pattern to
form an isolation trench on the semiconductor substrate. In
particular, in the etching process performed for forming the
trench, side walls of the first conductive layer and the gate
insulating layer are exposed so that an etching damage can be
generated.
[0006] In addition, after the trench is formed, an oxidation
process can be performed for compensating for etching damage in the
trench. At this time, a "bird's beak" phenomenon, in which the
thickness of both ends of the exposed gate insulating layer is
increased, can be generated.
SUMMARY OF THE INVENTION
[0007] In the present invention, when a process for forming an
isolation trench is performed, a first conductive layer to be used
for forming a floating gate is patterned to form a first conductive
pattern, a protective layer is then formed along surfaces of the
first conductive pattern and an exposed gate insulating layer, and
therefore the side walls of the first conductive layer can be
protected by the protective layer during the subsequent etching
process. In addition, since the gate insulating layer is formed
such that a width of the gate insulating pattern is wider than that
of the first conductive pattern, it is possible to compensate a
defect caused by an excessive oxidation generated at both ends of
the gate insulating layer during the subsequent etching
process.
[0008] A method of fabricating a semiconductor memory device
according to an embodiment includes: sequentially forming a gate
insulating layer and a first conductive pattern on a semiconductor
substrate; forming a protective layer along surfaces of the first
conductive pattern and the gate insulating layer; performing an
etching process to form a trench; the etching process being
performed such that the protective layer remains on side walls of
the first conductive pattern to form a protective pattern; forming
an isolation layer in the trench; etching the isolation layer;
removing the protective pattern above a surface of the isolation
layer; and forming sequentially a dielectric layer and a second
conductive layer along surfaces of the isolation layer, the
protective pattern and the first conductive pattern.
[0009] Sequentially forming the gate insulating layer and the first
conductive pattern on the semiconductor substrate can include
forming a gate insulating layer on the semiconductor substrate;
forming a first conductive layer on the gate insulating layer; and
patterning the first conductive layer to form the first conductive
pattern on the gate insulating layer.
[0010] The first conductive layer is preferably formed by
laminating sequentially an undoped polysilicon layer and a doped
polysilicon layer. The second conductive layer is preferably formed
of a doped polysilicon layer.
[0011] The protective layer preferably is formed of a nitride
layer, which can be formed through a deposition process or a
nitrification process. For example, the protective layer preferably
has a thickness in a range of about 50 .ANG. to about 100
.ANG..
[0012] The method of fabricating a semiconductor memory device can
further include performing an oxidation process to compensate for
damage to a surface of the trench after the trench is formed.
[0013] Etching the isolation layer is preferably performed through
an etching process so as to prevent the gate insulating layer from
being exposed.
[0014] Removing the protective pattern above a surface of the
isolation layer is preferably performed by a dry etching process or
a wet etching process. For example, the wet etching process can be
performed by utilizing phosphoric acid (H3PO4) solution as the
etchant.
[0015] A semiconductor memory device according to an embodiment
includes a semiconductor substrate on which an active area and a
trench are formed; a gate insulating pattern formed on the active
area; a first conductive pattern formed on the gate insulating
pattern and having a width narrower than that of the gate
insulating pattern; protective patterns formed at lower ends of
both side walls of the first conductive pattern to allow upper ends
of both side walls of the first conductive pattern to be exposed;
and an isolation layer formed in the trench.
[0016] Preferably, the sum of a width of the first conductive
pattern and widths of the protective patterns formed at lower ends
of the side walls of the first conductive pattern is the same as a
width of the gate insulating pattern.
[0017] Also, a central portion of an upper portion of the isolation
layer is located below an edge portion of an upper portion of the
isolation layer.
[0018] The semiconductor memory device further preferably includes
a dielectric layer formed along surfaces of the isolation layer,
the protective pattern and the first conductive pattern; and a
second conductive layer formed on the dielectric layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The above and other features and advantages of the present
invention will become readily apparent by reference to the
following detailed description when considered in conjunction with
the accompanying drawings wherein;
[0020] FIG. 1A to FIG. 1I are sectional views for illustrating a
semiconductor memory device according to an embodiment of the
present invention and a method of fabricating the same.
DESCRIPTION OF SPECIFIC EMBODIMENTS
[0021] Hereinafter, the preferred embodiments of the present
invention will be explained in more detail with reference to the
accompanying drawings. However, it should be understood that the
embodiment of the present invention can be variously modified, the
scope of the present invention is not limited to the embodiment
described herein, and the embodiment is provided for explaining
more completely the present invention to those skilled in the
art.
[0022] FIG. 1A to FIG. 1I are sectional views for illustrating a
semiconductor memory device according to an embodiment of the
present invention and a method of fabricating the same.
[0023] Referring to FIG. 1A, a gate insulating layer 102 and a
first conductive layer 104 to be used for forming a floating gate
are formed on a semiconductor substrate 100. The gate insulating
layer 102 can be formed of an oxide layer. The first conductive
layer 104 can be formed of a polysilicon layer. For example, the
first conductive layer 104 can be formed of a doped polysilicon
layer or can be formed by laminating sequentially an undoped
polysilicon layer and a doped polysilicon layer.
[0024] Referring to FIG. 1B, gate mask patterns 106 are formed on
the first conductive layer 104. The gate mask patterns 106 can be
formed according to an isolation trench pattern. Subsequently, the
exposed first conductive layer (104 in FIG. 1A) can be patterned
according to the gate mask patterns 106 to form first conductive
patterns 104a. Preferably the gate insulating layer 102 is not
patterned at this point in the method.
[0025] Hereinafter, only one gate mask pattern and only one
conductive pattern are described as the example.
[0026] Referring to FIG. 1C, a protective layer 108 is formed along
a surface of the exposed conductive pattern 104a. For example, the
protective layer 108 can be formed on a surface of the exposed
first conductive pattern 104a, a surface of the gate insulating
layer 102 and a surface of the gate mask pattern 106.
[0027] To form the protective layer 108, a nitride layer can be
formed on the exposed gate insulating layer 102, the conductive
pattern 104a and the gate mask pattern 106 by performing a
deposition process, or the surfaces of the exposed layer and
patterns can be nitrified by performing a nitrification process.
Preferably the protective layer 108 is formed of a nitride layer
obtained by performing the deposition process. In other words, the
protective layer 108 should preferably protect a side wall of the
first conductive pattern 104a during a subsequent etching process,
and so it is preferable to form the nitride layer as the protective
layer 108. The thickness of the protective layer 108 may be
adjusted according to a dimension of the flash memory device. For
example, in the flash memory device having a critical dimension of
48 nanometers, the protective layer 108 can have a thickness of 50
.ANG. to 100 .ANG..
[0028] Referring to FIG. 1D, an etching process is performed for
forming a trench TC on the semiconductor substrate 100. A blanket
etching process or an etch back process can be performed as the
etching process. Due to the etching process, the protective layer
(108 in FIG. 1C) formed on the gate mask pattern 106 and the gate
insulating layer (102 in FIG. 1C) is partially removed. The
protective layer (108 in FIG. 1C) formed on side walls of the gate
mask pattern 106 and the first conductive pattern 104a remains and
acts as a protective pattern 108a. Therefore, the side walls of the
first conductive pattern 104a are not exposed.
[0029] If the etching process is further performed using the
protective pattern 108a, the exposed gate insulating layer (102 in
FIG. 1C) is patterned to form gate insulating patterns 102a, and a
portion of the semiconductor substrate 100 is etched to form a part
of trench TC. Preferably, the sum of a width the first conductive
pattern 104a and widths of the protective patterns 108a formed on
the side walls of the first conductive pattern 104a are about the
same as a width of the gate insulating pattern 102a, e.g., the same
in the region of the junction of the gate insulating pattern 102a
with the first conductive pattern 104a and the protective patterns
108a, at the lower ends of the protective pattern 108a. In
addition, during the etching process, the exposed gate mask pattern
106 is etched partially so that a thickness thereof can be
reduced.
[0030] In particular, when the etching process for forming the
trench TC is performed, the side wall A of the first conductive
pattern 104a is protected by the protective pattern 108a,
minimizing or preventing damage caused by the etching process.
After the trench TC is formed, to compensate for potential damage
to a surface of the semiconductor substrate 100 exposed in the
trench TC, an oxidation process can be carried out. As a result, a
bird's beak phenomenon, in which a thickness of the side wall B of
the gate insulating pattern 102a exposed in the trench TC is
increased, can occur. However, because a width of the gate
insulating pattern 102a is larger than that of the first conductive
pattern 104 by a thickness of the protective pattern 108a, despite
the occurrence of the bird's beak phenomenon, it is possible to
prevent or reduce an electrical property from being deteriorated.
In other words, in a case where the bird's beak phenomenon has
occurred, because the bird's beak is mostly generated at a region
on which the first conductive pattern 104a is not formed, it is
possible to prevent electrical property deterioration between the
gate insulating pattern 102a and the first conductive pattern
104a.
[0031] Referring to FIG. 1E, the trench TC is preferably filled
with a gap-fill insulating layer 110. The gap-fill insulating layer
110 can be formed on the semiconductor substrate 100 to fill the
trench TC with the gap-fill insulating layer. It is preferable to
form the gap-fill insulating layer 110 sufficiently so as to cover
the gate insulating pattern 106 completely with the gap-fill
insulating layer 110. The gap-fill insulating layer 110 is
preferably formed of an oxide layer. For example, the gap-fill
insulating layer can be formed of a SOD layer (spin on dielectric
layer) or a HDP layer (high density plasma layer), or by laminating
a SOD layer and a HDP layer.
[0032] Referring to FIG. 1F, a planarization process is preferably
performed to allow the first conductive pattern 104a to be exposed.
For example, a chemical mechanical polishing (CMP) process can be
performed as the planarization process. By performing the
planarization process, the gap-fill insulating layer (110 in FIG.
1E) remains only in the trench TC, and the gap-fill insulating
layer 110 remaining in the trench becomes an isolation layer
110a.
[0033] Referring to FIG. 1G, a height of the isolation layer 110a
is preferably reduced to adjust the EFH (effective field height).
In addition, the etching process can be further performed to allow
a central portion C of an upper portion of the isolation layer 110a
to become lower than an edge portion, and so wings W can be formed
at both edges of the upper portion of the isolation layer 110a. If
the wings W are formed at both edges of the upper portion of the
isolation layer 110a, it is possible to increase a coupling ratio
between the floating gate and the control gate.
[0034] Referring to FIG. 1H, the portion of the protective pattern
of 108a formed on the side walls of the first conductive pattern
104a above a surface of the isolation layer 110a is removed,
preferably by an etching process. A dry etching process or a wet
etching process can be performed as the etching process for
removing a portion of the protective pattern. Preferably, the wet
etching process is performed as the etching process. If the wet
etching process is performed, an etchant whose etching ratio to the
protective pattern 108a is higher than that to the first conductive
pattern 104a and the isolation layer 110a is utilized. For example,
phosphoric acid (H3PO4) solution can be utilized as the etchant in
the wet etching process. As a result, the protective layer 108a
above a surface of the isolation layer 110a is removed to expose
upper portions S of the side walls of the first conductive pattern
104a.
[0035] Referring to FIG. 1I, a dielectric layer 112 is preferably
formed on surfaces of the isolation layer 110a, the protective
layer 108a and the first conductive pattern 104a. The dielectric
layer 112 can be formed by laminating an oxide layer, a nitride
layer and an oxide layer. Subsequently, a second conductive layer
114 can be formed on the dielectric layer 112, for example, for
forming a control gate. The second conductive layer 114 can be
formed of a polysilicon layer. For example, the second conductive
layer can be formed of a doped polysilicon layer.
[0036] As described above, due to the protective pattern 108a, side
walls of the first conductive pattern 104a can be protected in an
etching process, which is one of the processes for forming a flash
memory device. In addition, the deterioration of electrical
property caused by a bird's beak generated on the gate insulating
pattern 102a can be inhibited by the protective pattern.
[0037] By forming a protective layer along surfaces of a first
conductive pattern and an exposed gate insulating layer, it is
possible to protect side walls of a first conductive pattern during
a subsequent etching process. In addition, since the gate
insulating layer is preferably formed such that a width of the gate
insulating pattern is larger than that of the first conductive
pattern, it is possible to compensate for a defect caused by the
excessive oxidation at both ends of the gate insulating layer
generated during the subsequent oxidation process. As a result,
deterioration of the electrical property of the semiconductor
memory device can be prevented or reduced, improving reliability of
the semiconductor memory device.
[0038] Although embodiments have been described with reference to a
number of illustrative embodiments thereof, it should be understood
that numerous other modifications and embodiments can be devised by
those skilled in the art that will fall within the spirit and scope
of the principles of this disclosure. More particularly, various
variations and modifications are possible in the component parts
and/or arrangements of the subject combination arrangement within
the scope of the disclosure, the drawings and the appended claims.
In addition to variations and modifications in the component parts
and/or arrangements, alternative uses will also be apparent to
those skilled in the art.
* * * * *