U.S. patent application number 13/076437 was filed with the patent office on 2011-07-21 for method for calibrating analog-to-digital converting circuits.
Invention is credited to Chien-Ming Chen, Chen-Yu Hsiao.
Application Number | 20110175760 13/076437 |
Document ID | / |
Family ID | 42195744 |
Filed Date | 2011-07-21 |
United States Patent
Application |
20110175760 |
Kind Code |
A1 |
Chen; Chien-Ming ; et
al. |
July 21, 2011 |
METHOD FOR CALIBRATING ANALOG-TO-DIGITAL CONVERTING CIRCUITS
Abstract
A method for calibrating at least one analog-to-digital
converting circuit includes: during a wafer level probe testing,
inputting at least one calibration signal provided by a wafer level
testing machine into the analog-to-digital converting circuit to
generate at least one digital signal; and calibrating the
analog-to-digital converting circuit according to at least the
digital signal. The analog-to-digital converting circuit is applied
to a video system or an audio system.
Inventors: |
Chen; Chien-Ming; (Hsin-Chu
City, TW) ; Hsiao; Chen-Yu; (Pingtung County,
TW) |
Family ID: |
42195744 |
Appl. No.: |
13/076437 |
Filed: |
March 31, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12487626 |
Jun 18, 2009 |
7940199 |
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13076437 |
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61117581 |
Nov 25, 2008 |
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Current U.S.
Class: |
341/120 |
Current CPC
Class: |
H03M 1/12 20130101; H03M
1/1028 20130101 |
Class at
Publication: |
341/120 |
International
Class: |
H03M 1/10 20060101
H03M001/10 |
Claims
1. A method for calibrating at least one analog-to-digital
converting circuit, comprising: during a wafer level probe testing,
inputting at least one calibration signal provided by a wafer level
testing machine into the analog-to-digital converting circuit to
generate at least one digital signal; and calibrating the
analog-to-digital converting circuit according to at least the
digital signal; wherein the analog-to-digital converting circuit is
applied to a video system or an audio system.
2. The method of claim 1, wherein the step of calibrating the
analog-to-digital converting circuit comprises: calibrating gain or
offset of the analog-to-digital converting circuit to compensate
non-ideal characteristic of the analog-to-digital converting
circuit.
3. The method of claim 2, wherein when calibrating the gain of the
analog-to-digital converting circuit, the inputting step comprises
inputting at least two calibration signals into the
analog-to-digital converting circuit to generate at least two
digital signals; and the calibrating step comprises calibrating the
gain of the analog-to-digital converting circuit according to the
digital signals.
4. The method of claim 1, wherein the analog-to-digital converting
circuit comprises a programmable gain amplifier, and the step of
calibrating the analog-to-digital converting circuit according to
at least the digital signal comprises: calibrating the programmable
gain amplifier according to the digital signal.
5. The method of claim 1, wherein the analog-to-digital converting
circuit comprises an adjustable analog-to-digital converter, and
the step of calibrating the analog-to-digital converting circuit
according to at least the digital signal comprises: calibrating the
adjustable analog-to-digital converter according to the digital
signal.
6. The method of claim 1, further comprising: storing calibration
result into a non-volatile storage device.
7. The method of claim 6, wherein the non-volatile storage device
is an electronic fuse (E-fuse) storage device.
8. The method of claim 6, wherein the non-volatile storage device
and the analog-to-digital converting circuit are formed on a same
substrate.
9. The method of claim 1, wherein the video system includes a TV
system, a digital TV system or a video player system.
10. A method for calibrating at least one analog-to-digital
converting circuit, comprising: during a chip level testing,
inputting at least one calibration signal provided by a chip level
testing machine into the analog-to-digital converting circuit to
generate at least one digital signal; and calibrating the
analog-to-digital converting circuit according to at least the
digital signal; wherein the analog-to-digital converting circuit is
applied to a video system or an audio system.
11. The method of claim 10, wherein the step of calibrating the
analog-to-digital converting circuit according to the digital
signal comprises: calibrating gain or offset of the
analog-to-digital converting circuit.
12. The method of claim 11, wherein when calibrating the gain of
the analog-to-digital converting circuit, the inputting step
comprises inputting at least two calibration signals into the
analog-to-digital converting circuit to generate a plurality of
digital signals; and the calibrating step comprises calibrating the
gain of the analog-to-digital converting circuit according to the
digital signals.
13. The method of claim 10, wherein the analog-to-digital
converting circuit comprises a programmable gain amplifier, and the
step of calibrating the analog-to-digital converting circuit
according to the digital signal comprises: calibrating gain or
offset of the programmable gain amplifier according to the digital
signal.
14. The method of claim 10, wherein the analog-to-digital
converting circuit comprises an adjustable analog-to-digital
converter, and the step of calibrating the analog-to-digital
converting circuit according to at least the digital signal
comprises: calibrating the adjustable analog-to-digital converter
according to the digital signal.
15. The method of claim 10, further comprising: storing calibration
results into a non-volatile storage device.
16. The method of claim 15, wherein the non-volatile storage device
is an electronic fuse (E-fuse) storage device.
17. The method of claim 15, wherein the non-volatile storage device
and the analog-to-digital converting circuit are formed on a same
substrate.
18. The method of claim 10, wherein the video system includes a TV
system, a digital TV system or a video player system.
19. A method for calibrating at least one analog-to-digital
converting circuit, comprising: during a wafer level probe testing,
inputting at least two calibration signals into the
analog-to-digital converting circuit to generate at least two
digital signals; and calibrating gain of the analog-to-digital
converting circuit according to the digital signals.
20. A method for calibrating at least one analog-to-digital
converting circuit, comprising: during a chip level testing,
inputting at least two calibration signals into the
analog-to-digital converting circuit to generate at least two
digital signals; and calibrating gain of the analog-to-digital
converting circuit according to the digital signals.
Description
Cross Reference To Related Applications
[0001] This continuation application claims the benefit of
co-pending U.S. application No. 12/487,626 (filed on Jun. 18,
2009), which claims the benefit of U.S. provisional application No.
61/117,581 (filed on Nov. 25, 2008). The entire content of the
related applications is incorporated herein by reference.
BACKGROUND
[0002] The present invention relates to a method for calibrating
analog-to-digital converting circuits, and more particularly, to a
method for calibrating analog-to-digital converting circuits in a
wafer level probe testing process or a chip level testing
process.
[0003] A video system has three channels, respectively known as red
channel, green channel and blue channel. Each of the channels
includes an analog-to-digital converter (ADC), and the channels are
used, respectively, to receive red, green and blue signals and
perform analog-to-digital converting operations on the red, green
and blue signals to generate red, green and blue digital codes.
[0004] Theoretically, the ADCs in the red, green and blue channels
should output the same digital codes when receiving input signals
with the same analog color level. However, due to semiconductor
process variations, the ADCs in different channels may require
different gains to output the same digital codes. Therefore, the
gains of the ADCs need to be calibrated. Generally, this
calibration step proceeds in a production line by a machine that is
dedicated for the calibration; that is, the calibration proceeds in
a system level. Therefore, large amounts of manpower and time are
required, and cost of the production line is increased.
SUMMARY OF THE INVENTION
[0005] It is therefore an objective of the present invention to
provide a method for calibrating analog-to-digital converting
circuits in a wafer level probe testing or a chip level testing, to
solve the above-mentioned problems.
[0006] According to a first aspect of the present invention, a
method for calibrating at least one analog-to-digital converting
circuit is disclosed. The method includes: during a wafer level
probe testing, inputting at least one calibration signal provided
by a wafer level testing machine into the analog-to-digital
converting circuit to generate at least one digital signal; and
calibrating the analog-to-digital converting circuit according to
at least the digital signal. The analog-to-digital converting
circuit is applied to a video system or an audio system.
[0007] According to a second aspect of the present invention, a
method for calibrating at least one analog-to-digital converting
circuit is disclosed. The method includes: during a chip level
testing, inputting at least one calibration signal provided by a
chip level testing machine into the analog-to-digital converting
circuit to generate at least one digital signal; and calibrating
the analog-to-digital converting circuit according to at least the
digital signal; wherein the analog-to-digital converting circuit is
applied to a video system or an audio system.
[0008] According to a third aspect of the present invention, a
method for calibrating at least one analog-to-digital converting
circuit is disclosed. The method includes: during a wafer level
probe testing, inputting at least two calibration signals into the
analog-to-digital converting circuit to generate at least two
digital signals; and calibrating gain of the analog-to-digital
converting circuit according to the digital signals.
[0009] According to a fourth aspect of the present invention, a
method for calibrating at least one analog-to-digital converting
circuit is disclosed. The method includes: during a chip level
testing, inputting at least two calibration signals into the
analog-to-digital converting circuit to generate at least two
digital signals; and calibrating gain of the analog-to-digital
converting circuit according to the digital signals.
[0010] According to embodiments of the present invention, the
calibration step is integrated with the wafer level probe testing
or the chip level testing. Because a voltage level of the
calibration signal provided by the machine utilized for the wafer
level probe testing or the chip level testing has less variation,
the calibration result are precise. In addition, because the
calibration step is in the wafer level or the chip level, rather
than in the system level, the cost of the production line can also
be decreased.
[0011] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 is a diagram illustrating a video system according to
one embodiment of the present invention.
[0013] FIG. 2 is a diagram illustrating a flowchart of calibrating
the analog-to-digital converting circuits according to one
embodiment of the present invention.
[0014] FIG. 3 is a diagram illustrating the E-fuse storage device
according to one embodiment of the present invention.
[0015] FIG. 4A is a diagram illustrating a video system according
to another embodiment of the present invention.
[0016] FIG. 4B is a diagram illustrating a video system according
to another embodiment of the present invention.
[0017] FIG. 5 is a diagram illustrating a flowchart of calibrating
the analog-to-digital converting circuits according to another
embodiment of the present invention.
DETAILED DESCRIPTION
[0018] Certain terms are used throughout the following description
and claims to refer to particular system components. As one skilled
in the art will appreciate, manufacturers may refer to a component
by different names. This document does not intend to distinguish
between components that differ in name but not function. In the
following discussion and in the claims, the terms "including" and
"comprising" are used in an open-ended fashion, and thus should be
interpreted to mean "including, but not limited to . . . " The
terms "couple" and "couples" are intended to mean either an
indirect or a direct electrical connection. Thus, if a first device
couples to a second device, that connection may be through a direct
electrical connection, or through an indirect electrical connection
via other devices and connections.
[0019] Please refer to FIG. 1. FIG. 1 is a diagram illustrating a
video system 100 according to one embodiment of the present
invention. The video system (such as a TV system, a digital TV
system or a video player system) 100 includes three
analog-to-digital converting circuits 110, 120 and 130, where the
analog-to-digital converting circuit 110 includes two input nodes
116a and 116b, a programmable gain amplifier (PGA) 112 and an
adjustable analog-to-digital converter (ADC) 114, the
analog-to-digital converting circuit 120 includes two input nodes
126a and 126b, a PGA 122 and an adjustable ADC 124, and the
analog-to-digital converting circuit 130 includes two input nodes
136a and 136b, a PGA 132 and an adjustable ADC 134. In addition,
the analog-to-digital converting circuits 110, 120 and 130 are
positioned in red, green and blue channels of the video system,
respectively, and each analog-to-digital converting circuit is used
for receiving an input analog signal to generate corresponding
digital codes.
[0020] Please refer to FIG. 1 and FIG. 2 together. FIG. 2 is a
diagram illustrating a flowchart of calibrating the
analog-to-digital converting circuits 110, 120 and 130 according to
one embodiment of the present invention. Please note that, provided
the result is substantially the same, the steps are not limited to
be executed according to the exact order shown in FIG. 2, and other
steps may be inserted between two successive steps of the flow
chart. Referring to the flowchart shown in FIG. 2, a flow of
calibrating the analog-to-digital converting circuits 110, 120 and
130 is described as follows:
[0021] In Step 200, the calibration starts; the input nodes of the
analog-to-digital converting circuits 110, 120 and 130 are coupled
to the pads 102_1-102_6. The pads 102_1-102_6 are conventionally
utilized to receive wafer level probe testing signals or chip level
testing signals. In one embodiment where the calibration process is
integrated with the wafer level probe testing process, the pads
102_1-102_6 not only receive wafer level probe testing signals for
testing the performance of the wafer but also receive calibration
signals for calibrating the analog-to-digital converting circuits
110, 120 and 130. Similarly, in another embodiment where the
calibration process is integrated with the chip level testing
process, the pads 102_1-102_6 not only receive chip level testing
signals for testing the performance of the IC but also receive
calibration signals for calibrating the analog-to-digital
converting circuits 110, 120 and 130.
[0022] In Step 202, during the wafer level probe testing or the
chip level testing, a first calibration signal V+ is inputted into
the analog-to-digital converting circuits 110, 120 and 130 via the
pads 102_1, 102_3 and 102_5 to generate first digital signals C1,
C2 and C3, respectively; and then in Step 203, a second calibration
signal V- is inputted into the analog-to-digital converting
circuits 110, 120 and 130 via the pads 102_2, 102_4 and 102_6 to
generate second digital signals C1', C2' and C3', respectively. It
should be noted that although two input nodes and two pads are
illustrated for each analog-to-digital converting circuit to
receive input signals, it is not meant to be a limitation of the
present invention. For example, one input node with a switching
circuit (or a multiplexer) coupled between the pads and the input
node may be adopted as shown in FIG. 4A. FIG. 4A is a diagram
illustrating a video system 200 according to another embodiment of
the present invention. As a person skilled in this art can
understand the operations of the video system 200 after reading the
disclosure about the video system 100, further descriptions are
therefore omitted here. Moreover, one input node with one pad is
also feasible; please refer to FIG. 4B, the pad may receive the
first calibration signal V+ and the second calibration signal V-
sequentially. In one embodiment, the first calibration signal V+
and the second calibration signal V- is a differential pair.
However, as long as two different voltage signals are applied as
the first calibration signal and the second calibration signal,
substantially the same function can be achieved; that is, obtaining
two sets of digital signals C1, C2 and C3, and C1', C2' and C3'.
These modifications all fall within the scope of the present
invention.
[0023] Then, in Step 204, the analog-to-digital transfer functions
of the analog-to-digital converting circuits 110, 120 and 130 are
calibrated. Gains of the analog-to-digital converting circuits 110,
120 and 130 are determined based on the first digital signals C1,
C2 and C3 and the second digital signals C1', C2' and C3'. The
calibration amount for compensating the non-ideal characteristic of
each analog-to-digital converting circuit is then determined. In
one embodiment, the gains of the analog-to-digital converting
circuits 110, 120 and 130 are calibrated by calibrating gains of
the PGAs 112, 122 and 132. In another embodiment, the gains of the
analog-to-digital converting circuits 110, 120 and 130 are
calibrated by calibrating gains of the ADCs 114, 124 and 134.
[0024] Please note Steps 202-204 can be performed on the
analog-to-digital converting circuits 110, 120 and 130
simultaneously or sequentially. In other words, the
analog-to-digital converting circuits 110, 120 and 130 can be
calibrated simultaneously, or the analog-to-digital converting
circuits 110 can be calibrated first, and the analog-to-digital
converting circuits 120 and 130 can be calibrated after the
analog-to-digital converting circuit 110 finishes calibration.
[0025] In Step 206, the calibration result such as gains of the
PGAs 112, 122 and 132 determined in Step 204 are stored in a
non-volatile storage device such as an electronic fuse (E-fuse)
storage device 300 shown in FIG. 3. Finally, the flow enters Step
208 to finish the calibration. In this way, when the
analog-to-digital converting circuits 110, 120 and 130 function,
PGAs 112, 122 and 132 read the calibrated gains from the storage
device 300, thereby produce calibrated digital codes. Since the
calibrated gains are stored in the non-volatile storage device, the
calibration process can only be performed one time before the chip
enters the production line.
[0026] FIG. 3 is a diagram illustrating the E-fuse storage device
300 according to one embodiment of the present invention. E-fuse
storage device 300 includes two pads 302_1 and 302_2, a multiplexer
310, and three E-fuse units 320, 322 and 324. The gains of the PGAs
112, 122 and 132 determined in Step 204 are stored in the E-fuse
units 320, 322 and 324, respectively, via the pads 302_1 and 302_2
and the multiplexer 310 by using a high voltage HV and/or a low
voltage LV. The E-fuse storage device 300 may be a separate device,
or the E-fuse storage device 300 and the analog-to-digital
converting circuits 110, 120 and 130 may be formed on the same
substrate.
[0027] However, the present invention is not limited to store the
gains of the PGAs 112, 122 and 132 in the E-fuse storage device
300; other storage devices, such as poly-fuse, metal trim and ROM,
can also be utilized in Step 206.
[0028] The wafer level probe testing is a process before a die is
packaged, and the chip level testing is a process after packaging
but before the chip is used in the video system. For simplicity,
both the wafer level probe testing and the chip level testing are
processes performed before the chip enters the production line of
the video system such as a TV or a DVD player.
[0029] When the calibration signals V+ and V- are provided by the
wafer level probe testing machine or the chip level testing
machine, voltage levels of the calibration signals V+ and V- are
carefully adjusted and are highly precise. Therefore, the gains of
the analog-to-digital converting circuits 110, 120 and 130 can be
accurately determined. In addition, the analog-to-digital
converting circuits 110, 120 and 130 are coupled to the E-fuse
units 320, 322 and 324, respectively, and the gains of the
analog-to-digital converting circuits 110, 120 and 130 are
permanently set. Therefore, the gain calibration steps may not need
to be performed whenever the video system is turned on.
[0030] It is noted that, in Step 204 shown in FIG. 2, gains of the
PGAs 112, 122 and 132 are calibrated, and in FIG. 3, the E-fuse
units 320, 322 and 324 are coupled to the PGAs 112, 122 and 132,
respectively. However, in other embodiments of the present
invention, gains of the ADCs 114, 124 and 134 may be calibrated;
or, gains of the PGA and ADC are both calculated, and the E-fuse
units 320, 322 and 324 are coupled to the PGAs and ADCs.
[0031] The above-mentioned embodiments describe how to calibrate
the gains of the analog-to-digital converting circuits 110, 120 and
130. However, as a person with ordinary skill in the art would
appreciate, the above-mentioned structures and flow chart could
extend to calibrate the offsets of the analog-to-digital converting
circuits 110, 120 and 130 after some modifications. In this
embodiment, one calibration signal is required, and the calibration
flow chart shown in FIG. 5 is as follows.
[0032] In Step 500, the calibration starts; the input nodes 116a
(or 116), 126a (or 126), and 136a (or 136) of the analog-to-digital
converting circuits 110, 120 and 130 are coupled to the pads 102_1,
102_3, and 102_5.
[0033] In Step 502, during the wafer level probe testing or the
chip level testing, a calibration signal is inputted into the
analog-to-digital converting circuits 110, 120 and 130 via the pads
to generate digital signals C1, C2 and C3, respectively. In one
embodiment, the calibration signal corresponds to the middle point
of the input dynamic range of the analog-to-digital converting
circuits 110, 120 and 130.
[0034] Then, in Step 504, the offsets of the analog-to-digital
converting circuits 110, 120 and 130 are determined based on the
digital signals C1, C2 and C3. The calibration amounts are
determined by making the digital signals C1, C2 and C3 be the
same
[0035] In Step 506, the calibration results determined in Step 504
are stored in a non-volatile storage device such as an electronic
fuse (E-fuse) storage device 300 shown in FIG. 3. Finally, the flow
enters Step 508 to finish the calibration. In this way, when the
analog-to-digital converting circuits 110, 120 and 130 function,
the calibrated offsets are read from the storage device 300,
thereby produce calibrated digital codes. Since the calibrated
offsets are stored in the non-volatile storage device, the
calibration process can only be performed one time before the chip
enters the production line.
[0036] Briefly summarized, in the calibration method of the present
invention, the calibration step is performed during the wafer level
probe testing or the chip level testing, and the calibrated gains
or offsets of the analog-to-digital converting circuits are stored
in a non-volatile storage device. There are at least three
advantages of this method: first, because a voltage level of the
calibration signal provided in the wafer level probe testing or the
chip level testing has less variation, the calibrated gains/offsets
of the analog-to-digital converting circuits are more precise.
Second, because the calibrated gains/offsets are stored in the
non-volatile storage device, the calibration steps may not need to
be performed whenever the video system is turned on. Third, the
calibration step is in the wafer level or the chip level, so the
cost of the production line can also be decreased.
[0037] Please note that the present invention is not limited to
calibrate a video system having three (R/G/B) channels. The
above-mentioned calibration process can be applied to calibrate
only one of (or part of) the analog-to-digital converting circuits
110, 120 and 130, and may also be applied to an audio system. An
audio system may comprise an analog-to-digital converting circuit
for converting an analog audio input signal into a corresponding
digital code, where the analog-to-digital converting circuit may
comprise a PGA and an ADC. During the wafer level probe testing or
chip level probe testing, the calibration signal(s) is inputted
into the analog-to-digital converting circuit to generate digital
signal(s), and gain or offset of the analog-to-digital converting
circuit is then calibrated according to the digital signal(s). When
an audio signal is split into a left-channel signal and a
right-channel signal before inputted to an audio system, however,
the audio system may comprise two analog-to-digital converting
circuits respectively for converting the left-channel signal and
the right-channel signal into corresponding digital codes, where
each analog-to-digital converting circuit may comprise a PGA and an
ADC. Similarly, the calibration process can be utilized to
calibrate gains or offsets of the analog-to-digital converting
circuits by inputting calibration signal(s) into the
analog-to-digital converting circuits during wafer level probe
testing process or chip level testing process, and the calibration
results can be stored in a non-volatile storage device such as an
E-fuse device.
[0038] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *