U.S. patent application number 12/689444 was filed with the patent office on 2011-07-21 for gamma voltage generation circuit.
This patent application is currently assigned to HIMAX TECHNOLOGIES LIMITED. Invention is credited to Meng-Tse Weng.
Application Number | 20110175663 12/689444 |
Document ID | / |
Family ID | 44202414 |
Filed Date | 2011-07-21 |
United States Patent
Application |
20110175663 |
Kind Code |
A1 |
Weng; Meng-Tse |
July 21, 2011 |
GAMMA VOLTAGE GENERATION CIRCUIT
Abstract
A gamma voltage generation circuit is provided. An offset
voltage generator generates a first offset voltage by dividing a
voltage difference between a first input voltage and a second input
voltage based on a first code. A first voltage shifting circuit of
a voltage level shifter shifts down a first reference voltage by
the first offset voltage to output a first level-shifted voltage. A
second voltage shifting circuit of the voltage level shifter shifts
down a second reference voltage by the first offset voltage to
output a second level-shifted voltage. Each of resistors of a
resistor string outputs one of the gamma voltages. A first end and
a second end of the resistor string are respectively coupled to a
first output terminal and a second output terminal of the voltage
level shifter.
Inventors: |
Weng; Meng-Tse; (Tainan
County, TW) |
Assignee: |
HIMAX TECHNOLOGIES LIMITED
Tainan County
TW
|
Family ID: |
44202414 |
Appl. No.: |
12/689444 |
Filed: |
January 19, 2010 |
Current U.S.
Class: |
327/333 |
Current CPC
Class: |
H03M 1/664 20130101;
H03M 1/765 20130101; H03M 1/68 20130101; H03M 1/0682 20130101 |
Class at
Publication: |
327/333 |
International
Class: |
H03L 5/00 20060101
H03L005/00 |
Claims
1. A gamma voltage generation circuit, configured to generate a
plurality of gamma voltages, the gamma voltage generation circuit
comprising: an offset voltage generator, generating a first offset
voltage by dividing a voltage difference between a first input
voltage and a second input voltage based on a first code; a voltage
level shifter, coupled to the offset voltage generator and
comprising: a first voltage shifting circuit, coupled to the offset
voltage generator, shifting down a first reference voltage by the
first offset voltage to output a first level-shifted voltage; and a
second voltage shifting circuit, coupled to the offset voltage
generator, shifting down a second reference voltage by the first
offset voltage to output a second level-shifted voltage; and a
resistor string, comprising a plurality of resistors connected in
series, each of the resistors outputting one of the gamma voltages,
wherein a first end of the resistor string is coupled to an output
terminal of the voltage level shifter, and a second end of the
resistor string is coupled to an output terminal of the voltage
level shifter; wherein the offset voltage generator comprises: a
digital-to-analog converter, generating a first divided voltage by
dividing the voltage difference between the first input voltage and
the second input voltage according to the first code; and a first
voltage divider, coupled to the digital-to-analog converter,
dividing the first divided voltage to generate the first offset
voltage.
2. The gamma voltage generation circuit as claimed in claim 1,
wherein a voltage level of the output terminal of the voltage level
shifter is equal to the first level-shifted voltage, and a voltage
level of the output terminal of the voltage level shifter is equal
to the second level-shifted voltage.
3. (canceled)
4. The gamma voltage generation circuit as claimed in claim 1,
wherein the first voltage divider comprises a first resistor and a
second resistor, the first resistor and the second resistor are
connected in series, a first end of the first resistor is applied
with the first divided voltage, and a second end of the first
resistor is coupled to the second resistor and outputs the first
offset voltage.
5. The gamma voltage generation circuit as claimed in claim 1,
wherein the first voltage divider comprises a first resistor, a
second resistor, and an operational amplifier, the first resistor
and the second resistor are connected in series, a first end of the
first resistor is applied with the first divided voltage, a second
end of the first resistor is coupled to the second resistor and a
positive input terminal of the operational amplifier, and an output
terminal of the operational amplifier is coupled to a negative
input terminal of the operational amplifier and outputs the first
offset voltage.
6. The gamma voltage generation circuit as claimed in claim 1,
wherein the digital-to-analog converter further generates a second
divided voltage by dividing the voltage difference between the
first input voltage and the second input voltage based on a second
code, and the offset voltage generator further comprises a second
voltage divider, the voltage divider is coupled to the
digital-to-analog converter and divides the second divided voltage
to generate a second offset voltage.
7. The gamma voltage generation circuit as claimed in claim 6,
wherein the second voltage divider comprises a first resistor and a
second resistor, the first resistor and the second resistor are
connected in series, a first end of the first resistor is applied
with the second divided voltage, and a second end of the first
resistor is coupled to the second resistor and outputs the second
offset voltage.
8. The gamma voltage generation circuit as claimed in claim 6,
wherein the second voltage divider comprises a first resistor, a
second resistor, and an operational amplifier, the first resistor
and the second resistor are connected in series, a first end of the
first resistor is applied with the second divided voltage, a second
end of the first resistor is coupled to the second resistor and a
positive input terminal of the operational amplifier, and an output
terminal of the operational amplifier is coupled to a negative
input terminal of the operational amplifier and outputs the second
offset voltage.
9. The gamma voltage generation circuit as claimed in claim 1,
wherein the offset voltage generator divides the voltage difference
between the first input voltage and the second input voltage based
on a second code so as to generate a second offset voltage, and the
voltage level shifter further comprises: a third voltage shifting
circuit, coupled to the offset voltage generator, shifting down the
first reference voltage by the second offset voltage to output a
third level-shifted voltage; and a fourth voltage shifting circuit,
coupled to the offset voltage generator, shifting down the second
reference voltage by the second offset voltage to output a fourth
level-shifted voltage.
10. The gamma voltage generation circuit as claimed in claim 9,
wherein the voltage level shifter comprises a first switch and a
second switch, the first switch selects and outputs one of the
first level-shifted voltage and the third level-shifted voltage to
the first end of the resistor string according to a timing signal,
and second switch selects and outputs one of the second
level-shifted voltage and the fourth level-shifted voltage to the
second end of the resistor string according to the timing
signal.
11. The gamma voltage generation circuit as claimed in claim 10,
wherein the first switch is controlled by the timing signal to
interleavedly output the first level-shifted voltage and the third
level-shifted voltage, and the second switch is controlled by the
timing signal to interleavedly output the second level-shifted
voltage and the fourth level-shifted voltage.
12. The gamma voltage generation circuit as claimed in claim 9,
wherein each of the third voltage shifting circuit and fourth
voltage shifting circuit comprises an operational amplifier,
wherein a positive input terminal of the operational amplifier of
the third voltage shifting circuit is coupled to the first
reference voltage, a negative input terminal of the operational
amplifier of the third voltage shifting circuit is coupled to the
second offset voltage, and an output terminal of the operational
amplifier of the third voltage shifting circuit is coupled to the
negative input terminal of the operational amplifier of the third
voltage shifting circuit and outputs the third level-shifted
voltage, wherein a positive input terminal of the operational
amplifier of the fourth voltage shifting circuit is coupled to the
second reference voltage, a negative input terminal of the
operational amplifier of the fourth voltage shifting circuit is
coupled to the second offset voltage, and an output terminal of the
operational amplifier of the fourth voltage shifting circuit is
coupled to the negative input terminal of the operational amplifier
of the fourth voltage shifting circuit and outputs the fourth
level-shifted voltage.
13. The gamma voltage generation circuit as claimed in claim 1,
wherein each of the first voltage shifting circuit and the second
voltage shifting circuit comprises an operational amplifier,
wherein a positive input terminal of the operational amplifier of
the first voltage shifting circuit is coupled to the first
reference voltage, a negative input terminal of the operational
amplifier of the first voltage shifting circuit is coupled to the
first offset voltage, and an output terminal of the operational
amplifier of the first voltage shifting circuit is coupled to the
negative input terminal of the operational amplifier of the first
voltage shifting circuit and outputs the first level-shifted
voltage, wherein a positive input terminal of the operational
amplifier of the second voltage shifting circuit is coupled to the
second reference voltage, a negative input terminal of the
operational amplifier of the second voltage shifting circuit is
coupled to the first offset voltage, and an output terminal of the
operational amplifier of the second voltage shifting circuit is
coupled to the negative input terminal of the operational amplifier
of the second voltage shifting circuit and outputs the second
level-shifted voltage.
14. The gamma voltage generation circuit as claimed in claim 1,
further comprising a digital-to-analog converter, coupled to the
resistors of the resistor string, wherein the digital-to-analog
converter outputs one of the gamma voltages according to a data
code.
15. The gamma voltage generation circuit as claimed in claim 1,
wherein the first offset voltage is a positive voltage.
16. The gamma voltage generation circuit as claimed in claim 1,
wherein the first offset voltage is a negative voltage.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a gamma voltage generation
circuit. More particularly, the present invention relates to a
gamma voltage generation circuit capable of shifting gamma voltages
by a common voltage level.
[0003] 2. Description of Related Art
[0004] In a present information society, as information
communication media and various electronic display devices are
widely used in industrial apparatus or home appliances, the
electronic display devices become indispensable, and the electronic
display devices are continually updated to meet various demands of
the information society.
[0005] Generally, the electronic display devices display and
transmit various information to users. Namely, the electronic
device can convert electronic information signals into optical
information signals that can be visually recognized by the
users.
[0006] In a present display device or a system, for example, a
cathode-ray tube (CRT) or a liquid crystal display (LCD), a
relationship between an input voltage and a display output thereof
is not linear, and the relationship between the input voltage and
the display output can be described by a gamma curve. Regarding the
LCD, an output voltage (i.e. a gamma voltage) corresponding to each
of gray levels can be found according to the gamma curve. A LCD
panel can display a correct gray level according to the
corresponding gamma voltage, so that the LCD can correctly display
images.
[0007] To improve a display effect of the LCD, some of the LCD
panels can divide a single pixel into two sub-pixels. Common
voltage levels of the two sub-pixels are probably different due to
a circuit structure design. In this case, when a same gamma voltage
is output to the LCD panel, display effects of the two sub-pixels
can be different, so that a display quality thereof is influenced.
Referring to FIG. 1, a pixel is composed of two sub-pixels A and B.
The common voltage level of the sub-pixel A is VCOMA, and the
common voltage level of the sub-pixel B is VCOMB. A difference
.DELTA.V between the common voltage levels VCOMA and VCOMB causes a
phenomenon of color shift of the LCD panel, such that the display
quality of the LCD would be reduced.
SUMMARY OF THE INVENTION
[0008] The present invention is directed to a gamma voltage
generation circuit, which can shift gamma voltages by a common
voltage level.
[0009] The present invention provides a gamma voltage generation
circuit configured to generate a plurality of gamma voltages. The
gamma voltage generation circuit includes an offset voltage
generator, a voltage level shifter, and a resistor string. The
offset voltage generator generates a first offset voltage by
dividing a voltage difference between a first input voltage and a
second input voltage based on a first code.
[0010] The voltage level shifter is coupled to the offset voltage
generator, and includes a first voltage shifting circuit and a
second voltage shifting circuit. The first voltage shifting circuit
is coupled to the offset voltage generator, and shifts down a first
reference voltage by the first offset voltage to output a first
level-shifted voltage. The second voltage shifting circuit is
coupled to the offset voltage generator, and shifts down a second
reference voltage by the first offset voltage to output a second
level-shifted voltage. The resistor string includes a plurality of
resistors connected in series, and each of the resistors outputs
one of the gamma voltages, wherein a first end of the resistor
string is coupled to a first output terminal of the voltage level
shifter, and a second end of the resistor string is coupled to a
second output terminal of the voltage level shifter.
[0011] In an embodiment of the present invention, a voltage level
of the first output terminal of the voltage level shifter is equal
to the first level-shifted voltage, and a voltage level of the
second output terminal of the voltage level shifter is equal to the
second level-shifted voltage.
[0012] In an embodiment of the present invention, the offset
voltage generator includes a digital-to-analog converter (DAC) and
a first voltage divider. The DAC generates a first divided voltage
by dividing the voltage difference between the first input voltage
and the second input voltage according to the first code. The first
voltage divider is coupled to the DAC, and divides the first
divided voltage to generate the first offset voltage.
[0013] In an embodiment of the present invention, the first voltage
divider includes a first resistor and a second resistor, wherein
the first resistor and the second resistor are connected in series.
A first end of the first resistor is applied with the first divided
voltage, and a second end of the first resistor is coupled to the
second resistor and outputs the first offset voltage.
[0014] In an embodiment of the present invention, the first voltage
divider includes a first resistor, a second resistor, and an
operational amplifier. The first resistor and the second resistor
are connected in series. A first end of the first resistor is
applied with the first divided voltage, and a second end of the
first resistor is coupled to the second resistor and a positive
input terminal of the operational amplifier. An output terminal of
the operational amplifier is coupled to a negative input terminal
of the operational amplifier and outputs the first offset
voltage.
[0015] In an embodiment of the present invention, the DAC generates
a second divided voltage by dividing the voltage difference between
the first input voltage and the second input voltage based on a
second code, and the offset voltage generator further includes a
second voltage divider. The voltage divider is coupled to the DAC
and divides the second divided voltage to generate a second offset
voltage.
[0016] In an embodiment of the present invention, the second
voltage divider includes a first resistor and a second resistor,
wherein the first resistor and the second resistor are connected in
series. A first end of the first resistor is applied with the
second divided voltage, and a second end of the first resistor is
coupled to the second resistor and outputs the second offset
voltage.
[0017] In an embodiment of the present invention, the second
voltage divider includes a first resistor, a second resistor, and
an operational amplifier. The first resistor and the second
resistor are connected in series. A first end of the first resistor
is applied with the second divided voltage, and a second end of the
first resistor is coupled to the second resistor and a positive
input terminal of the operational amplifier. An output terminal of
the operational amplifier is coupled to a negative input terminal
of the operational amplifier and outputs the second offset
voltage.
[0018] In an embodiment of the present invention, the offset
voltage generator divides the voltage difference between the first
input voltage and the second input voltage based on a second code
so as to generate a second offset voltage, and the voltage level
shifter further includes a third voltage shifting circuit and a
fourth voltage shifting circuit. The third voltage shifting circuit
is coupled to the offset voltage generator, and shifts down the
first reference voltage by the second offset voltage to output a
third level-shifted voltage. The fourth voltage shifting circuit is
coupled to the offset voltage generator, and shifts down the second
reference voltage by the second offset voltage to output a fourth
level-shifted voltage.
[0019] In an embodiment of the present invention, the voltage level
shifter includes a first switch and a second switch. The first
switch selects and outputs one of the first level-shifted voltage
and the third level-shifted voltage to the first end of the
resistor string according to a timing signal. The second switch
selects and outputs one of the second level-shifted voltage and the
fourth level-shifted voltage to the second end of the resistor
string according to the timing signal.
[0020] In an embodiment of the present invention, the first switch
is controlled by the timing signal to interleavedly output the
first level-shifted voltage and the third level-shifted voltage.
The second switch is controlled by the timing signal to
interleavedly output the second level-shifted voltage and the
fourth level-shifted voltage.
[0021] In an embodiment of the present invention, each of the third
voltage shifting circuit and the fourth voltage shifting circuit
includes an operational amplifier. A positive input terminal of the
operational amplifier of the third voltage shifting circuit is
coupled to the first reference voltage, a negative input terminal
of the operational amplifier of the third voltage shifting circuit
is coupled to the second offset voltage, and an output terminal of
the operational amplifier of the third voltage shifting circuit is
coupled to the negative input terminal of the operational amplifier
of the third voltage shifting circuit and outputs the third
level-shifted voltage. A positive input terminal of the operational
amplifier of the fourth voltage shifting circuit is coupled to the
second reference voltage, a negative input terminal of the
operational amplifier of the fourth voltage shifting circuit s
coupled to the second offset voltage, and an output terminal of the
operational amplifier of the fourth voltage shifting circuit is
coupled to the negative input terminal of the operational amplifier
of the fourth voltage shifting circuit and outputs the fourth
level-shifted voltage.
[0022] In an embodiment of the present invention, each of the first
voltage shifting circuit and the second voltage shifting circuit
comprises an operational amplifier. A positive input terminal of
the operational amplifier of the first voltage shifting circuit is
coupled to the first reference voltage, a negative input terminal
of the operational amplifier of the first voltage shifting circuit
is coupled to the first offset voltage, and an output terminal of
the operational amplifier of the first voltage shifting circuit is
coupled to the negative input terminal of the operational amplifier
of the first voltage shifting circuit and outputs the first
level-shifted voltage. A positive input terminal of the operational
amplifier of the second voltage shifting circuit is coupled to the
second reference voltage, a negative input terminal of the
operational amplifier of the second voltage shifting circuit is
coupled to the first offset voltage, and an output terminal of the
operational amplifier of the second voltage shifting circuit is
coupled to the negative input terminal of the operational amplifier
of the second voltage shifting circuit and outputs the second
level-shifted voltage.
[0023] In an embodiment of the present invention, the gamma voltage
generation circuit further includes a DAC coupled to the resistors
of the resistor string, wherein the DAC outputs one of the gamma
voltages according to a data code.
[0024] In an embodiment of the present invention, the first offset
voltage is a positive voltage.
[0025] In an embodiment of the present invention, the first offset
voltage is a negative voltage.
[0026] According to the above descriptions, the gamma generation
circuit of the present invention can generate an offset voltage
according to the first code, and shifts the levels of the gamma
voltages according to the offset voltage. Moreover, the gamma
generation circuit can generate another offset voltage according to
the second code, and shifts the levels of the gamma voltages
according to the other offset voltage. Therefore, according to the
shifted gamma voltages, the pixels with different common voltage
levels may have a similar or a same display effect.
[0027] In order to make the aforementioned and other features and
advantages of the present invention comprehensible, several
exemplary embodiments accompanied with figures are described in
detail below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The accompanying drawings are included to provide a further
understanding of the invention, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the invention and, together with the description,
serve to explain the principles of the invention.
[0029] FIG. 1 illustrates a pixel having two sub-pixels biased by
different common voltage levels.
[0030] FIG. 2 is a circuit diagram illustrating a gamma voltage
generation circuit according to a first embodiment of the present
invention.
[0031] FIG. 3 is a circuit diagram illustrating a gamma voltage
generation circuit according to a second embodiment of the present
invention.
[0032] FIG. 4 is a circuit diagram illustrating a gamma voltage
generation circuit according to a third embodiment of the present
invention.
[0033] FIG. 5 is a timing diagram of signals of the gamma voltage
generation circuit in FIG. 4.
[0034] FIG. 6 is a circuit diagram illustrating a gamma voltage
generation circuit according to a fourth embodiment of the present
invention.
DESCRIPTION OF THE EMBODIMENTS
First Embodiment
[0035] FIG. 2 is a circuit diagram illustrating a gamma voltage
generation circuit according to a first embodiment of the present
invention. Referring to FIG. 2, the gamma voltage generation
circuit 100 includes an offset voltage generator 110, a voltage
level shifter 120, a resistor string 140, and a digital-to-analog
converter (DAC) 150. The offset voltage generator 110 includes a
DAC 112 and a first voltage divider 114. After the DAC 112 receives
an enable signal .DELTA.V_Enable, the DAC 112 generates a first
divided voltage .DELTA.V_IC by dividing a voltage difference
between a first input voltage VREF_H and a second input voltage
VREF_L according to a first code C1.
[0036] Further, assuming the first code C1 is 10 bits, i.e. the DAC
112 is 10 bits, the DAC 112 then divides the voltage difference
between the first input voltage VREF_H and the second input voltage
VREF_L into 1024 (i.e. 10 power of 2) equal parts, and outputs a
corresponding voltage level according to the first code C1. It
should be noticed that the higher the bit number of the DAC 112 is
(for example, 12 bits), the more equal parts the voltage difference
between the first input voltage VREF_H and the second input voltage
VREF_L is divided (for example, 4096 equal parts, i.e. 12 power of
2 equal parts). Conversely, the lower the bit number of the DAC 112
is (for example, 8 bits), the lesser equal parts the voltage
difference between the first input voltage VREF_H and the second
input voltage VREF_L is divided (for example, 256 equal parts, i.e.
8 power of 2 equal parts).
[0037] The first voltage divider 114 includes resistors Rx and Ry,
wherein the resistor Rx and the resistor Ry are connected in
series. A first end C of the resistor Rx is coupled to the DAC 112
and is applied with the first divided voltage .DELTA.V_IC, and a
second end D of the resistor Rx is coupled to the resistor Ry and
outputs a first offset voltage .DELTA.V to the voltage level
shifter 120, so that the voltage divider 114 can divide the first
divided voltage .DELTA.V_IC to generate the first offset voltage
.DELTA.V. A relationship among the first divided voltage
.DELTA.V_IC, the resistors Rx and Ry can be represented by a
following equation:
.DELTA. V = .DELTA. V_IC .times. Ry Rx + Ry ##EQU00001##
[0038] Where, Ry/(Rx+Ry) can be regarded as a voltage-dividing
ratio of the voltage divider 114. Therefore, the offset voltage
generator 110 can generate the first offset voltage .DELTA.V by
dividing the voltage difference between the first input voltage
VREF_H and the second input voltage VREF_L based on the first code
C1.
[0039] It should be noticed that the DAC 112 could be implemented
by a DAC with a low bit number as considering the cost thereof, so
that the first divided voltage .DELTA.V_IC may be not in accordance
with the ideal first offset voltage .DELTA.V, and thus, the ideal
first offset voltage .DELTA.V can be obtained based on the
voltage-dividing ratio of the voltage divider 114. For example, if
the ideal first offset voltage .DELTA.V is 1/100 of the first
divided voltage .DELTA.V_IC, a resistance ratio between the
resistors Rx and Ry can be designed to 99:1, i.e. the
voltage-dividing ratio of the voltage divider 114 is designed to be
1/100. According to the above description, the voltage difference
between the first input voltage VREF_H and the second input voltage
VREF_L is first divided by the DAC 112 (a first voltage-dividing),
and further divided by the voltage divider 114 (a second
voltage-dividing), so that the voltage difference between the first
input voltage VREF_H and the second input voltage VREF_L can be
finely divided to obtain the ideal first offset voltage
.DELTA.V.
[0040] In an embodiment of the present invention, the DAC 112, the
resistor string 140 and the DAC 150 is embedded in a source driver,
and the voltage divider 114 and the voltage level shifter 120 is
placed on a flexible printed board outside the source driver.
Therefore, in case of the long transmission path of the first
divided voltage .DELTA.V_IC, the first divided voltage .DELTA.V_IC
could be shifted due to the influence of noise. To reduce the
influence of noise during transmission of the first divided voltage
.DELTA.V_IC, the first divided voltage .DELTA.V_IC can be designed
to be higher than a voltage of the noise. Therefore, after the
voltage-dividing operation of the voltage divider 114, the first
divided voltage .DELTA.V_IC is divided to obtain the first offset
voltage .DELTA.V, and the noise can be reduced or eliminated due to
the voltage-dividing operation.
[0041] The voltage level shifter 120 includes a first voltage
shifting circuit 131 and a second voltage shifting circuit 132. The
first voltage shifting circuit 131 includes an operational
amplifier OP1 and resistors RA, RB, RC and RD, wherein resistances
of the resistors RA, RB, RC and RD are the same. A positive input
terminal of the operational amplifier OP1 is coupled to a first
reference voltage GMAH via the resistor RC, and is coupled to a
ground voltage via the resistor RD, a negative input terminal of
the operational amplifier OP1 is coupled to the first offset
voltage .DELTA.V via the resistor RA, and an output terminal of the
operational amplifier OP1 is coupled to the negative input terminal
of the operational amplifier OP1 via the resistor RB, and outputs a
first level-shifted voltage VH. The first level-shifted voltage VH
output by the first voltage shifting circuit 131 is equal to the
first reference voltage GMAH minus the first offset voltage
.DELTA.V, i.e. the first level-shifted voltage VH is equal to the
first reference voltage GMAH shifted down by the first offset
voltage .DELTA.V.
[0042] The second voltage shifting circuit 132 includes an
operational amplifier OP2 and resistors RE, RF, RG and RH, wherein
resistances of the resistors RE, RF, RG and RH are the same. A
positive input terminal of the operational amplifier OP2 is coupled
to a second reference voltage GMAL via the resistor RG, and is
coupled to the ground voltage via the resistor RH, a negative input
terminal of the operational amplifier OP2 is coupled to the first
offset voltage .DELTA.V via the resistor RE, and an output terminal
of the operational amplifier OP2 is coupled to the negative input
terminal of the operational amplifier OP2 via the resistor RF, and
outputs a second level-shifted voltage VL. The second level-shifted
voltage VL output by the second voltage shifting circuit 132 is
equal to the second reference voltage GMAL minus the first offset
voltage .DELTA.V, i.e. the second level-shifted voltage VL is equal
to the second reference voltage GMAL shifted down by the first
offset voltage .DELTA.V.
[0043] The voltage level shifter 120 takes the output terminal of
the operational amplifier OP1 as a first output terminal O1 to
output the first level-shifted voltage VH to a first end A of the
resistor string 140, and the voltage level shifter 120 takes the
output terminal of the operational amplifier OP2 as a second output
terminal O2 to output the second level-shifted voltage VL to a
second end B of the resistor string 140. The resistor string 140
includes a plurality of resistors R1-R64 connected in series, and
the resistors R1-R64 can divide the voltage difference between the
first level-shifted voltage VH and the second level-shifted voltage
VL to output a plurality of divided voltages, wherein the divided
voltages severe as gamma voltages V0-V63. The DAC 150 is coupled to
the resistors R1-R64 of the resistor string 140, and outputs one of
the gamma voltages V0-V63 provided by the resistors R1-R64 to serve
as a driving voltage according to a data code CA, so as to drive
liquid crystal to display a brightness of a corresponding gray
level. By such means, when common voltage levels of two pixels (or
sub pixels) are different, a level of each of the gamma voltages
can be shifted according to the first offset voltage .DELTA.V, so
that the two sub pixels can display similar or the same brightness
in case of the same gray level.
[0044] Moreover, since the first level-shifted voltage VH and the
second level-shifted voltage VL is generated based on the first
offset voltage .DELTA.V, and the first offset voltage .DELTA.V is
generated according to the first code C1, a plurality of gamma
curves for providing the gamma voltages V0-V63 could be generated
based on the first code C1. In addition, when the level of the
common voltages of different pixels (or sub-pixel) is different,
the reference voltages of different levels can be outputted to tune
the level of respective gamma voltages according to the first code
C1 so as to make the illumination of different pixels close or even
the same for the same grey level. The phenomenon of color shift of
the LCD panel would be avoided by applying proper gamma voltages to
the sub-pixels of the LCD panel. For example, in an LCD panel that
one pixel thereof has two sub-pixels applied by different common
voltages, when driving the two sub-pixels of the same pixel, one of
the sub-pixels may be driven by using one of the plurality of gamma
curves, and the other sub-pixel may be driven by using another one
of the plurality of gamma curves, such that the phenomenon of color
shift of the LCD panel would be avoided. Moreover, the phenomenon
of crosstalk of the display could be avoided by shifting the gamma
voltages by the proper offset voltages within corresponding
scanning periods of the display.
[0045] It should be noticed that since a level shifting reference
point of the gamma voltage can be a higher common voltage or a
lower common voltage of the two pixels, the first offset voltage
.DELTA.V can be a negative voltage or a positive voltage. Moreover,
the gamma voltage generation circuit of 6 bits (i.e. the number of
the resistors in the resistor string 140 is 6 power of 2) is
illustrated in FIG. 2, and if a gamma voltage generation circuit of
8 bits is used, the number of the resistors connected in series in
the resistor string 140 is increased to 256 (i.e. 8 power of 2).
The gamma voltage generation circuits with other bit numbers (for
example, 10 bits) can be deduced by analogy.
Second Embodiment
[0046] FIG. 3 is a circuit diagram illustrating a gamma voltage
generation circuit according to a second embodiment of the present
invention. Referring to FIG. 2 and FIG. 3, a difference there
between is that a first voltage divider 116 of the gamma voltage
generation circuit 200 further includes an operational amplifier
OP3. A positive input terminal of the operational amplifier OP3 is
coupled to the second end of the resistor Rx, and an output
terminal of the operational amplifier OP3 is coupled to a negative
terminal thereof, and outputs the first offset voltage .DELTA.V.
Wherein, the operational amplifier OP3 can be regarded as a voltage
follower, and after the resistors Rx and Ry divide the first
divided voltage .DELTA.V_IC, the divided voltage is output to serve
as the first offset voltage .DELTA.V. By such means, a load effect
between the offset voltage generator 110 and the voltage level
shifter 120 is reduced.
Third Embodiment
[0047] FIG. 4 is a circuit diagram illustrating a gamma voltage
generation circuit according to a third embodiment of the present
invention. Referring to FIG. 2 and FIG. 4, a difference there
between lies in an offset voltage generator 310 and a voltage level
shifter 320 of the gamma voltage generation circuit 300. The offset
voltage generator 310 includes a DAC 312, a first voltage divider
314a and a second voltage divider 314b. After the DAC 312 receives
the enable signal .DELTA.V_Enable, the DAC 312 generates a first
divided voltage .DELTA.V1_IC by dividing the voltage difference
between the first input voltage VREF_H and the second input voltage
VREF_L according to the first code C1, and generates a second
divided voltage .DELTA.V2_IC by dividing the voltage difference
between the first input voltage VREF_H and the second input voltage
VREF_L according to a second code C2.
[0048] The voltage dividers 314a and 314b are coupled to the DAC
312. The voltage divider 314a divides the first divided voltage
.DELTA.V1_IC to generate a first offset voltage .DELTA.Va, and the
voltage divider 314b divides the second divided voltage
.DELTA.V2_IC to generate a second offset voltage .DELTA.Vb. The
voltage divider 314a includes resistors Rx1 and Ry1, wherein a
first end C of the resistor Rx1 is applied with the first divided
voltage .DELTA.V1_IC, and a second end D of the resistor Rx1
outputs the first offset voltage .DELTA.Va. The voltage divider
314b includes resistors Rx2 and Ry2, wherein a first end E of the
resistor Rx2 is applied with the second divided voltage
.DELTA.V2_IC, and a second end F of the resistor Rx2 outputs the
second offset voltage .DELTA.Vb. Wherein, circuit structures and
operations of the voltage dividers 314a and 314b are similar to
those of the voltage divider 114, and therefore detailed
descriptions thereof are not repeated.
[0049] The voltage level shifter 320 includes a first voltage
shifting circuit 331, a second voltage shifting circuit 332, a
third voltage shifting circuit 333, a fourth voltage shifting
circuit 334, a first switch 340, and a second switch 342. The first
voltage shifting circuit 331 is coupled to the offset voltage
generator 310 for shifting down the first reference voltage GMAH by
the first offset voltage .DELTA.Va to output a first level-shifted
voltage VHa. The second voltage shifting circuit 332 is also
coupled to the offset voltage generator 310 for shifting down the
second reference voltage GMAL by the first offset voltage .DELTA.Va
to output a second level-shifted voltage VLa. The third voltage
shifting circuit 333 is coupled to the offset voltage generator 310
for shifting down the first reference voltage GMAH by the second
offset voltage .DELTA.Vb to output a third level-shifted voltage
VHb. The fourth voltage shifting circuit 334 is coupled to the
offset voltage generator 310 for shifting down the second reference
voltage GMAL by the second offset voltage .DELTA.Vb to output a
fourth level-shifted voltage VLb.
[0050] The first switch 340 selects and outputs the first
level-shifted voltage VHa or the third level-shifted voltage VHb to
the first end A of the resistor string 140 according to a timing
signal S1, and an output terminal of the first switch 340 serves as
an output terminal O3 of the voltage level shifter 320. The second
switch 342 selects and outputs the second level-shifted voltage VLa
or the fourth level-shifted voltage VLb to the second end B of the
resistor string 140 according to the timing signal S1, and an
output terminal of the second switch 342 serves as an output
terminal O4 of the voltage level shifter 320. Further, the first
switch 340 is controlled by the timing signal S1 to interleavedly
output the first level-shifted voltage VHa and the third
level-shifted voltage VHb to the first end A of the resistor string
140, and the second switch 342 is controlled by the timing signal
S1 to interleavedly output the second level-shifted voltage VLa and
the fourth level-shifted voltage VLb to the second end B of the
resistor string 140. In an embodiment, the gamma voltage generation
circuit 300 is used in a LCD, which operates at a frame rate of 120
hertz. As compared to a LCD operating at a frame rate of 60 hertz,
the LCD operating at a frame rate of 120 hertz has a shorter
display period for scanning the scan lines of the LCD. Since the
display period of the LCD operating at the frame rate of 120 hertz
may be too short, the voltage shifting circuits 331-334 may not
output the level-shifted voltage VHa, VHb, VLa and VLb at desired
voltage levels within a single display period. Therefore, the first
switch 340 and the second switch 342 interleavedly output
corresponding level-shifted voltages to the first end A and the
second B to shift the gamma voltages V0-V63 at desired voltage
levels. Please refer to FIG. 5. FIG. 5 is a timing diagram of
signals of the gamma voltage generation circuit 300. The parameter
n is a positive odd integer, such that the nth display period is
one of the odd display period of the LCD panel driven by the
voltage generation circuit 300 and that each of the (n-1).sup.th
and the (n+1).sup.th display periods is one of the even display
period of the LCD panel. The voltage shifting circuits 331-334
operate under the control of the signal TP1. In detail, within even
display periods and when the signal TP1 is high, the first voltage
shifting circuit 331 and the second voltage shifting circuit 332
settle the first level-shifted voltage VHa and the second
level-shifted voltage VLa, and the third voltage shifting circuit
333 and the fourth voltage shifting circuit 334 output the third
level-shifted voltage VHb and the fourth level-shifted voltage VLb
through the switches 340 and 342 to the resistor string 140. Within
odd display periods and when the signal TP1 is high, the first
voltage shifting circuit 331 and the second voltage shifting
circuit 332 output the first level-shifted voltage VHa and the
second level-shifted voltage VLa through the switches 340 and 342
to the resistor string 140, and the third voltage shifting circuit
333 and the fourth voltage shifting circuit 334 settle the third
level-shifted voltage VHb and the fourth level-shifted voltage VLb.
Therefore, the gamma voltages V0-V63 would be shifted at desired
voltage levels even if the display period is short.
[0051] The first voltage shifting circuit 331 includes an
operational amplifier OPa1 and resistors Ra, Rb, Rc, and Rd. The
second voltage shifting circuit 332 includes an operational
amplifier OPa2 and resistors Re, Rf, Rg, and Rh. The third voltage
shifting circuit 333 includes an operational amplifier OPb1 and
resistors Ri, Rj, Rk, and Rl. The fourth voltage shifting circuit
334 includes an operational amplifier Opb2 and resistors Rm, Rn,
Ro, and Rp. Wherein, circuit structures and operations of the first
voltage shifting circuit 331, the second voltage shifting circuit
332, the third voltage shifting circuit 333 and the fourth voltage
shifting circuit 334 are similar to that of the first voltage
shifting circuit 131 or the second voltage shifting circuit 132,
and therefore detailed descriptions thereof are not repeated.
[0052] Because the first offset voltage .DELTA.Va is generated
according to the first code C1, and the second offset voltage
.DELTA.Vb is generated according to the second code C2, a plurality
of gamma curves for providing the gamma voltages V0-V63 could be
generated based on the first code C1 and the second code C2. When
the level of the common voltages of different pixels (or sub-pixel)
is different, the reference voltages of different levels can be
outputted to tune the level of respective gamma voltages according
to the first code C1 so as to make the illumination of different
pixels close or even the same for the same grey level. The
phenomenon of color shift of the LCD panel would be avoided by
applying proper gamma voltages to the sub-pixels of the LCD panel.
For example, in an LCD panel that one pixel thereof has two
sub-pixels applied by different common voltages, when driving the
two sub-pixels of the same pixel, one of the sub-pixels may be
driven by using one of the plurality of gamma curves, and the other
sub-pixel may be driven by using another one of the plurality of
gamma curves, such that the phenomenon of color shift of the LCD
panel would be avoided. Moreover, the phenomenon of crosstalk of
the display could be avoided by shifting the gamma voltages by the
proper offset voltages within corresponding scanning periods of the
display.
Fourth Embodiment
[0053] FIG. 6 is a circuit diagram illustrating a gamma voltage
generation circuit according to a fourth embodiment of the present
invention. Referring to FIG. 4 and FIG. 6, a difference there
between is that a first voltage divider 316a of the gamma voltage
generation circuit 400 further includes an operational amplifier
OPa3, and a second voltage divider 316b of the gamma voltage
generation circuit 400 further includes an operational amplifier
OPb3. The operational amplifier OPa3 can be regarded as a voltage
follower, and after the resistors Rx1 and Ry1 divide the first
divided voltage .DELTA.V1_IC, the divided voltage is output to
serve as the first offset voltage .DELTA.Va. Similarly, the
operational amplifier OPb3 can be regarded as a voltage follower,
and after the resistors Rx2 and Ry2 divide the second divided
voltage .DELTA.V2_IC, the divided voltage is output to serve as the
second offset voltage .DELTA.Vb. By such means, a load effect
between the offset voltage generator 310 and the voltage level
shifter 320 is reduced.
[0054] In summary, the gamma generation circuit of the present
invention can generate an offset voltage according to the first
code, and shifts the levels of the gamma voltages according to the
offset voltage. Moreover, the gamma generation circuit can generate
another offset voltage according to the second code, and shifts the
levels of the gamma voltages according to the other offset voltage.
Therefore, according to the shifted gamma voltages, the pixels with
different common voltage levels may have a similar or a same
display effect. Moreover, the voltage follower is added to the
offset voltage generator, so as to reduce the load effect between
the offset voltage generator and the voltage level shifter.
[0055] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
present invention without departing from the scope or spirit of the
invention. In view of the foregoing, it is intended that the
present invention cover modifications and variations of this
invention provided they fall within the scope of the following
claims and their equivalents.
* * * * *