U.S. patent application number 13/052117 was filed with the patent office on 2011-07-14 for pixel structure.
Invention is credited to Shiun-Chang Jan, Han-Tu Lin.
Application Number | 20110169002 13/052117 |
Document ID | / |
Family ID | 40581676 |
Filed Date | 2011-07-14 |
United States Patent
Application |
20110169002 |
Kind Code |
A1 |
Jan; Shiun-Chang ; et
al. |
July 14, 2011 |
PIXEL STRUCTURE
Abstract
A pixel structure includes a substrate, a gate and a pixel
electrode that are disposed on the substrate, a patterned
dielectric layer and a patterned semiconductor layer disposed on
the gate, a source and a drain disposed on two sides of the
patterned semiconductor layer respectively, and a passivation layer
disposed on the source, the drain and the semiconductor layer. The
sidewall surfaces of the source and the drain are completely
covered with the passivation layer, but a part of the pixel
electrode is exposed by the passivation layer.
Inventors: |
Jan; Shiun-Chang; (Hsin-Chu,
TW) ; Lin; Han-Tu; (Hsin-Chu, TW) |
Family ID: |
40581676 |
Appl. No.: |
13/052117 |
Filed: |
March 21, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11951321 |
Dec 5, 2007 |
7935583 |
|
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13052117 |
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Current U.S.
Class: |
257/59 ;
257/E29.003 |
Current CPC
Class: |
H01L 27/1288 20130101;
H01L 27/1214 20130101 |
Class at
Publication: |
257/59 ;
257/E29.003 |
International
Class: |
H01L 29/04 20060101
H01L029/04 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 26, 2007 |
TW |
096140324 |
Claims
1. A pixel structure, comprising: a substrate; a gate and a pixel
electrode, disposed on the substrate; a patterned dielectric layer
and a patterned semiconductor layer, disposed on the gate; a source
and a drain disposed on two sides of the patterned semiconductor
layer respectively; and a passivation layer disposed on the source,
the drain and the semiconductor layer, the passivation layer
completely covering sidewall surfaces of the source and the drain
and exposing a part of the pixel electrode.
2. The pixel structure of claim 1, wherein the passivation layer is
at least 0.5 .mu.m wider than the source or the drain.
3. The pixel structure of claim 1, wherein the drain covers a part
of surface of the pixel electrode.
4. The pixel structure of claim 1, wherein the gate comprises a
transparent conductive layer and a metal layer disposed on the
transparent conductive layer.
5. The pixel structure of claim 1, further comprising a channel
passivation layer disposed on the semiconductor layer.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of application Ser. No.
11/951,321 filed Dec. 5, 2007, now allowed, which claims the
benefit of Taiwan Patent Application No. 096140324 filed on Oct.
26, 2007.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention provides a pixel structure and a
fabrication method thereof, and more particularly, to a pixel
structure and a fabrication method thereof utilizing a single
photomask in two different lithographic processes for defining
different patterns.
[0004] 2. Description of the Prior Art
[0005] Due to the continued development in technology, flat
displays have been applied to all kinds of information products,
especially for thin-film transistor liquid crystal displays
(TFT-LCDs) that are the most maturely developed. Because TFT-LCDs
have qualities of light weight, low power consumption and no
radiated pollution, they have been widely used in various portable
information products, such as notebooks, personal digital
assistants (PDAs), and etc. Furthermore, the TFT-LCD even has a
potential to replace the cathode ray tube (CRT) monitor gradually.
Pixel structures arranged as an array are main devices of the
TFT-LCD, which comprise electronic devices, such as TFTs,
capacitors, pads, and etc., for driving liquid crystal pixels in
the production of brilliant images.
[0006] A typical fabrication process for a pixel structure of a
conventional TFT-LCD has to perform five photolithography
processes, which means five photomasks are needed for defining the
patterns of the TFT. However, since the cost of photomasks
seriously influences the display fabrication costs, a new
fabrication process of the pixel structure by using four
photomasks, including a half-tone mask or a gray-tone mask, has
been researched in order to reduce the fabrication costs.
[0007] Referring to FIG. 1 through FIG. 6, FIG. 1 through FIG. 6
are schematic diagrams of a conventional fabrication process for
fabricating a pixel array by using four photomasks. As shown in
FIG. 1, first, a first conductive layer and a photoresist layer are
formed on a transparent substrate 10 in sequence, and then, a first
photolithography-etching process (PEP) is performed to form a gate
12 and a wire pattern 14.
[0008] Next, as shown in FIG. 2, an insulation layer 16, a
semiconductor layer 18, an N+ doped layer 20, a second conductive
layer 22 and a photoresist layer 24 are formed on the transparent
substrate 10 in sequence. Then, as shown in FIG. 3, a second
lithographic process is performed by using a half-tone mask 26. The
half-tone region 26a of the half-tone mask 26 is corresponding to a
predetermined channel pattern above the gate 12 so as to pattern
the photoresist layer 24.
[0009] With reference to FIG. 4, next, the patterned photoresist
layer 24 is utilized to be an etching mask, and a wet etching and a
dry etching are performed for the transparent substrate 10 in
sequence to remove a part of the semiconductor layer 18, the N+
doped layer 20 and the second conductive layer 22 so as to form a
semiconductor island 32, a source 28 and a drain 30. As shown in
FIG. 5, subsequently, a passivation layer 34 is deposited on the
transparent substrate 10, and then, a third PEP is performed to
form a contact hole 36 in the passivation layer 34 on the drain 30.
Finally, as shown in FIG. 6, a transparent conductive layer is
formed on the transparent substrate 10, and a fourth PEP is
performed to remove a part of the transparent conductive layer on
the semiconductor island 32 so as to form a pixel electrode 38. The
pixel electrode 38 is electrically connected to the drain 30
through the contact hole 36.
[0010] As mentioned above, the conventional fabrication process of
TFTs uses the half-tone mask during the second PEP process by
taking its half-tone region to define the channel pattern of the
TFT. Because the size of the channel pattern of the TFT is very
detailed and minute, the half-tone mask for defining the channel
pattern by its half-tone region has to be very accurate, whose
costs is very high that is twice the cost of normal photomask. In
addition, once a defect of the transference of the channel pattern
occurs during the second PEP by using a half-tone mask, it will
seriously affect the electric property of the TFT, which is hard to
be repaired, so as to affect the electrical performance of the
TFT.
[0011] Therefore, how to fabricate TFTs with lower-cost and
practicable processes is still an important issue for the
manufactures.
SUMMARY OF THE INVENTION
[0012] It is an objective of the present invention to provide a
fabrication method of a pixel structure so that the total amount of
photomasks of the fabrication process can be decreased by a method
of reusing a photomask so as to reduce the cost of fabrication
generated in the aforementioned method of the prior art.
[0013] According to the present invention, a fabrication method of
a pixel structure is provided. First, a substrate is provided, and
a gate and a pixel electrode are formed on the substrate. Next, a
dielectric layer and a semiconductor layer are formed on the
substrate in sequence, and then, the dielectric layer and the
semiconductor layer are patterned to form a patterned dielectric
layer and a patterned semiconductor layer on the gate.
Subsequently, a conductive layer is formed on the substrate, and
then, a first lithographic process is performed by utilizing a
photomask to pattern the conductive layer so as to form a source
and a drain on the patterned semiconductor layer, wherein the drain
is electrically connected to the pixel electrode. Next, a
passivation layer is formed on the substrate, and a second
lithographic process is performed by utilizing the photomask to
form a patterned passivation layer covering the source, the drain
and the semiconductor layer, which exposes a part of the pixel
electrode.
[0014] According to the present invention, a pixel structure is
further provided. The pixel structure comprises a substrate, a gate
and a pixel electrode that are disposed on the substrate, a
patterned dielectric layer and a patterned semiconductor layer
disposed on the gate, a source and a drain disposed on two sides of
the patterned semiconductor layer respectively, and a passivation
layer disposed on the source, the drain and the semiconductor
layer. The sidewall surfaces of the source and the drain are
completely covered with the passivation layer, but a part of the
pixel electrode is exposed by the passivation layer.
[0015] The present invention utilizes a single photomask in the
first and second lithographic process to define patterns of the
source/drain and the passivation layer respectively so that the
total amount of photomasks of the fabrication process can be
decreased. Therefore, the fabrication costs can be reduced.
Furthermore, according to the pixel structure fabricated by the
method of the present invention, the sidewall surfaces of the
source/drain are completely covered with the passivation layer so
that the source/drain can be protected from damage generated by
exposing the source/drain during the following assembly or
operation. Therefore, the stability and the operating efficiency of
the pixel structure can be effectively increased.
[0016] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] FIG. 1 through FIG. 6 are schematic diagrams of a
conventional fabrication process for fabricating a TFT by using
four photomasks.
[0018] FIG. 7 through FIG. 12 are schematic diagrams of the
fabrication process of a pixel structure according to a first
embodiment of the present invention.
[0019] FIG. 13 and FIG. 14 are schematic diagrams of the
fabrication process of a pixel structure according to a second
embodiment of the present invention.
[0020] FIG. 15 through FIG. 17 are schematic diagrams of the
fabrication process of a pixel structure according to a third
embodiment of the present invention.
DETAILED DESCRIPTION
[0021] FIG. 7 through FIG. 12 are schematic diagrams of the
fabrication process of a pixel structure according to a first
embodiment of the present invention. Referring to FIG. 7, first, a
substrate 200 is provided. The substrate 200 can be a transparent
substrate of glass, quartz or comprising other materials. Then, a
transparent conductive layer 202 and a metal layer 204 are formed
on the substrate 200 in sequence. Next, a PEP is performed to
pattern the transparent conductive layer 202 and the metal layer
204 so as to form a gate 206 of a TFT in a pixel region, a pixel
electrode stack layer 208, a capacitor bottom electrode 210 and a
pad stack layer 212 in a periphery circuit region. In other
embodiments of the present invention, the gate 206 and the pixel
electrode stack layer 208 or the pad stack layer 212 also can be
fabricated separately. For example, the metal layer 204 may be
formed first, and then, be patterned to form the gate 206. Next,
the transparent conductive layer 202 is deposited, and then, a PEP
is performed to form the pixel electrode stack layer 208.
[0022] With reference to FIG. 8, a dielectric layer, a
semiconductor layer and an N+ doped layer are successively
deposited on the substrate 200. The semiconductor layer can
comprise amorphous silicon layer. Then, another PEP is performed to
form a patterned dielectric layer 214, a patterned semiconductor
layer 216 and a patterned N+doped layer 218 so as to define a
pattern of a semiconductor island 220, wherein the patterned
dielectric layer 214 covers the surface of the gate 206, and forms
a capacitor dielectric layer 222 on the capacitor bottom electrode
210.
[0023] Next, as shown in FIG. 9, a conductive layer 226 with low
resistance and a photoresist layer 228 are blanket deposited on the
substrate 200. The conductive layer 226 may comprise metal
materials, and the photoresist layer may comprise inorganic
photosensitive materials. Then, a first lithographic process is
performed by utilizing a photomask 224 to pattern the photoresist
layer 228. The photomask 224 comprises a source/drain pattern 230
and a capacitor pattern 232. Subsequently, the patterned
photoresist layer 228 is regarded as an etching mask, and an
etching process is performed for the conductive layer 226 and the
N+ doped layer 218 to form a source 234, a drain 236 and a
capacitor top electrode 238 so as to fabricate a TFT 237 and a
capacitor 246 and expose a part of the semiconductor layer 216 to
be a channel of the TFT 237. The source 234 and the drain 236 are
disposed on two sides of the patterned semiconductor layer 216. In
addition, during the etching process, parts of the metal layer 204
of the pixel electrode stack layer 208 and the pad stack layer 212
are also removed at the same time so that a part of the transparent
conductive layer 202 is exposed to be a pixel electrode 208' and a
pad 212', and the drain 236 is electrically connected to the pixel
electrode 208'.
[0024] Referring to FIG. 10, the remnant patterned photoresist
layer 228 is removed, and then, a passivation layer 240 is formed
on the substrate 200. The passivation layer 240 can comprise
inorganic materials, such as silicon nitride or silicon oxide.
Next, as shown in FIG. 11, a second lithographic process is
performed by utilizing the photomask 224 to pattern the passivation
layer 240. The method of performing the second lithographic process
is to deposit a photoresist layer 242 on the substrate 200 first,
and then, the patterns of the photomask 224 are lithographed on the
photoresist layer 242. The patterned photoresist layer 242 has a
passivation-layer pattern 244 after a develop step. However, the
passivation-layer pattern 244 has to be larger than the electrical
devices underneath, such as the source 234, the drain 236 or the
capacitor top electrode 238 so as to provide protection, while the
photoresist layer 242 is patterned by utilizing the single
photomask 224 comprising the source/drain pattern 230 and the
capacitor pattern 232. Therefore, in the second lithographic
process, the process parameters have to be adjusted to make the
passivation-layer pattern 244 defined on the photoresist layer 242
be larger or wider than the source 234, the drain 236 and the
capacitor top electrode 238. The aforementioned process parameters
comprise a total exposure dose tuning, a pre-curing temperature of
the photoresist layer 242 and a developing time. For example, in
the lithographic process, if the total exposure dose tuning is
larger, the line width of the pattern formed on the photoresist
layer 242 will be narrower; if the pre-curing temperature is lower,
the line width exposed on the photoresist layer 242 also will be
narrower; and if the developing time is shorter, the patterned
photoresist layer 242 will have larger line width. Therefore, the
passivation-layer pattern 244 possessed by the photoresist layer
242 after developing is wider than the source 234, the drain 236
and the capacitor top electrode 238 through adjusting the condition
of the process parameters, as shown in FIG. 11. In addition, a step
of widening the patterned photoresist layer 242 also can be
performed by utilizing a reflow method.
[0025] Next, referring to FIG. 12, the patterned photoresist layer
242 is utilized to be an etching mask, and an etching process is
performed to remove a part of the passivation layer 240 not covered
with the photoresist layer 242 and expose a part of the pixel
electrode 208'. Subsequently, the remnant photoresist layer 242 is
removed, and the fabrication of the pixel structure 248 of the
present invention is finished. The patterned passivation layer 240
completely covers the devices of the TFT 237. For example, the
patterned passivation layer 240 covers the sidewall surfaces of the
source 234 and the drain 236, and is at least 0.5 .mu.m wider than
the source 234 and the drain 236, as the width difference w shown
in figure. However, in other embodiments of the present invention,
the passivation layer 240 having the pattern of the photomask 224
also can be reflowed to increase the pattern widths.
[0026] FIG. 13 and FIG. 14 are schematic diagrams of the
fabrication process of a pixel structure according to a second
embodiment of the present invention, wherein the numerals given to
most elements are the same as that in FIGS. 7-12. FIG. 13 is the
process following the FIG. 7. A dielectric layer 214, a
semiconductor layer 216 and an N+ doped layer 218 are deposited on
the substrate 200 in sequence after finishing the formation of the
gate 206, the pixel electrode stack layer 208, the capacitor bottom
electrode 210 and the pad stack layer 212. Next, a half-tone mask
250 or a gray-tone mask (not shown in figures) for defining the
patterns of the semiconductor island and the capacitor dielectric
layer is provided. The half-tone mask 250 comprises an opaque
region 250a and a half-tone region 250b, wherein the opaque region
250a is utilized to define the semiconductor island, and the
half-tone region 250b is corresponding to the pattern of the
capacitor dielectric layer. A PEP is performed by utilizing the
half-tone mask 250 to pattern the dielectric layer 214, the
semiconductor layer 216 and the N+ doped layer 218 so as to form a
semiconductor island 220 disposed on the dielectric layer 214 and
simultaneously expose the dielectric layer 214 on the capacitor
bottom electrode 210 to form the capacitor dielectric layer 222. In
other embodiments of the present invention, the step of patterning
the dielectric layer 214, the semiconductor layer 216 and the N+
doped layer 218 also can be fabricated through two photomasks with
different exposure energy.
[0027] Next, the method similar to that of the first embodiment
shown in FIGS. 10-12 is utilized to fabricate the source 234, the
drain 236 and the capacitor top electrode 238, disposed on the
semiconductor island 220, and the passivation layer 240 covering
the TFT 237 and the capacitor 246 through several deposition
processes combined with the first and second lithographic processes
by utilizing the photomask 224. As shown in FIG. 14, the pixel
structure 248 according to the second embodiment of the present
invention is finished.
[0028] In other embodiments of the present invention, an organic
photosensitive material also can be utilized to replace the
inorganic material of the passivation layer used in the
aforementioned embodiments so as to omit the step of fabricating
the photoresist layer during the second lithographic process. FIG.
15 through FIG. 17 are schematic diagrams of the fabrication
process of a pixel structure according to a third embodiment of the
present invention. First, as shown in FIG. 15, a gate 302 of a TFT,
a pixel electrode stack layer 304, a capacitor bottom electrode 306
and a pad stack layer 308 are fabricated on a transparent substrate
300, which are all stack-layer structures composed of a transparent
conductive layer 310 and a metal layer 312. Subsequently, a first
dielectric layer 314, a semiconductor layer 316 and a second
dielectric layer are formed on the transparent substrate 300 in
sequence, wherein the first dielectric layer 314 and the second
dielectric layer can comprise materials, such as silicon nitride,
silicon oxynitride or silicon oxide, etc. Next, a PEP is performed
by utilizing a half-tone mask 318 or a gray-tone mask (not shown in
figures) to pattern the first dielectric layer 314, the
semiconductor layer 316 and the second dielectric layer so that the
semiconductor layer 316 on the gate 302 is formed as a
semiconductor island, the first dielectric layer 314 is formed as a
gate insulation layer and a capacitor dielectric layer in the TFT,
and the remnant second dielectric layer is regarded as a channel
passivation layer 320 covering the channel region of the TFT. As
shown in FIG. 15, the half-tone mask 318 has an opaque region 318a
and a half-tone region 318b respectively corresponding to the
channel passivation layer 320 and the patterned semiconductor layer
316.
[0029] Next, with reference to FIG. 16, a conductive layer 322
comprising metal materials and a photoresist layer 324 comprising
inorganic photosensitive materials are formed on the transparent
substrate 300 in sequence. A first lithographic process is
performed by utilizing a photomask 326 comprising a source/drain
pattern 326a and a capacitor pattern 326b to pattern the
photoresist layer 324. Then, the patterned photoresist layer 324 is
utilized to be a mask, and a part of the conductive layer 322 and
the metal layer 312 under the conductive layer 322 not covered with
the photoresist layer 324 are etched to form the source/drain 328
and the capacitor top electrode 330. At the same time, a part of
the metal layer 312 of the pixel electrode stack layer 304 and the
pad stack layer 308 is removed.
[0030] Finally, as shown in FIG. 17, the patterned photoresist
layer 324 is removed, and then, an organic passivation layer 332
having photosensitivity is deposited on the transparent substrate
300. A second lithographic process is performed by utilizing the
photomask 326 to pattern the organic passivation layer 332. Because
the organic passivation layer 332 itself has the quality of
photosensitivity, it is not required to further fabricate a
photoresist layer on the organic passivation layer 332. The organic
passivation layer 332 can be directly exposed during the second
lithographic process so that the patterns of the photomask 326 are
lithographed and transferred on the organic passivation layer 332.
Then, the organic passivation layer 332 is patterned after a
develop step, and parts of the organic passivation layer 332
without the source/drain pattern 326a and the capacitor pattern
326b of the photomask 326 are removed. In the second lithographic
process, the pattern of the organic passivation layer 332 can be
patterned to be wider than the source/drain 328 and the capacitor
top electrode 330, such as at least 0.5 .mu.m wider, through
adjusting the process parameters, such as total exposure dose
tuning and developing time, etc., such that the passivation layer
332 covers the sidewall surfaces of the source/drain 328. Besides,
parts of the organic passivation layer 332 with the patterns of the
photomask 326 can be reflowed to widen the patterns of the organic
passivation layer 332 after developing. Accordingly, the
fabrication of a pixel structure 334 of the third embodiment of the
present invention is finished.
[0031] It is an advantage of the present invention that only a
single photomask is utilized during the first and second
lithographic processes to define patterns of the source/drain and
the passivation layer respectively so that the total amount of
photomasks of the fabrication process can be reduced. Furthermore,
in the aforementioned process according to the first embodiment of
the present invention, the half-tone mask or gray-tone mask is not
required so that the fabrication cost of the photomasks also can be
reduced. In addition, the passivation layer defined during the
second lithographic process completely covers the electrical
devices, such as source/drain and capacitor, so that the operating
efficiency of the pixel structure can be increased. Compared with
the prior art, the process of the present invention only requires
three photomasks for fabricating the pixel structure such that the
total amount of fabrication tools used in the whole fabrication
process can be reduced, saving raw materials and hardware
equipments. And also, the usages of the precise equipments, such as
half-tone mask, can be reduced to effectively increase the capacity
of production and the quality of the product. Therefore, the cost
of the whole product fabrication is reduced.
[0032] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *