U.S. patent application number 13/064082 was filed with the patent office on 2011-07-07 for mounting structures for integrated circuit modules.
Invention is credited to Soo-Kyung Kim, Ki-Hyun Ko, Sung-Joo Park, Young Yun.
Application Number | 20110163418 13/064082 |
Document ID | / |
Family ID | 39666969 |
Filed Date | 2011-07-07 |
United States Patent
Application |
20110163418 |
Kind Code |
A1 |
Park; Sung-Joo ; et
al. |
July 7, 2011 |
Mounting structures for integrated circuit modules
Abstract
A structure of an integrated circuit module includes a wiring
board, a plurality of integrated circuits and at least one
terminating resistance circuit. The wiring board has a mounting
region on at least one surface thereof. The plurality of integrated
circuits are mounted in the mounting region of the wiring board and
spaced from one another in a first direction. The at least one
terminating resistance circuit is arranged between at least two
adjacent integrated circuits, and coupled to an output of a last of
the plurality of integrated circuits.
Inventors: |
Park; Sung-Joo; (Anyang-si,
KR) ; Ko; Ki-Hyun; (Yongin-si, KR) ; Yun;
Young; (Yongin-si, KR) ; Kim; Soo-Kyung;
(Seoul, KR) |
Family ID: |
39666969 |
Appl. No.: |
13/064082 |
Filed: |
March 4, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12010138 |
Jan 22, 2008 |
7919841 |
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13064082 |
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Current U.S.
Class: |
257/536 ;
257/E27.009 |
Current CPC
Class: |
H05K 2201/10022
20130101; H05K 1/181 20130101; H05K 2201/10159 20130101; H05K
1/0246 20130101; H05K 2201/10522 20130101; H01L 2924/0002 20130101;
H01L 2924/0002 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/536 ;
257/E27.009 |
International
Class: |
H01L 27/02 20060101
H01L027/02 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 25, 2007 |
KR |
10-2007-0007720 |
Claims
1. An integrated circuit module structure comprising: a wiring
board having a mounting region on at least one surface, the
mounting region having a first mounting length in a first direction
and a first mounting width in a second direction; a plurality of
integrated circuits mounted within the mounting region of the
wiring board, the plurality of integrated circuits being spaced
from one another in the first direction; and a terminating
resistance circuit arranged in a space between two adjacent
integrated circuits, the terminating resistance circuit being
coupled to an output of a last integrated circuit among the
plurality of integrated circuits.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This nonprovisional U.S. patent application is a
Continuation application of, and claims priority under 35 U.S.C.
.sctn.120 to, U.S. application Ser. No. 12/010,138, filed on Jan.
22, 2008, which claims priority under 35 U.S.C. .sctn.119 to Korean
Patent Application no. 10-2007-0007720, filed on Jan. 25, 2007, the
entire contents of each of which are incorporated herein by
reference.
BACKGROUND
Description of the Related Art
[0002] An advanced portable terminal or personal computer may
require relatively high speed and/or high capacity main memories,
such as, dynamic random access memories. A memory module, capable
of functioning as a main memory of personal computer may be based
on a plurality of encapsulated memory chips mounted on a wiring
board such as a printed circuit board (PCB).
[0003] Operating speeds in related art memory modules may be
determined by input/output data and an operating frequency of
command and address signals. Command and address signals in a
memory device may handle a greater load as compared to input/output
data, and thus, a maximum operating frequency may be determined by
the structure of signal lines employed.
[0004] As operating speeds of related art memories increase, signal
line topology has changed to accommodate the higher speeds. A
relatively more advanced change is a daisy-chain type channel
configuration. A daisy-chain type channel configuration is a fly-by
type channel coupled with each load through a short-stub. In this
example, electrical characteristics of a signal line may be
improved by performing impedance matching using terminating
resistor(s).
[0005] FIG. 1 illustrates a conventional connection structure with
command/address lines in a fly-by structure. In FIG. 1, unit signal
lines L1 to L3 may be connected sequentially, and unit signal line
L3 and a unit signal line L4 may be connected to each other. Unit
signal line L5 may be coupled to a DRAM pin 20a. A terminating
resistance unit Rtt for impedance matching may be connected to a
last pin of the memory device.
[0006] As shown in FIG. 1, in a conventional fly-by (daisy-chain)
structure, the DRAMs may be connected in series and a terminating
resistor is positioned on the signal line. In this example, the
terminating resistance is located on an outer portion of memory
module. In disposing several passive devices on such an outer
portion of the memory module, the memory module may be weaker
against exterior impact.
[0007] FIGS. 2 and 3 illustrate a conventional double in-line
memory module (DIMM) utilizing the fly-by structure of FIG. 1, in
which a terminating resistance unit 30 is mounted on an edge
portion of a side port of a memory module. Referring to FIGS. 2 and
3, a plurality of DRAM packages 20 to 28 and a terminating
resistance unit 30 may be mounted on a wiring board 10. In FIG. 3,
the direction of the arrow indicates a channel connection structure
for FIG. 1. FIG. 3 depicts a sequential electrical connection of
the leftmost DRAM package 20 to the rightmost DRAM package 28. The
terminating resistance unit 30 may be coupled to pins of the DRAM
package 28. The wiring board 10 may be comprised of glassy epoxy
resin sheet having a rectangular shape. Connector pins for
connection with a mother board of an electrical system may be
formed as shown in a lower part of FIG. 2. The DRAM packages 20 to
28 each encapsulating a DRAM chip may be electrically connected to
the wiring board 10 individually through a plurality of leads
arrayed at a lower part thereof or through connection balls of a
ball grid array BGA. Each of DRAM packages 20 to 28 may have a
given width and length as shown in the drawing. The details of a
portion 12 where the terminating resistance unit 30 is located is
shown in FIG. 4.
[0008] As illustrated in FIGS. 1 to 4, devices such as the passive
device 32 or terminating resistance unit 30 may be located at an
outermost portion of the module when a terminating resistance unit
is disposed on the wiring board. As a result, terminating
resistance unit may be relatively weak, physically. Furthermore,
when the terminating resistance unit is open or short-circuited, a
module and/or electrical system employing the module may
malfunction. As a result, related art integrated circuit modules
are based on a structure including a terminating resistance unit
provided together with memory devices located at an edge portion of
the memory module. Such integrated circuit modules may have lower
fidelity and/or accuracy due to damage.
SUMMARY
[0009] Example embodiments relate to integrated circuit modules
such as a dynamic random access memories, etc., mounted on a wiring
board. For example, example embodiments relate to terminating
resistor layouts mounted together with semiconductor devices in an
integrated circuit module.
[0010] At least one example embodiment provides an integrated
circuit module structure capable of substantially reducing damage
based on errors in passive devices. At least one other example
embodiment provides a terminating resistor layout method and
integrated circuit module structure capable of reducing or
substantially reducing damage to terminating resistor mounted on
integrated circuit modules.
[0011] At least one other example embodiment provides a terminating
resistor layout structure and a terminating resistor layout method
thereof, which may suppress and/or prevent damage caused by dealing
error.
[0012] According to at least one example embodiment, an integrated
circuit module structure may include a wiring board having a
mounting region on at least one surface thereof. The mounting
region may be formed to have a mounting length in a first direction
and a mounting width in a second direction. A plurality of
integrated circuit packages may be mounted in the mounting region
of the wiring board and may be spaced from one another in the first
direction. A terminating resistance circuit may be disposed between
any two adjacent integrated circuit packages and may be coupled to
an output of a last integrated circuit package among the integrated
circuit packages.
[0013] At least one other example embodiment provides a structure
of integrated circuit module. In at least this example embodiment,
a board may have a mounting region on at least one surface. The
mounting region may have a first mounting length in a first
direction and a first mounting width in a second direction. A
plurality of integrated circuits may be mounted in the mounting
region of the wiring board. The plurality of integrated circuits
may be spaced from one another in the first direction. A
terminating resistance circuit may be arranged in a space between
two adjacent integrated circuits. The terminating resistance
circuit may be coupled to an output of a last integrated circuit
among the plurality of integrated circuits.
[0014] According to at least some example embodiments, the
integrated circuit packages may be a volatile memory device (e.g.,
DRAM or the like) and may have the same or substantially the same
dimension in the first and second directions. The wiring board may
be a multi-layer printed circuit board (PCB), and the integrated
circuit module may have a fly-by type electrical connection
structure.
[0015] At least one other example embodiment provides a method of
disposing a terminating resistance circuit for a memory module in
configuring the memory module by mounting a plurality of memory
devices on a wiring board. In an example embodiment of the method,
the terminating resistance circuit may be disposed on any one of a
plurality of regions between the plurality of memory devices,
except an edge region of the wiring board. The terminating
resistance circuit may be electrically coupled to an output of an
end device among the plurality of memory devices.
[0016] According to at least some example embodiments, the
integrated circuit module structure and/or the layout method
according to at least some example embodiments may reduce or
substantially reduce outer physical impact applicable to a
terminating resistance unit of the module and/or a handling damage,
thereby increasing accuracy and/or fidelity of the module.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Example embodiments will be apparent from the more
particular description of the example embodiments illustrated in
the accompanying drawings in which like reference characters refer
to the same parts throughout the different views, in which:
[0018] FIGS. 1 to 4 illustrate a structure of a conventional
integrated circuit module;
[0019] FIGS. 5 to 7 illustrate structures of integrated circuit
module according to example embodiments; and
[0020] FIGS. 8 and 9 illustrate a layout of a terminating
resistance circuit according to example embodiments.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0021] Various example embodiments of the present invention will
now be described more fully with reference to the accompanying
drawings in which some example embodiments of the invention are
shown. In the drawings, the thicknesses of layers and regions are
exaggerated for clarity.
[0022] Detailed illustrative embodiments of the present invention
are disclosed herein. However, specific structural and functional
details disclosed herein are merely representative for purposes of
describing example embodiments of the present invention. This
invention may, however, may be embodied in many alternate forms and
should not be construed as limited to only the embodiments set
forth herein.
[0023] Accordingly, while example embodiments of the invention are
capable of various modifications and alternative forms, embodiments
thereof are shown by way of example in the drawings and will herein
be described in detail. It should be understood, however, that
there is no intent to limit example embodiments of the invention to
the particular forms disclosed, but on the contrary, example
embodiments of the invention are to cover all modifications,
equivalents, and alternatives falling within the scope of the
invention. Like numbers refer to like elements throughout the
description of the figures.
[0024] It will be understood that, although the terms first,
second, etc. may be used herein to describe various elements, these
elements should not be limited by these terms. These terms are only
used to distinguish one element from another. For example, a first
element could be termed a second element, and, similarly, a second
element could be termed a first element, without departing from the
scope of example embodiments of the present invention. As used
herein, the term "and/or" includes any and all combinations of one
or more of the associated listed items.
[0025] It will be understood that when an element is referred to as
being "connected" or "coupled" to another element, it can be
directly connected or coupled to the other element or intervening
elements may be present. In contrast, when an element is referred
to as being "directly connected" or "directly coupled" to another
element, there are no intervening elements present. Other words
used to describe the relationship between elements should be
interpreted in a like fashion (e.g., "between" versus "directly
between", "adjacent" versus "directly adjacent", etc.).
[0026] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
example embodiments of the invention. As used herein, the singular
forms "a", "an" and "the" are intended to include the plural forms
as well, unless the context clearly indicates otherwise. It will be
further understood that the terms "comprises", "comprising,",
"includes" and/or "including", when used herein, specify the
presence of stated features, integers, steps, operations, elements,
and/or components, but do not preclude the presence or addition of
one or more other features, integers, steps, operations, elements,
components, and/or groups thereof.
[0027] It should also be noted that in some alternative
implementations, the functions/acts noted may occur out of the
order noted in the figures. For example, two figures shown in
succession may in fact be executed substantially concurrently or
may sometimes be executed in the reverse order, depending upon the
functionality/acts involved. FIGS. 5 to 7 illustrate a structure of
integrated circuit module according to an example embodiment. FIGS.
8 and 9 illustrate a layout of terminating resistance according to
example embodiments.
[0028] Example embodiments may include a terminating resistance
unit or circuit disposed in an internal region (e.g., between
memory devices), to reduce or substantially reduce damage resulting
from, for example, a dealing error on the terminating resistance
unit of the integrated circuit module.
[0029] Referring to FIGS. 5 and 6, an integrated circuit module may
include a wiring board 10 having a mounting region on at least one
surface thereof. The mounting region may have a first mounting
length in a first direction (also referred to as the length
direction) and a first mounting width in a second direction (also
referred to as the width direction). The length and width
directions ma be perpendicular to one another. The integrated
circuit module may further include a plurality of integrated
circuit packages 20-28 and a terminating resistance unit or circuit
33. The terminating resistance circuit may include a plurality of
passive devices such as resistors or the like.
[0030] As shown in FIG. 6, in the wiring board 10 having a mounting
region on at least one surface thereof, the plurality of integrated
circuit packages 20-28 may be disposed at a first distance from one
another in the first direction. In this example configuration, the
terminating resistance circuit 33 may be disposed between any two
adjacent integrated circuit packages 20-28. For example, the
terminating resistance circuit 33 may be arranged between the
circuit packages 27 and 28, and may be connected to an output of
the last or end integrated circuit package (e.g., 28 of FIG. 6).
According to at least this example embodiment, the terminating
resistance circuit 33 may be disposed between two adjacent
integrated circuit packages (e.g., DRAMs or the like), but may be
electrically coupled to the end integrated circuit package (e.g.,
28 of FIG. 6).
[0031] Each of the integrated circuit packages 20-28 may be a
volatile memory device (e.g., a DDR DRAM, or the like) and may have
the same or substantially the same dimensions in the first and/or
second directions. The wiring board 10 may be a multi-layer printed
circuit board, and the integrated circuit module may have a fly-by
type structure.
[0032] With reference to FIGS. 5 and 6, in arranging a passive
device such as terminating resistor between memory devices, the
passive device may be better protected from an external, outer
impact and/or handling damage. The terminating resistances may have
a lower step than that of the memory device packages, and thus, may
be better protected from physical impact and/or static electricity.
According to at least some example embodiments, the integrated
circuit module may have the connection structure of "DRAM.fwdarw. .
. . .fwdarw.DRAM.fwdarw.Terminating Resistor," and be more
physically durable. To compensate for conventional, sequential
connections, more conductive layers for wiring may be added, but in
example embodiments, a wiring structure without added conductive
layers is shown in FIG. 7.
[0033] FIG. 7 illustrates an example of multi-layer substrate,
which may have electrical connections similar or substantially
similar to those in FIG. 6, without an added conductive layer.
Referring to FIG. 7, a first rank module may have a PCB structure
of including a plurality of (e.g., six) layers, which include a
plurality of (e.g., four) signal layers and two reference
power/ground layers. According to FIG. 7, a round-trip wire may be
added to the wiring of the existing two inside layers, and a wire
may be added to a sixth layer in which a memory device is not
disposed. The conventional art offers a one-way scheme in a
via-to-via connection within the inside layer. By contrast in FIG.
7, the round-trip scheme is provided in a via-to-via connection.
Consequently, an inside layer of a multi-layer printed circuit
board has the round-trip scheme via-to-via connection, and an outer
layer has a pin connection of a via-to-memory device. Accordingly,
a terminating resistance circuit may be arranged in an internal
region without an added conductive layer.
[0034] In arranging memory devices on both faces of a mounting
board, sides or surfaces of the module (e.g., second rank), an
outer layer may be used for wiring of round-trip signal line, and
an additional layout to the existing inside layer signal line may
be provided to form the wiring shown in FIG. 6. Wiring methods
according to at least some example embodiments may be applicable to
structures other than those discussed herein. In addition, when a
pinout of the module and/or a wiring direction is changed (e.g.,
left to right, right to left), example embodiments may be
applied.
[0035] FIGS. 8 and 9 illustrate various layout examples based on a
pinout of the module, wiring direction and/or module type. The
memory module may have different sizes and/or pinouts, and may have
configurable options such as using a buffer device. In FIGS. 8 and
9, arrows LW1 to LW4 and LW10 to LW13 represent channel connection
structures of signal lines.
[0036] The wiring boards 10 and 11 of FIG. 8 may have a center
entry type in which an arrow LW1 of the drawing enters through a
center or substantially center portion of the module and passes
sequentially through memory devices 20 to 28 and terminating
resistance circuit 33. An arrow LW2 may start through a center or
substantially center portion of the module and sequentially pass
through memory devices 28 to 20 and terminating resistance circuit
33. In wiring board 12, an arrow LW3 of the drawing begins through
a left portion of the module and sequentially passes through memory
devices 20 to 28 and terminating resistance circuit 33. In wiring
board 13, an arrow LW4 begins at a right portion of the module and
sequentially passes through memory devices 28 to 20 and terminating
resistance circuit 33.
[0037] The wiring boards 14, 15 and 16 illustrated in FIG. 9 may be
applicable to any or all types of DIMM structures having similar or
substantially similar wiring structures, such as, unbuffered
structures (UDIMM) in which a buffer device is not disposed,
registered modules (RDIMM) having register/phase locked loop (PLL)
integrated circuits (IC), and/or fully buffered DIMMs (FBDIMM)
using an AMB (Advanced Memory Buffer), a small-sized memory module
(SoDIMM: Small outline DIMM), etc. Example embodiments may be
applicable to all types of module layout and/or wiring having the
same or substantially the same signal line structure.
[0038] Referring to FIG. 9, in wiring board 14, arrow LW10 enters
through a right center portion of the module and passes
sequentially through memory devices 20 to 28 and terminating
resistance circuit 33. In wiring board 15, arrows LW11 and LW12
enter through a portion 40 between two adjacent memory devices 25
and 26. The arrow L11 passes sequentially through memory devices 24
to 20 and terminating resistance circuit 34. The arrow L12 passes
sequentially through memory devices 25 to 28 and terminating
resistance circuit 33. As shown, the structure of the wiring board
15 may include a plurality of terminating resistance circuits 33
and 34, each arranged between two adjacent memory devices. Although
shown as arranged between memory devices 20 and 21, and 28 and 29,
the terminating resistance circuits may be arranged between any two
adjacent memory devices.
[0039] In wiring board 16, the arrow LW13 may enter through a
center portion and pass sequentially through memory devices 20 to
23 and terminating resistance circuit 33.
[0040] As described above, in configuring a memory module by
mounting a plurality of memory devices on a wiring board, a
terminating resistance may be located between adjacent memory
devices, and may be electrically coupled to an output of a last
device among the memory devices. Accordingly, an exterior physical
impact applied to a terminating resistance circuit of the module
and/or handling damage may be reduced or substantially reduced to
enhance fidelity of the module.
[0041] Example embodiments may be applied to a technique of
mounting tape carrier packages TCPs with a given tilt on a mounting
surface of a wiring board by using support leads to obtain higher
density mounting and/or reduce a thickness of the wiring board. In
example embodiments of terminating resistance layouts, terminating
resistances may be located in an internal region of the module.
Example embodiments may be applied to conventional techniques
through an appropriate modulation.
[0042] Using example embodiments of structures of integrated
circuit modules and/or terminating resistor layout methods, an
outer physical impact and/or handling damage may be reduced or
substantially reduced. Operation reliability may also be
increased.
[0043] It will be apparent to those skilled in the art that
modifications and variations can be made in the present invention
without deviating from the spirit or scope of the invention. Thus,
it is intended that the present invention cover any such
modifications and variations of this invention provided they come
within the scope of the appended claims and their equivalents. For
example, positions for not only terminating resistances but other
module devices may be changed diversely. Accordingly, these and
other changes and modifications are seen to be within the true
spirit and scope of the invention as defined by the appended
claims.
[0044] In the drawings and specification, there have been disclosed
example embodiments and, although specific terms are employed, they
are used in a generic and descriptive sense only and not for
purposes of limitation, the scope of the invention being set forth
in the following claims.
* * * * *