U.S. patent application number 12/984563 was filed with the patent office on 2011-04-28 for method for fabricating p-channel field-effect transistor (fet).
Invention is credited to Tzyy-Ming Cheng, Cheng-Tung Huang, Wen-Han Hung, Li-Shian Jeng, Kun-Hsien Lee, Shyh-Fann Ting, Meng-Yi Wu.
Application Number | 20110097868 12/984563 |
Document ID | / |
Family ID | 39795146 |
Filed Date | 2011-04-28 |
United States Patent
Application |
20110097868 |
Kind Code |
A1 |
Lee; Kun-Hsien ; et
al. |
April 28, 2011 |
METHOD FOR FABRICATING P-CHANNEL FIELD-EFFECT TRANSISTOR (FET)
Abstract
A method for fabrication a p-type channel FET includes forming a
gate on a substrate. Then, a PAI ion implantation process is
performed. Further, a pocket implantation process is conducted to
form a pocket region. Thereafter, a first co-implantation process
is performed to define a source/drain extension region depth
profile. Then, a p-type source/drain extension region is formed.
Afterwards, a second co-implantation process is performed to define
a source/drain region depth profile. Thereafter, an in-situ doped
epitaxy growth process is performed to form a doped semiconductor
compound for serving as a p-type source/drain region.
Inventors: |
Lee; Kun-Hsien; (Tainan
City, TW) ; Huang; Cheng-Tung; (Kaohsiung City,
TW) ; Hung; Wen-Han; (Kaohsiung City, TW) ;
Ting; Shyh-Fann; (Kaohsiung County, TW) ; Jeng;
Li-Shian; (Taitung City, TW) ; Wu; Meng-Yi;
(Kaohsiung Hsien, TW) ; Cheng; Tzyy-Ming;
(Hsinchu, TW) |
Family ID: |
39795146 |
Appl. No.: |
12/984563 |
Filed: |
January 4, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11692609 |
Mar 28, 2007 |
7888223 |
|
|
12984563 |
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Current U.S.
Class: |
438/306 ;
257/E21.409 |
Current CPC
Class: |
H01L 21/26586 20130101;
H01L 21/26566 20130101; H01L 29/6659 20130101; H01L 21/26513
20130101; H01L 21/2658 20130101; H01L 21/26506 20130101; H01L
29/1083 20130101; H01L 29/7833 20130101 |
Class at
Publication: |
438/306 ;
257/E21.409 |
International
Class: |
H01L 21/336 20060101
H01L021/336 |
Claims
1. A method for fabricating a p-type channel field-effect
transistor, the method comprising: (A) forming a gate structure on
a substrate; (B) performing a pre-amorphization implantation
process to amorphize the substrate beside two sides of the gate
structure; (C) performing a pocket implantation process to form an
n-type pocket region in the substrate; (D) performing a first
co-implantation process and a fourth co-implantation process to
define a p-type source/drain extension region depth profile in the
substrate; and (E) forming a p-type source/drain extension region
in the substrate beside two sides of the gate structure.
2. The method of claim 1, further comprising: (F) performing a
second co-implantation process to define a p-type source/drain
region depth profile in the substrate; and (G) forming a
semiconductor compound layer in the substrate beside two sides of
the gate structure and forming a p-type source/drain region in the
semiconductor compound layer.
3. The method of claim 1, wherein a species implanted in the first
co-implantation process and the third co-implantation process
comprises carbon or fluorine.
4. The method of claim 2, wherein a species implanted in the second
co-implantation process comprises carbon or fluorine.
5. The method of claim 2, wherein the species implanted in the
first co-implantation process is different from the species
implanted in the second co-implantation process.
6. The method of claim 2, wherein the species implanted in the
first co-implantation process is the same as the species implanted
in the second co-implantation process.
7. The method of claim 2, implantation energy of the second
co-implantation process is higher than implantation energy of the
first co-implantation process.
8. The method of claim 2, wherein the step (G) comprises: (H)
performing an in-situ epitaxy growth process to form a doped
semiconductor compound as the p-type source/drain region, wherein a
sequence of performing the steps of (A) to (H) comprises performing
sequentially the steps of (A), (B), (D), (E), (C), (F) and (H).
9. The method of claim 8, wherein between any two neighboring steps
among the steps of (B), (D), (E), (C) and (F), step (I) of
performing a third co-implantation process is performed to define a
pocket region depth profile in the substrate.
10. The method of claim 9, wherein a species implanted in the third
co-implantation process comprises carbon or fluorine.
11. The method of claim 9, wherein energy of the third
co-implantation process is higher than energy of the first
co-implantation process.
12. The method of claim 8, wherein the step (G) comprises: (J)
performing an epitaxy growth process to form a semiconductor
compound; and (K) performing an ion implantation process to form a
p-type source/drain region, wherein a sequence of performing the
steps of (A) to (K) comprises performing sequentially the step (A),
the step (B), the step (D), the step (E), the step (C), the step
(J), the step (F) and the step (K).
13. The method of claim 12, wherein between any two neighboring
steps among the steps (B), (D), (E), (C) and (J), step (I) of
performing a third co-implantation process is performed to define a
pocket region depth profile in the substrate.
14. The method of claim 13, wherein a species implanted in the
third co-implantation process comprises carbon or fluorine.
15. The method of claim 13, wherein energy of the third
co-implantation process is higher than energy of the first
co-implantation process.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a division of U.S. application Ser. No.
11/692,609, filed Mar. 28, 2007, and incorporated herein by
reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a fabrication method of
integrated circuits. More particularly, the present invention
relates to a fabrication method of a complimentary
metal-oxide-semiconductor field-effect transistor (MOSFET).
[0004] 2. Description of the Prior Art
[0005] The demand for high speed and low power consumption for
logic devices can be accomplished by miniaturizing transistors.
Scaling transistors to smaller dimensions can provide the logic
devices with sufficiently high transistor saturation drain current
and low gate capacitance for high speed and reduce leakage current
for low power consumption.
[0006] However, as the size of a transistor is further reduced,
various problems generated from the short-channel effects become
significant. The ultra-shallow junction formation technique is one
method used to resolve the short-channel effects. According to the
traditional ultra-shallow junction formation technique, after the
formation of a gate electrode, dopants are implanted with an
appropriate amount of energy to two sides of the gate electrode,
followed by performing rapid thermal annealing to generate the
junction profile. Before the 90 nanometer (nm) generation,
achieving the proper resistance and depth basically relies on
lowering the implantation energy of dopants and diminishing the
annealing time. However, after the arrival of the 65 and 45 nm
generations, the conventional technique is no longer applicable.
Co-implantation, laser annealing and high-angle ion implantation
techniques are being investigated.
[0007] The concept of co-implantation technique is based on the
fact that ion implantation causes interstitials injection. These
interstitials are routes for transient enhanced diffusion of boron
ions during spike annealing. The co-implantation schemes have shown
to improve such an effect because the species implanted by
co-implantation form bonds with the interstitials. Ultimately, the
transient enhanced diffusion of boron ions and the formation of
boron cluster caused by the interstitials are reduced.
[0008] Currently, carbon is the most commonly employed species in a
single co-implantation process for increasing saturation voltage
and for controlling the short-channel effects. However, the
implanted carbon ions create abrupt junction depth profile.
Ultimately, high electric field is resulted that in turns induces
serious current leakage, especially at the side-wall-gate.
[0009] Fluorine ions are also of great interest as species for a
single co-implantation process because both the depth and the
abruptness of the junction profile can be better controlled.
Ultimately, current leakage is mitigated. However, co-implantation
with fluorine ions provides limited improvement on the saturation
voltage. Hence, it is ineffective in improving the short-channel
effects.
[0010] Another approach for enhancing the effectiveness of a device
is by altering the mobility of the source/drain region. Since the
traveling speed of electrons and holes in a silicon channel is
limited, the application of this approach in transistors is also
limited. The technology of employing a silicon germanium material
for the source/drain region of a transistor has been proposed. This
technology basically includes removing a portion of the silicon
substrate pre-determined for forming the source/drain region,
followed by employing the selective epitaxial technology to re-fill
the substrate with silicon germanium. Comparing a source/drain
region formed mainly with a silicon germanium material with that
formed with a silicon material, germanium has a smaller electron
effective mass and hole effective mass, the source/drain region
formed with silicon germanium can enhance the mobility of electrons
and holes. As a result, the effectiveness of the device is
improved.
[0011] However, during the formation of silicon germanium, the
epitaxy growth process is conducted at extremely high temperature.
The heat provided for the formation of silicon germanium also
causes the diffusion of boron, which ultimately leads to the
short-channel effects.
SUMMARY OF THE INVENTION
[0012] The present invention is to provide a fabrication method of
a semiconductor device, wherein the short-channel effects, caused
by the size reduction of a device and an epitaxy growth process,
can be mitigated.
[0013] A method for fabricating a p-type channel field-effect
transistor is disclosed. The method includes the steps of: (A)
forming a gate structure on a substrate; (B) performing a
pre-amorphization implantation process to amorphize the substrate
beside two sides of the gate structure; (C) performing a pocket
implantation process to form an n-type pocket region in the
substrate; (D) performing a first co-implantation process and a
fourth co-implantation process to define a p-type source/drain
extension region depth profile in the substrate; and (E) forming a
p-type source/drain extension region in the substrate beside two
sides of the gate structure.
[0014] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 is a schematic, cross-sectional view of a metal oxide
semiconductor device.
[0016] FIG. 2. is a flow chart of exemplary process steps for
fabricating a P-type channel field-effect transistor according to a
first embodiment of the present invention.
[0017] FIG. 3 is a flow chart of exemplary process steps for
fabricating a P-type channel field-effect transistor according to a
second embodiment of the present invention.
[0018] FIG. 4 is a flow chart of exemplary process steps for
fabricating a P-type channel field-effect transistor according to a
third embodiment of the present invention.
[0019] FIG. 5 is a flow chart of exemplary process steps for
fabricating a P-type channel field-effect transistor according to a
fourth embodiment of the present invention.
[0020] FIG. 6 is a flow chart of exemplary process steps for
fabricating a P-type channel field-effect transistor according to a
fifth embodiment of the present invention.
[0021] FIG. 7 is a flow chart of exemplary process steps for
fabricating a P-type channel field-effect transistor according to a
sixth embodiment of the present invention.
[0022] FIG. 8 is a flow chart of exemplary process steps for
fabricating a P-type channel field-effect transistor according to a
seventh embodiment of the present invention.
[0023] FIG. 9 is a flow chart of exemplary process steps for
fabricating a P-type channel field-effect transistor according to
an eighth embodiment of the present invention.
DETAILED DESCRIPTION
[0024] According to the fabrication method of a semiconductor
device of the present invention, preceding the implantation process
for the formation of, for example, the source/drain extension
region of a p-type channel field-effect (FET) transistor or the
source/drain region, or the pocket region of a p-type channel
field-effect transistor (FET) wherein the species in the ion
implantation process, such as the boron ion implantation, are
susceptible to diffusion or generation of the short-channel
effects, a co-implantation process is performed to lower the
transient enhanced diffusion effect of boron ions and the formation
of boron cluster. Further, another co-implantation process is
performed before or after performing the pocket implantation
process of a p-type FET to improve the effectiveness of the
device.
[0025] FIG. 1 is a schematic, cross-sectional view of a metal oxide
semiconductor device. In one embodiment, the metal oxide
semiconductor device formed on the substrate 100 is a P-type
channel field-effect transistor (FET) 10. The substrate 100 is a
P-type substrate, for example, and an N-type well region (not
shown) is formed in the P-type substrate. The gate structure 102 of
the p-type channel FET 10 is constructed with a gate dielectric
layer 104 and a gate conductive layer 106. The dopants in the
source/drain extension region 110 beside two sides of the gate
structure 102 include boron or BF.sub.3.sup.+. The dopants in the
pocket region 130 below the source/drain extension region 110
include n-type dopants, such as phosphorous or arsenic, for
suppressing the short-channel effects. Generally, the source/drain
extension region 110 and the pocket region 130 are formed in the
loop of the source/drain extension region during the semiconductor
fabrication process. The dopants in the source/drain region 120
beside two sides of the spacer 108 include boron or BF.sub.3.sup.+.
The source/drain region 120 is formed in the loop of the
source/drain region.
[0026] In one embodiment of the invention, when performing the
source/drain extension region loop, a first co-implantation process
is performed before forming the source/drain extension region 110.
The species implanted in the first co-implantation process can form
bonds with the interstitials in the depth profile predetermined for
forming the source/drain extension region 110. The transient
enhanced diffusion of boron ions and the formation of boron
cluster, caused by the interstitials, can be mitigated. The species
implanted in the first co-implantation process include but not
limited to carbon or fluorine. Further, the implantation energy is
related to the dimension of the device. For example, the first
co-implantation process includes employing implantation energy of
about 1 KeV to 6 KeV, a dosage of about 1.times.10.sup.14 to
2.times.10.sup.15/cm.sup.2 and an implantation angle of about 0 to
30 degrees. The source/drain region 120 at the periphery of the
spacer 108 is doped with boron or BF.sub.3.sup.+.
[0027] Further, in the embodiments of the present invention, during
the performance of the source/drain region loop, a second
co-implantation process is performed before forming the
source/drain region 120. The species implanted in the second
co-implantation process can form bonds with the interstitials in
the depth profile predetermined for forming the source/drain region
120. Thus, the transient enhanced diffusion of boron ions and the
formation of boron cluster, induced by the interstitials, can be
mitigated. The species implanted in the second co-implantation
process include but not limited to carbon or fluorine. Further, the
implantation energy is related to the dimension of the device. The
implantation energy is slightly greater than the previous
implantation energy used in the second co-implantation process for
forming the source/drain extension region 110. For example, the
second co-implantation process includes using implantation energy
of about 1 KeV to 30 KeV, a dosage of about 1.times.10.sup.14 to
2.times.10.sup.15/cm.sup.2 and an implantation angle of 0
degree.
[0028] The sequence of the process steps in a semiconductor
fabrication process may vary. For example, depending on the
sequence of the process steps, the pocket implantation may or may
not belong to the source/drain extension region loop. In one
embodiment, the pocket implantation process belongs to the
source/drain extension region loop, wherein during the source/drain
extension region loop, a third co-implantation process is performed
to implant a species, for example, carbon or fluorine, to the
pocket region 130 depth profile. In another embodiment, the pocket
implantation process is not a part of the source/drain extension
region loop, wherein the above third co-implantation process may be
conducted during the source/drain extension region loop, or before
or after performing the pocket implantation process. The
implantation energy of the third co-implantation process is
associated with the dimension of the device. For example, the third
co-implantation process is performed with implantation energy of
about 2 KeV to 20 KeV, an implanted dosage of about
1.times.10.sup.14 to 2.times.10.sup.15/cm.sup.2 and an implantation
angle of about 0 degree to 30 degrees. The species implanted in
above first, second and third co-implantation processes may be the
same or different.
[0029] Normally, a pre-amorphization implantation (PAI) process is
incorporated with the co-implantation process. The
pre-amorphization implantation process is mostly directed to
silicon or germanium, in which appropriate amounts of energy and
dosage can generate a destruction of the silicon lattice structure
of the substrate to from an amorphous layer. The amorphized
structure can lower the boron channeling and the transient enhanced
diffusion (TED). During a typical manufacturing process, the
pre-amorphization implantation process is directed to a germanium
substrate because, comparing with a silicon substrate, less surface
defects is generated and the low resistance of the shallow layer
that is formed is lower.
[0030] During the fabrication of a metal oxide semiconductor
device, the sequence of forming the source/drain extension region
110, the source/drain region 120 and the pocket region 130 can be
altered according the demands and conditions of the manufacturing
process. For example, the source/drain extension region 110 may
form first, followed by forming the source/drain region and then
the pocket region 130, or the source/drain extension region 110 may
form first, followed by forming the pocket region130 and then the
source/drain region. To enhance the electron mobility of the
source/drain region, a semiconductor compound is used and dopants
for the source/drain region are introduced by in-situ doping during
the epitaxy growth process of the semiconductor compound. On the
other hand, the dopants for the source/drain region may introduce
after the epitaxy growth process of the semiconductor compound. The
following embodiments illustrate the various sequences of process
steps of the fabrication method of the present invention.
[0031] FIGS. 2 to 9 are flow chart of exemplary process steps for
fabricating a P-type channel field-effect transistor according to
various embodiments of the present invention.
[0032] Referring to FIG. 2, a gate structure is formed on a
substrate in step 200. After this, step 202 is performed, in which
a pre-amorphization implantation process is performed to amorphize
the substrate at two sides of the gate structure, using the gate
structure as a mask. Thereafter, in step 204, a pocket implantation
process is performed to form an n-type pocket region in the
substrate. Continuing to step 206, a first co-implantation process
is performed to define a p-type source/drain extension region depth
profile in the substrate. Further, in step 208, a p-type
source/drain extension region is formed in the substrate. Then, in
step 210, a second co-implantation process is performed to define a
p-type source/drain depth profile in the substrate. Thereafter, in
step 212, an epitaxy growth process is performed to form a
semiconductor compound in the substrate, wherein the semiconductor
compound is doped in-situ to form a P-type source/drain region.
[0033] In one embodiment, the above fabrication method further
includes performing a third co-implantation process in step 220 to
define a pocket region depth profile. Step 220 can be performed
between any two neighboring process steps among the steps 202 to
210.
[0034] Referring to FIG. 3, a gate structure is formed on a
substrate in step 300. After this, step 302 is performed, in which
a pre-amorphization implantation process is performed to amorphize
the substrate at two sides of the gate structure, using the gate
structure as a mask. Thereafter, in step 304, a pocket implantation
process is performed to form an n-type pocket region in the
substrate. Continuing to step 306, a first co-implantation process
is performed to define a p-type source/drain extension region depth
profile in the substrate. Further, in step 308, a p-type
source/drain extension region is formed in the substrate. Then, in
step 310, an epitaxy growth process is performed to form a
semiconductor compound in the substrate. Continuing to step 312, a
second co-implantation process is performed to define a p-type
source/drain depth profile in the substrate. Thereafter, in step
314, an ion implantation process is performed to form a P-type
source/drain region.
[0035] In one embodiment, the above fabrication method further
includes performing a third co-implantation process in step 320 to
define a pocket region depth profile. Step 320 can be performed
between any two neighboring process steps among the steps 302 to
310.
[0036] Referring to FIG. 4, a gate structure is formed on a
substrate in step 400. After this, step 402 is performed, in which
a pre-amorphization implantation process is performed to amorphize
the substrate at two sides of the gate structure, using the gate
structure as a mask. Thereafter, in step 404, a co-implantation
process is performed to define a p-type source/drain extension
region depth profile. Continuing to step 406, a p-type source/drain
extension region is formed in the substrate. Then, in step 408, a
pocket implantation process is performed to form an n-type pocket
region in the substrate. Thereafter, in step 410, a second
co-implantation process is performed to define a p-type
source/drain region depth profile in the substrate. Then in step
412, an epitaxy growth process is performed to form a semiconductor
compound in the substrate, and an in-situ doping is performed to
form a p-type source/drain region.
[0037] In one embodiment, the above fabrication method further
includes step 420 of performing a third co-implantation process to
define a pocket region depth profile. Step 420 can be conducted
between any two neighboring steps among the steps 402 to 410.
Referring to FIG. 5, in step 500, a gate structure is formed on a
substrate. Then, in step 502, a pre-amorphization implantation
process is performed to amorphize the substrate beside two sides of
the gate structure. Thereafter, in step 504, a first
co-implantation process is performed to define a p-type
source/drain extension region depth profile. Continuing to step
506, a p-type extension region is formed in the substrate. After
this, in step 508, a pocket implantation process is performed to
form an n-type pocket region in the substrate. Then, in step 510,
an epitaxy growth process is performed to form a semiconductor
compound in the substrate. Continuing to step 512, a second
co-implantation process is performed to define a p-type
source/drain region depth profile to form a p-type source/drain
region. Thereafter, in step 514, an ion implantation process is
performed to form a p-type source/drain region.
[0038] In one embodiment, the above fabrication method may further
include step 520 of performing a third co-implantation process to
define the pocket region depth profile. Step 520 may be performed
between any two neighboring process steps among the steps 502 to
510.
[0039] Referring to FIG. 6, a gate structure is formed on a
substrate in step 600. After this, step 602 is performed, in which
a pre-amorphization implantation process is performed to amorphize
the substrate at two sides of the gate structure, using the gate
structure as a mask. Thereafter, in step 604, a co-implantation
process is performed to define a p-type source/drain extension
region depth profile. Continuing to step 606, an epitaxy growth
process is performed to form a semiconductor compound in the
substrate, and an in-situ doping is performed to form a p-type
source/drain region. In step 608, a pocket implantation process is
performed to form an n-type pocket region in the substrate.
Thereafter in step 610, another co-implantation process is
performed to define a p-type source/drain region depth profile in
the substrate. Then, in step 612, a p-type source/drain extension
region is formed in the substrate.
[0040] In one embodiment, the above fabrication method may further
include step 620 of performing a third co-implantation process to
define the pocket region depth profile. Step 620 may be performed
between any two neighboring process steps among the steps 606 to
612.
[0041] Referring to FIG. 7, a gate structure is formed on a
substrate in step 700. After this, step 702 is performed, in which
a pre-amorphization implantation process is performed to amorphize
the substrate at two sides of the gate structure, using the gate
structure as a mask. Thereafter, in step 704, an epitaxy growth
process is performed to form a semiconductor compound in the
substrate. Continuing to step 706, a co-implantation process is
performed to define a p-type source/drain extension region depth
profile in the substrate. Hereafter, in step 708, an ion
implantation process is performed to form a p-type source/drain
region. Then, in step 710, a pocket implantation process is
performed to form an n-type pocket region in the substrate. Further
in step 712, another co-implantation process is performed to define
a p-type source/drain region depth profile in the substrate.
Subsequently, in step 714, a p-type source/drain extension region
is formed in the substrate.
[0042] In one embodiment, the above fabrication method may further
include step 720 of performing a third co-implantation process to
define the pocket region depth profile. Step 720 may be performed
between any two neighboring process steps among the steps 708 to
714.
[0043] Referring to FIG. 8, a gate structure is formed on a
substrate in step 800. After this, step 802 is performed, in which
a pre-amorphization implantation process is performed to amorphize
the substrate at two sides of the gate structure, using the gate
structure as a mask. Thereafter, in step 804, a pocket implantation
process is performed to form an n-type pocket region in the
substrate. Continuing to step 806, a co-implantation process is
performed to define a p-type source/drain extension region depth
profile in the substrate. Further in step 808, an epitaxy growth
process is performed to form a semiconductor compound in the
substrate and an in-situ doping is performed to form a p-type
source/drain region. Then, in step 810, another co-implantation
process is performed to define a p-type source/drain region depth
profile in the substrate. Hereafter, in step 812, a p-type
source/drain extension region is formed in the substrate.
[0044] In one embodiment, the above fabrication method may further
include step 820 of performing a third co-implantation process to
define the pocket region depth profile. Step 820 may be performed
between any two neighboring process steps among the steps 802 to
806 or among the steps 808 and 812, or after step 812.
[0045] Referring to FIG. 9, a gate structure is formed on a
substrate in step 900. After this, step 902 is performed, in which
a pre-amorphization implantation process is performed to amorphize
the substrate at two sides of the gate structure, using the gate
structure as a mask. Thereafter, in step 904, a pocket implantation
process is performed to form an n-type pocket region in the
substrate. Continuing to step 906, an epitaxy growth process is
performed to form a semiconductor compound in the substrate.
Thereafter, in step 908, a co-implantation process is performed to
define a p-type source/drain extension region depth profile in the
substrate. Then, in step 910, an ion implantation process is
performed to form a p-type source/drain region. Further in step
912, another co-implantation process is performed to define a
p-type source/drain region depth profile in the substrate.
Subsequently, in step 914, a p-type source/drain extension region
is formed in the substrate.
[0046] In one embodiment, the above fabrication method may further
include step 920 of performing a third co-implantation process to
define the pocket region depth profile. Step 920 may be performed
between any two neighboring process steps among the steps 902 to
906, or between any two neighboring process steps among the process
steps 910 to 914. Although the embodiments herein refer to p-type
channel field-effect transistors, it is to be understood that the
present invention is also applicable to n-type field-effect
transistors. Further, the source/drain region of an n-type
field-effect transistor may constitute with a material including
silicon carbide, which may form by an epitaxy growth process.
[0047] The present invention has been disclosed above in the
preferred embodiments, but is not limited to those. It is known to
persons skilled in the art that some modifications and innovations
may be made without departing from the spirit and scope of the
present invention. Therefore, the scope of the present invention
should be defined by the following claims.
[0048] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *