U.S. patent application number 12/805933 was filed with the patent office on 2011-04-21 for graphene device and method of manufacturing the same.
This patent application is currently assigned to Samsung Electronics Co., Ltd.. Invention is credited to Hyun-jong Chung, Jin seong Heo, Dong-chul Kim, Sun-ae Seo, Yun-sung Woo.
Application Number | 20110089995 12/805933 |
Document ID | / |
Family ID | 43878826 |
Filed Date | 2011-04-21 |
United States Patent
Application |
20110089995 |
Kind Code |
A1 |
Heo; Jin seong ; et
al. |
April 21, 2011 |
Graphene device and method of manufacturing the same
Abstract
Provided is a graphene device and a method of manufacturing the
same. The graphene device may include an upper oxide layer on at
least one embedded gate, and a graphene channel and a plurality of
electrodes on the upper oxide layer. The at least one embedded gate
may be formed on the substrate. The graphene channel may be formed
on the plurality of electrodes, or the plurality of electrodes may
be formed on the graphene channel.
Inventors: |
Heo; Jin seong; (Suwon-si,
KR) ; Seo; Sun-ae; (Hwaseong-si, KR) ; Kim;
Dong-chul; (Suwon-si, KR) ; Woo; Yun-sung;
(Suwon-si, KR) ; Chung; Hyun-jong; (Hwaseong-si,
KR) |
Assignee: |
Samsung Electronics Co.,
Ltd.
Suwon-si
KR
|
Family ID: |
43878826 |
Appl. No.: |
12/805933 |
Filed: |
August 25, 2010 |
Current U.S.
Class: |
327/534 ; 257/29;
257/E21.404; 257/E29.245; 438/158 |
Current CPC
Class: |
H01L 29/42384 20130101;
H01L 29/78645 20130101; H01L 29/78684 20130101; H01L 29/1606
20130101; H01L 29/7781 20130101; H01L 29/66742 20130101 |
Class at
Publication: |
327/534 ; 257/29;
438/158; 257/E29.245; 257/E21.404 |
International
Class: |
H03K 3/01 20060101
H03K003/01; H01L 29/775 20060101 H01L029/775; H01L 21/335 20060101
H01L021/335 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 16, 2009 |
KR |
10-2009-0098778 |
Claims
1. A graphene device comprising: at least one embedded gate on a
substrate; an upper oxide layer on the at least one embedded gate;
and a graphene channel and a plurality of electrodes on the upper
oxide layer.
2. The graphene device of claim 1, wherein the plurality of
electrodes are on the graphene channel.
3. The graphene device of claim 2, wherein the graphene device is
an inverter.
4. The graphene device of claim 1, wherein the graphene channel is
on the plurality of electrodes.
5. The graphene device of claim 1, wherein the graphene channel is
on and between the plurality of electrodes.
6. The graphene device of claim 3, wherein the graphene channel is
spaced apart from the upper oxide layer.
7. The graphene device of claim 3, wherein the plurality of
electrodes are three electrodes spaced apart on the graphene
channel and the at least one embedded gate is one embedded gate
such that the graphene device operates as the inverter.
8. The graphene device of claim 2, further comprising: an
insulating layer on the graphene channel and between the plurality
of electrodes; at least one metal pattern on the insulating layer,
the at least one metal pattern corresponding with the at least one
embedded gate.
9. The graphene device of claim 1, wherein the substrate includes a
semiconductor substrate and an oxide layer which are sequentially
stacked.
10. The graphene device of claim 2, wherein the graphene channel
has a single layer, bi-layer, or multi-layer structure.
11. The graphene device of claim 4, wherein the graphene channel
has a single layer, bi-layer, or multi-layer structure.
12. The graphene device of claim 8, wherein the graphene channel
has a bi-layer structure.
13. A method of manufacturing a graphene device, comprising:
forming at least one an embedded gate on a substrate; forming an
upper oxide layer on the at least one embedded gate; and forming a
graphene channel and a plurality of electrodes on the upper oxide
layer.
14. The method of claim 13, wherein the plurality of electrodes are
formed on the graphene channel.
15. The method of claim 13, wherein the graphene channel is formed
on the plurality of electrodes.
16. The method of claim 13, wherein the graphene channel is formed
on the plurality of electrodes and on the upper oxide layer between
the plurality of electrodes.
17. The method of claim 14, wherein a graphene layer is formed and
then deposited on the upper oxide layer to form the graphene
channel.
18. The method of claim 15, wherein a graphene layer is formed and
then deposited on the upper oxide layer to form the graphene
channel.
19. The method of claim 16, wherein a graphene layer is formed and
then deposited on the upper oxide layer to form the graphene
channel.
20. The method of claim 14, wherein the plurality of electrodes is
three electrodes, and the at least one embedded gate is one
embedded gate.
21. The method of claim 14, further comprising: forming an
insulating layer between the plurality of electrodes on the
graphene channel; and forming at least one metal pattern on the
insulating layer, the at least one metal pattern corresponding with
the at least one embedded gate.
22. The method of claim 14, wherein the graphene channel is formed
by depositing a single layer, bi-layer, or multi-layer
graphene.
23. The method of claim 15, wherein the graphene channel is formed
by depositing a single layer, bi-layer, or multi-layer
graphene.
24. The method of claim 21, wherein the graphene channel is formed
by depositing a bi-layer graphene.
25. The method of claim 13, wherein the graphene device is an
inverter.
26. A method of operating a graphene device comprising: providing a
graphene channel and a plurality of electrodes on at least one
embedded gate and a metal pattern between the plurality of
electrodes, the at least one metal pattern corresponding with the
at least one embedded gate; and applying different voltages to at
least two of the plurality of electrodes and the metal pattern,
respectively.
27. The method of claim 26, wherein the voltage applied to one of
the plurality of electrodes is a VDD voltage and the voltage
applied to another of the plurality of electrodes is a ground
voltage.
28. The method of claim 27, wherein the graphene channel is an
N-type or P-type channel.
29. The method of claim 28, wherein the graphene channel is an
N-type channel and the voltage applied to the metal pattern is a
negative voltage.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority under U.S.C. .sctn.119 to
Korean Patent Application No. 10-2009-0098778, filed on Oct. 16,
2009, in the Korean Intellectual Property Office (KIPO), the entire
contents of which are incorporated herein by reference.
BACKGROUND
[0002] 1. Field
[0003] Example embodiments relate to a graphene device and a method
of manufacturing the same.
[0004] 2. Description of the Related Art
[0005] Recently, research on graphene that can be used instead of
semiconductor devices has been widely conducted. Graphene is a zero
gap semiconductor. When a graphene nano-ribbon (GNR) is formed to
have a channel width less than about 10 nm, a band gap may be
formed due to a size effect. Accordingly, a field effect transistor
capable of operating at room temperature may be manufactured by
using the GNR.
[0006] After the GNR is formed, an oxide layer having a thickness
of about 300 nm may be formed thereon, and a global back gate may
be formed on the oxide layer. However, coupling between the oxide
layer and the global back gate may be relatively low, and
accordingly, an operation voltage of the FET may increase. Also, if
the processes of forming the oxide layer and a gate electrode on
the oxide layer are used, a manufacturing process may be
complicated, and thus, the properties of graphene may change.
SUMMARY
[0007] Example embodiments provide a graphene device that may be
manufactured using a relatively simple process that facilitates
operation control and does not affect the properties of the
graphene device and a method of manufacturing the graphene
device.
[0008] Additional aspects will be set forth in part in the
description which follows and, in part, will be apparent from the
description, or may be learned by practice of example
embodiments.
[0009] According to example embodiments, a graphene device may
include at least one embedded gate on a substrate, an upper oxide
layer on the at least one embedded gate and a graphene channel and
a plurality of electrodes on the upper oxide layer.
[0010] The plurality of electrodes may be on the graphene channel
and the graphene device may be an inverter. The graphene channel
may be on and/or between the plurality of electrodes and may be
spaced apart from the upper oxide layer. The plurality of
electrodes may be three electrodes spaced apart on the graphene
channel and the at least one embedded gate may be one embedded gate
such that the graphene device operates as the inverter.
[0011] The graphene device may further include an insulating layer
on the graphene channel and between the plurality of electrodes and
at least one metal pattern on the insulating layer, the at least
one metal pattern corresponding with the at least one embedded
gate. The substrate may include a semiconductor substrate and an
oxide layer which are sequentially stacked. The graphene channel
may have a single layer, bi-layer, or multi-layer structure.
[0012] According to example embodiments, a method of manufacturing
a graphene device may include forming at least one an embedded gate
on a substrate, forming an upper oxide layer on the at least one
embedded gate and forming a graphene channel and a plurality of
electrodes on the upper oxide layer.
[0013] The plurality of electrodes may be formed on the graphene
channel or the graphene channel may be formed on the plurality of
electrodes. The graphene channel may also be formed on the upper
oxide layer between the plurality of electrodes. A graphene layer
may be formed and then deposited on the upper oxide layer to form
the graphene channel. The plurality of electrodes may be three
electrodes, and the at least one embedded gate may be one embedded
gate. The method may further include forming an insulating layer
between the plurality of electrodes on the graphene channel and
forming at least one metal pattern on the insulating layer, the at
least one metal pattern corresponding with the at least one
embedded gate. The graphene channel may be formed by depositing a
single layer, bi-layer, or multi-layer graphene and the graphene
device may be an inverter.
[0014] According to example embodiments, a method of operating a
graphene device may include providing a graphene channel and a
plurality of electrodes on at least one embedded gate and a metal
pattern between the plurality of electrodes, the at least one metal
pattern corresponding with the at least one embedded gate and
applying different voltages to at least two of the plurality of
electrodes and the metal pattern, respectively.
[0015] The voltage applied to one of the plurality of electrodes
may be a VDD voltage and the voltage applied to another of the
plurality of electrodes may be a ground voltage. The graphene
channel may be an N-type or P-type channel, and if the graphene
channel is an N-type channel, the voltage applied to the metal
pattern may be a negative voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] These and/or other aspects will become apparent and more
readily appreciated from the following description of example
embodiments, taken in conjunction with the accompanying drawings of
which:
[0017] FIGS. 1 through 5 are cross-sectional views illustrating a
graphene device according to example embodiments; and
[0018] FIGS. 6 through 11 are cross-sectional views illustrating a
method of manufacturing a graphene device according to example
embodiments.
DETAILED DESCRIPTION
[0019] Hereinafter, a graphene device and a method of manufacturing
the same according to example embodiments will be described in
detail by explanation with reference to the attached drawings. In
the drawings, the thicknesses of layers and regions are exaggerated
for clarity. Example embodiments may, however, be embodied in many
different forms and should not be construed as being limited to
example embodiments set forth herein; rather, these example
embodiments are provided so that this disclosure will be thorough
and complete, and will fully convey the concept of example
embodiments to those of ordinary skill in the art.
[0020] It will be understood that when an element is referred to as
being "connected" or "coupled" to another element, it can be
directly connected or coupled to the other element or intervening
elements may be present. In contrast, when an element is referred
to as being "directly connected" or "directly coupled" to another
element, there are no intervening elements present. As used herein
the term "and/or" includes any and all combinations of one or more
of the associated listed items.
[0021] It will be understood that, although the terms "first",
"second", etc. may be used herein to describe various elements,
components, regions, layers and/or sections, these elements,
components, regions, layers and/or sections should not be limited
by these terms. These terms are only used to distinguish one
element, component, region, layer or section from another element,
component, region, layer or section. Thus, a first element,
component, region, layer or section discussed below could be termed
a second element, component, region, layer or section without
departing from the teachings of example embodiments.
[0022] Spatially relative terms, such as "beneath," "below,"
"lower," "above," "upper" and the like, may be used herein for ease
of description to describe one element or feature's relationship to
another element(s) or feature(s) as illustrated in the figures. It
will be understood that the spatially relative terms are intended
to encompass different orientations of the device in use or
operation in addition to the orientation depicted in the figures.
For example, if the device in the figures is turned over, elements
described as "below" or "beneath" other elements or features would
then be oriented "above" the other elements or features. Thus, the
exemplary term "below" can encompass both an orientation of above
and below. The device may be otherwise oriented (rotated 90 degrees
or at other orientations) and the spatially relative descriptors
used herein interpreted accordingly.
[0023] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
example embodiments. As used herein, the singular forms "a," "an"
and "the" are intended to include the plural forms as well, unless
the context clearly indicates otherwise. It will be further
understood that the terms "comprises", "comprising", "includes"
and/or "including," if used herein, specify the presence of stated
features, integers, steps, operations, elements, and/or components,
but do not preclude the presence or addition of one or more other
features, integers, steps, operations, elements, components, and/or
groups thereof.
[0024] Example embodiments are described herein with reference to
cross-sectional illustrations that are schematic illustrations of
idealized embodiments (and intermediate structures) of example
embodiments. As such, variations from the shapes of the
illustrations as a result, for example, of manufacturing techniques
and/or tolerances, are to be expected. Thus, example embodiments
should not be construed as limited to the particular shapes of
regions illustrated herein but are to include deviations in shapes
that result, for example, from manufacturing. For example, an
implanted region illustrated as a rectangle will, typically, have
rounded or curved features and/or a gradient of implant
concentration at its edges rather than a binary change from
implanted to non-implanted region. Likewise, a buried region formed
by implantation may result in some implantation in the region
between the buried region and the surface through which the
implantation takes place. Thus, the regions illustrated in the
figures are schematic in nature and their shapes are not intended
to illustrate the actual shape of a region of a device and are not
intended to limit the scope of example embodiments.
[0025] Unless otherwise defined, all terms (including technical and
scientific terms) used herein have the same meaning as commonly
understood by one of ordinary skill in the art to which example
embodiments belong. It will be further understood that terms, such
as those defined in commonly-used dictionaries, should be
interpreted as having a meaning that is consistent with their
meaning in the context of the relevant art and will not be
interpreted in an idealized or overly formal sense unless expressly
so defined herein.
[0026] FIGS. 1 through 5 are cross-sectional views illustrating a
graphene device according to example embodiments. Referring to FIG.
1, a lower oxide layer 22 may be formed on a substrate 20 to cover
an upper surface of the substrate 20. The substrate 20 may be a
silicon substrate or another substrate. The lower oxide layer 22
may be a buffer layer for forming an electrode. The lower oxide
layer 22 may be a silicon oxide layer or another oxide layer. For
example, the lower oxide layer 22 may be an oxide layer including
another material except silicon, or alternatively, may be an oxide
layer including silicon and another material.
[0027] First through third metal patterns 24A, 24B, and 24C may be
formed spaced apart from one another on the lower oxide layer 22.
The number of metal patterns may vary, for example, three or more,
or three or less. The first through third metal patterns 24A, 24B,
and 24C may be gate electrodes formed of TiN. Alternatively, the
first through third metal patterns 24A, 24B, and 24C may be formed
of a conventional material that may be used as a gate electrode.
The first through third metal patterns 24A, 24B, and 24C may be a
single layer or a multi-layer. An interlayer insulating layer 26
surrounding the first through third metal patterns 24A, 24B, and
24C may be formed on the lower oxide layer 22. Thus, the first
through third metal patterns 24A, 24B, and 24C may be embedded in
the interlayer insulating layer 26.
[0028] The interlayer insulating layer 26 may have the same height
as the first through third metal patterns 24A, 24B, and 24C. Thus,
the interlayer insulating layer 26 and the first through third
metal patterns 24A, 24B, and 24C may form a flat surface. The
interlayer insulating layer 26 may be a silicon oxide layer or
another insulating layer.
[0029] As such, a plurality of gate electrodes (not shown) embedded
in the interlayer insulating layer 26 may be formed under a
graphene channel, and thus, a graphene device including a plurality
of gate electrodes that are independently controlled may be formed,
thereby facilitating the control of the graphene device.
[0030] An upper oxide layer 28 covering the first through third
metal patterns 24A, 24B, and 24C may be formed on the interlayer
insulating layer 26. The upper oxide layer 28 may be an aluminum
oxide layer or another oxide layer. Alternatively, the upper oxide
layer 28 may be formed of the same material as the lower oxide
layer 22. The upper oxide layer 28 may have a thickness of about 20
nm or less. A graphene channel 30 formed with a graphene layer may
be formed on the upper oxide layer 28. The graphene channel 30 may
have a single-layer, bi-layer, or multi-layer structure. The
graphene channel 30 may have a multi-layer structure as long as the
graphene channel 30 is not a metal layer. First and second
electrodes 32 and 34 may be formed on the graphene channel 30. One
of the first and second electrodes 32 and 34 is a source electrode,
and the other is a drain electrode. The first electrode 32 may be
formed on one end of the graphene channel 30, and the second
electrode 34 may be disposed on other end of the graphene channel
30.
[0031] The first through third metal patterns 24A, 24B, and 24C may
be formed between the first electrode 32 and the second electrode
34. The first and second electrodes 32 and 34 are spaced apart from
the first through third metal patterns 24A, 24B, and 24C. A first
portion 30A facing an upper surface of the first metal pattern 24A
of the graphene channel 30 may be a P-type or an N-type according
to a voltage applied to the first metal pattern 24A. For example,
when the voltage applied to the first metal pattern 24A is a
positive voltage +V, the first portion 30A of the graphene channel
30 may be an N-type. A second portion 30B facing an upper surface
of the second metal pattern 24B of the graphene channel 30 may be
of a P-type or an N-type according to a voltage applied to the
second metal pattern 24B.
[0032] For example, when the voltage applied to the second metal
pattern 24B is a negative voltage -V, the second portion 30B of the
graphene channel 30 may be a P-type. Also, a third portion 30C
facing an upper surface of the third metal pattern 24C of the
graphene channel 30 may be a P-type or an N-type according to a
voltage applied to the third metal pattern 24C. For example, when
the voltage applied to the third metal pattern 24C is a positive
voltage +V, the third portion 30C may be an N-type. Accordingly,
the graphene device of FIG. 1 may be one selected from the group
consisting of PPP, PPN, PNP, NPP, NPN, NNP, PNN, and NNN types.
[0033] The graphene channel 30 may be formed on the first and
second electrodes 32 and 34, as illustrated in FIG. 2. In detail,
one end of the graphene channel 30 may be formed on an upper
surface of one of the first and second electrodes 32 and 34, and
other end of the graphene channel 30 may be formed on an upper
surface of the other of the first and second electrodes 32 and 34.
That is, the graphene channel 30 may be supported by the first and
second electrodes 32 and 34. The graphene channel 30 may also be
formed on the upper oxide layer 28 disposed between the first and
second electrodes 32 and 34, as illustrated in FIG. 3, and may
extend on the first and second electrodes 32 and 34 along surfaces
thereof.
[0034] FIG. 4 illustrates a graphene-based inverter as an example
of a graphene device, according to example embodiments. Like
reference numerals in the following description denote like
elements in the previous description, and thus, they will not be
explained again.
[0035] Referring to FIG. 4, a lower oxide layer 22 may be formed on
a substrate 20. A fourth metal pattern 40 may be formed on the
lower oxide layer 22. The fourth metal pattern 40 may be a gate
electrode. The fourth metal pattern 40 may be formed of the same
material as the first through third metal patterns 24A, 24B, and
24C of FIG. 1. An interlayer insulating layer 42 surrounding the
fourth metal pattern 40 may be formed on the lower oxide layer 22.
The interlayer insulating layer 42 may have the same height as the
fourth metal pattern 40. Accordingly, an upper surface of the
fourth metal pattern 40 and an upper surface of the interlayer
insulating layer 42 may form a flat surface. The interlayer
insulating layer 42 may be the same as the interlayer insulating
layer 26 of FIG. 1.
[0036] An upper oxide layer 44 covering the upper surface of the
fourth metal pattern 40 may be formed on the interlayer insulating
layer 42. The upper oxide layer 44 may be the same as the upper
oxide layer 28 of FIG. 1. A graphene channel 46 may be formed on
the upper oxide layer 44. The graphene channel 46 may be the same
as the graphene channel 30 of FIG. 1. The graphene channel 46 may
be a P-type or an N-type. Third through fifth electrodes 48, 50,
and 52 may be formed on the graphene channel 46. The fourth metal
pattern 40 may be formed between the fourth electrode 50 and the
fifth electrode 52. To operate the inverter, a VDD may be applied
to the third electrode 48, and a ground voltage may be applied to
the fifth electrode 52. When the graphene channel 46 is an N-type,
a negative voltage -V may be applied to the fourth metal pattern
40. In example embodiments, a portion between the fourth electrode
50 and the fifth electrode 52 of the graphene channel 46 may be a
P-type.
[0037] The inverter of FIG. 4 may be operated as follows. If R1 is
a resistance of the graphene channel 46 between the third electrode
48 and the fourth electrode 50 and R2 is a resistance of the
graphene channel 46 between the fourth electrode 50 and the fifth
electrode 52, a voltage Vout applied to the fourth electrode 50 is
Vout=VDD*(1/(1+R1/R2)). A voltage +Vin may be applied to the fourth
metal pattern 40, R2=R1-.DELTA.R, and a voltage Vin may be applied
to the fourth metal pattern 40, R2=R1+.DELTA.R, where .DELTA.R is
difference between R1 and R2. Accordingly, Vout(-Vin) is larger
than Vout(Vin), that is, Vout(-Vin)>Vout(Vin), and thereby, an
inverter may be embodied. The Vout (Vin) denotes a voltage applied
to the fourth electrode 50 when a voltage +Vin is applied to the
fourth metal pattern 40. The Vout (-Vin) denotes a voltage applied
to the fourth electrode 50 when a voltage -Vin is applied to the
fourth metal pattern 40.
[0038] FIG. 5 illustrates a graphene device according to example
embodiments. Referring to FIG. 5, a lower oxide layer 22 may be
formed on a substrate 20. First through third metal patterns 24A,
24B, and 24C may be formed spaced apart from one another on the
lower oxide layer 22. An interlayer insulating layer 26 surrounding
the first through third metal patterns 24A, 24B, and 24C may be
formed on the lower oxide layer 22. An upper oxide layer 28
covering upper surfaces of the first through third metal patterns
24A, 24B, and 24C may be formed on the interlayer insulating layer
26. A graphene channel 30 may be formed on the upper oxide layer
28. The graphene channel 30 may be a bi-layer channel. First and
second electrodes 32 and 34 spaced apart from each other may be
formed on the graphene channel 30.
[0039] The graphene channel 30 between the first electrode 32 and
the second electrode 34 may be covered by an insulating layer 60.
The insulating layer 60 may be formed of the same material as the
upper oxide layer 28. The insulating layer 60 may have a thickness
of about 20 nm or less. The thickness of the insulating layer 60
may be the same as that of the upper oxide layer 28. Fifth through
seventh metal patterns 62A, 62B, and 62C may be formed on the
insulating layer 60. The fifth through seventh metal patterns 62A,
62B, and 62C may be formed on the first through third metal
patterns 24A, 24B, and 24C, respectively, to correspond to each
other.
[0040] When a predetermined or given voltage is applied to the
first through third metal patterns 24A, 24B, and 24C and the fifth
through seventh metal patterns 62A, 62B, and 62C, a band gap of the
graphene channel 30 between the metal patterns disposed one above
the other may be controlled. For example, if a potential difference
between the first metal pattern 24A and the fifth metal pattern 62A
is greater than that between the second metal pattern 24B and the
sixth metal pattern 62B, a band gap of the graphene channel 30
disposed between the first metal pattern 24A and the fifth metal
pattern 62A may be greater than that of the graphene channel 30
disposed between the second metal pattern 24B and the sixth metal
pattern 62B. As an example, a voltage of -2V may be applied to the
first metal pattern 24A, a voltage of +2V may be applied to the
fifth metal pattern 62A, a voltage of -1V may be applied to the
second metal pattern 24B, and a voltage of +1V may be applied to
the sixth metal pattern 62B.
[0041] A method of manufacturing a graphene device according to
example embodiments will now be described with reference to FIGS. 6
through 11. Referring to FIG. 6, a lower oxide layer 22 may be
formed on a substrate 20. First through third metal patterns 24A,
24B, and 24C may be formed on the lower oxide layer 22. The first
through third metal patterns 24A, 24B, and 24C may be formed by
forming a metal layer (not shown) on the lower oxide layer 22 and
etching the metal layer using a predetermined or given etching
process, for example, a reactive ion etching (RIE) method. The
metal layer may be etched using another etching method. The metal
layer may be formed of TiN using a chemical vapor deposition (CVD)
method or using another method. A manufacturing process may be
simplified by forming the first through third metal patterns 24A,
24B, and 24C, that is, gate electrodes before forming a graphene
channel.
[0042] Referring to FIG. 7, an interlayer insulating layer 26
surrounding the first through third metal patterns 24A, 24B, and
24C may be formed on the lower oxide layer 22. The interlayer
insulating layer 26 may be formed of a silicon oxide layer or other
insulating material or oxide. The interlayer insulating layer 26
may be formed by forming an insulating layer (not shown) covering
the first through third metal patterns 24A, 24B, and 24C on the
lower oxide layer 22 and etching an upper surface of the insulating
layer until the first through third metal patterns 24A, 24B, and
24C are exposed. Such an etching process may be performed by
etchback or chemical mechanical polishing (CMP). The insulating
layer may be formed by plasma enhanced CVD (PECVD), but may be
formed using another depositing method.
[0043] The first through third metal patterns 24A, 24B, and 24C may
be embedded in the interlayer insulating layer 26 before a graphene
channel is formed, and thus, change of properties of graphene that
may occur when a graphene channel is formed before forming the gate
electrodes may be prevented or reduced.
[0044] Referring to FIG. 8, an upper oxide layer 28 covering the
first through third metal patterns 24A, 24B, and 24C may be formed
on the interlayer insulating layer 26. The upper oxide layer 28 may
be formed of an aluminum oxide layer and may have a thickness of
about 20 nm or less. However, the thickness of the upper oxide
layer 28 may be controlled as needed. A graphene channel 30 may be
formed on the upper oxide layer 28. A graphene layer may be formed
independently, and the graphene layer may be transferred on the
upper oxide layer 28 to form the graphene channel 30. The
transferred graphene layer may be a CVD graphene or a flake sample.
The graphene channel 30 may have a single layer, bi-layer, or
multi-layer structure.
[0045] After the upper oxide layer 28 is formed, first and second
electrodes 32 and 34 may be formed spaced apart from each other on
the first and second electrodes 32 and 34, as illustrated in FIG.
9. The first and second electrodes 32 and 34 may be located outside
of the first through third metal patterns 24A, 24B, and 24C.
[0046] After the upper oxide layer 28 is formed, the first and
second electrodes 32 and 34 may be first formed on the upper oxide
layer 28, as illustrated in FIG. 10. As illustrated in FIG. 11, the
graphene channel 30 may be transferred on the first and second
electrodes 32 and 34. In example embodiments, ends of the graphene
channel 30 are placed on the first and second electrodes 32 and 34.
Thus, the graphene channel 30 may be supported by the first and
second electrodes 32 and 34. The inverter of FIG. 4 and the
graphene device of FIG. 5 may be manufactured using a manufacturing
method illustrated in FIGS. 6 through 9.
[0047] It should be understood that example embodiments described
therein should be considered in a descriptive sense only and not
for purposes of limitation. Descriptions of features or aspects
within each example embodiment should typically be considered as
available for other similar features or aspects in other example
embodiments.
* * * * *