U.S. patent application number 12/926773 was filed with the patent office on 2011-04-07 for semiconductor circuit including electrostatic discharge circuit having protection element and trigger transistor.
This patent application is currently assigned to Renesas Electronics Corporation. Invention is credited to Yasuyuki Morishita.
Application Number | 20110079818 12/926773 |
Document ID | / |
Family ID | 39740754 |
Filed Date | 2011-04-07 |
United States Patent
Application |
20110079818 |
Kind Code |
A1 |
Morishita; Yasuyuki |
April 7, 2011 |
Semiconductor circuit including electrostatic discharge circuit
having protection element and trigger transistor
Abstract
A semiconductor circuit includes a first pad for a first power
source, a second pad for a second power source, a third pad for an
input/output signal, a protection element arranged between the
first pad and the third pad, and a transistor functioning as a
trigger element for use in passing a trigger current through the
protection element. The transistor includes source connected to the
third pad, a gate and a backgate commonly connected to the second
pad.
Inventors: |
Morishita; Yasuyuki;
(Kanagawa, JP) |
Assignee: |
Renesas Electronics
Corporation
Kawasaki-shi
JP
|
Family ID: |
39740754 |
Appl. No.: |
12/926773 |
Filed: |
December 8, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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12071766 |
Feb 26, 2008 |
|
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12926773 |
|
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Current U.S.
Class: |
257/137 ;
257/E29.166 |
Current CPC
Class: |
H01L 29/7436 20130101;
H01L 27/0262 20130101 |
Class at
Publication: |
257/137 ;
257/E29.166 |
International
Class: |
H01L 29/66 20060101
H01L029/66 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 7, 2007 |
JP |
2007-057165 |
Claims
1. A semiconductor circuit comprising: a first pad for a first
power source; a second pad for a second power source; a third pad
for an input/output signal; a protection element arranged between
the first pad and the third pad; and a transistor functioning as a
trigger element for use in passing a trigger current through the
protection element, said transistor including a source connected to
the third pad, a gate and a backgate commonly connected to the
second pad.
2. The semiconductor circuit according to claim 1,wherein the
protection element comprises a silicon controlled rectifier (SCR),
wherein an anode of the SCR is connected to the first pad, wherein
a cathode of the SCR is connected to the third pad, andwherein a
gate of the SCR is connected to a drain of the transistor.
3. The semiconductor circuit according to claim 2, wherein the SCR
comprises: a member of a P-type substrate or a P-well; a first
P.sup.3+ region formed at the member and connected to the second
pad; a first N.sup.+ region formed at the member and connected to
the third pad; an N-well formed at the P-type substrate or adjacent
to the P-well; a second P.sup.+ region formed at the N-well and
connected to the first pad; and a second N.sup.+ region formed at
the N-well and connected to a drain of the transistor.
4. The semiconductor circuit as claimed in claim 1, wherein said
transistor comprises a NMOS transistor, said first power source
comprises VDD, and said second power source comprises VSS.
5. The semiconductor circuit as claimed in claim 1, wherein said
second pad is at a ground level, the first pad is at a power supply
voltage level, and said third pad is supplied with a signal always
higher than the ground level.
Description
[0001] The present Application is a Divisional Application of U.S.
patent application Ser. No. 12/071,766, filed on Feb. 26, 2008.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0002] This application is based upon, claims the benefit of
priority of, and incorporates by reference the contents of Japanese
Patent Application No. 2007-057165 filed on Mar. 7, 2007.
BACKGROUND OF THE INVENTION
[0003] 1. Field of the Invention
[0004] This invention relates to a semiconductor circuit and more
particularly to a semiconductor integrated circuit on which an
electrostatic discharge (ESD) protection circuit for use in
preventing damage to an internal circuit caused by an ESD and
application of surges is installed.
[0005] 2. Description of Related Art
[0006] On the semiconductor integrated circuit is installed an ESD
protection circuit for use in protecting an internal circuit
against a surge applied to input/output pads. One of the well-known
circuit topologies in the ESD protection circuit is a circuit
topology using a silicon controlled rectifier (SCR). The ESD
protection circuit using the SCR has an advantage that a
discharging capability for performing an active operation is high
when the surge is inputted, and this circuit is thus widely
used.
[0007] The ESD protection circuit using the SCR is typically
constituted by a SCR and a trigger element connected to the gate of
the SCR. One of the elements to be used as the trigger element is a
PMOS transistor. For example, Japanese Patent Laid-Open Application
No. 2003-318265 discloses an ESD protection circuit having a
configuration in which the PMOS transistor is connected to the gate
of P gate-type SCR (refer to FIG. 1). The ESD protection circuit in
FIG. 1 is constituted by the SCR and the PMOS transistor 105. Anode
of the SCR is connected to an I/O pad 102, and its cathode is
connected to VSS pad 103. The gate of the SCR is connected to a
drain of the PMOS transistor 105. The gate of the PMOS transistor
105 is connected to a VDD pad 101, and its source and backgate are
connected to the I/O. pad 102. Further, although FIG. 2 of Japanese
Patent Laid-Open Application No. 2003-318265 illustrates the ESD
protection circuit where the input circuit 104 is connected to the
VDD pad 101, this illustration would be an erroneous
expression.
[0008] In addition, as the trigger element, the NMOS transistor may
also be used. Japanese Patent Laid-Open Application No. 2003-203985
and its corresponding U.S. Patent Application, i.e. U.S. Pat. No.
6,545,321 disclose an ESD protection circuit having a configuration
in which the NMOS transistor acting as a trigger element is
connected to the gate of N-gate type SCR. In addition, Japanese
Patent Laid-Open Application No. 2006-303110 discloses a
configuration in which the PMOS transistor is used as the trigger
element and also the NMOS transistor is used.
[0009] In addition, as already been disclosed in the reference: M.
Mergens et al., IEEE raps. Device Materi. Reliab. vol. 5, no. 3,
pp. 532-542, September 2005, it is also possible to use diodes
connected in series as the trigger element. FIG. 2 shows a
configuration of the ESD protection circuit having such a
configuration as above. The ESD protection circuit shown in FIG. 2
is constituted by the SCR and the diodes 106 connected in series.
Anode of the SCR is connected to the I/O pad 102 and its cathode is
connected to the VSS pad 103. As the trigger element, the diodes
106 connected in series in a forward direction from the gate of the
SCR toward the VSS pad 103 are used.
[0010] One requirement applied to the ESD protection circuit
consists in the fact that a leakage current at the I/O pad is low
during normal operation. That is, under a condition in which the
VDD pad is kept at the power supply voltage level VDD and the VSS
pad is kept at the ground level VSS, it is preferable that the
leakage current flowed from the I/O pad through the ESD protection
circuit is low. The leakage current in the I/O pad is important in
reduction of a consumption current in the semiconductor integrated
circuit.
[0011] Another requirement applied to the ESD protection circuit
consists in a low trigger voltage in which the SCR starts to
operate during ESD stress condition, in particular, a low trigger
voltage when an ESD stress of positive voltage for the VSS pad is
applied to the I/O pad. A circuit topology using the SCR shows a
tendency that the trigger voltage becomes high when the ESD stress
of positive voltage for the VSS pad is applied to the I/O pad, in
particular. If the trigger voltage is high, it shows a certain
problem because an internal circuit may be damaged.
[0012] However, the aforementioned ESD protection circuit cannot
satisfy these both requirements. For example, although the ESD
protection circuit shown in FIG. 1 can reduce the trigger voltage
of the SCR, it cannot reduce the leakage current of the I/O pad. A
reason why this occurs consists in the fact that a value of leakage
current in the I/O pad 102 when "High" level (i.e. a power supply
voltage level VDD) is applied to the I/O pad 102 is determined by
an off-leakage current I.sub.OFF of the PMOS transistor 105. In
this case, the off-leakage current I.sub.OFF is a drain-source
current I.sub.DS when both a gate-source voltage V.sub.GS and a
backgate-source voltage V.sub.BS of the PMOS transistor 105 are 0V.
With such a configuration as described above, the leakage current
at the I/O pad 102 cannot be reduced to a value less than the
off-leakage current I.sub.OFF of the PMOS transistor 105.
[0013] Even the ESD protection circuit in FIG. 2 can reduce the
trigger voltage of the SCR by reducing the number of the diodes
106. However, the leakage current at the I/O pad 102 is high
because the diodes 106 are connected in a forward direction toward
the ground line (the power source line connected to the VSS pad
103).
[0014] B. Keppcns et al., EOS/ESD Symposium Proceedings, 4B.7, 2004
disclose the ESD protection circuit for satisfying aforementioned
both two requirements. FIG. 3A shows a circuit diagram indicating a
configuration of the ESD protection circuit disclosed in this
document. The ESD protection circuit in FIG. 3A is provided with
N-gate type SCR. The anode of the SCR is connected to the I/O pad
102 and its cathode is connected to the VSS pad 103. A gate G2 of
the SCR is connected to the VDD pad 101 through a resistor R2.
[0015] FIG. 3B is a view for showing a sectional structure of the
semiconductor integrated circuit for realizing the ESD protection
circuit shown in FIG. 3A. The ESD protection circuit shown in FIG.
3A is integrated at the P-type substrate 111 having N-well 112
formed the rein. The P-type substrate 111 is formed with P.sup.+
region 113 and N.sup.+ region 114, and the P.sup.+ region 113 and
N.sup.+ region 114 are connected to the VSS pad 103. In this case,
P.sup.+ region is a region where P-type impurities are doped under
a high concentration and N.sup.+ region is a region where N-type
impurities are doped under a high concentration. In addition, an
N-well region 112 is formed with a P.sup.+ region 115 and an
N.sup.+ region 116. The P.sup.+ region 115 is connected to the I/O
pad 102 and the N.sup.+ region 116 is connected to the VDD pad 101.
The P.sup.+ region 115, N-well 112, P-type substrate 111 and
N.sup.+ region 114 act as a SCR (having PNPN structure). The
P.sup.+ region 113, N.sup.+ region 114, P.sup.+ region 115, and
N.sup.+ region 116 are separated from each other by field oxide
films 117. The resistor of the P-type substrate 111 acts as a
resistor element R1 in FIG. 3A and a resistor of the N-well 112
acts as a resistor element R2.
[0016] A leakage current at the I/O pad 102 is less in the ESD
protection circuit of FIG. 3A because the gate G2 of the SCR is
clamped at the power source voltage level VDD during its normal
operation. In addition, when the ESD stress of positive voltage is
applicd to the I/O pad against the VSS pad 103, the VDD pad 101 is
of a floating condition, so that a forward biasing may easily be
applied between the anode and gate G2 of the SCR. Accordingly, the
ESD protection circuit in FIG. 3A can reduce the trigger voltage of
the SCR.
[0017] However, the ESD protection circuit in FIG. 3A shows a
problem that a pn junction between the P.sup.+ region 115 and
N-well 112 may easily be damaged when an ESD stress of negative
polarity for the VDD pad 101 is applied against the I/O pad 102.
This problem is particularly serious when an area of the pn
junction between the P.sup.+ region 115 and N-well 112 is reduced
so as to reduce a parasitic capacitance of the SCR. Accordingly,
the ESD protection circuit in FIG. 3A cannot be a practical
one.
[0018] As described above, it is believed that it has not been well
known in the art that such a practical technology as one satisfying
the two requirements of reduction of the leakage current at the I/O
pad under the normal operating state and reduction of trigger
voltage when the ESD stress of positive voltage is applied to the
I/O pad with respect to the VSS pad.
SUMMARY OF THE INVENTION
[0019] The semiconductor circuit of the present invention comprises
exemplarily a VDD pad, an I/O pad, a VSS pad, a protection element
arranged between the I/O pad and the VSS pad, and a PMOS transistor
acting as a trigger element for flowing a trigger current in the
protection element. The gate and backgate of the PMOS transistor
are connected to the VDD pad. The aforementioned protection element
is constituted such that the potential at the source of the PMOS
transistor is lower than the potential of the I/O pad due to a
voltage drop generated at the protection element when the
potentials of the VDD pad and I/O pad are kept at the power supply
voltage level.
[0020] In such a semiconductor circuit having such a configuration
as described above, it is possible to reduce the sub-threshold
current flowing through the PMOS transistor under the normal
operating state. A reason why this state can be attained consists
in the fact that the gate-source voltage of the PMOS transistor
becomes a positive voltage because the potential of source of the
PMOS transistor is lower than the potential of the VDD pad due to a
voltage drop generated at the protection element. Thus, the
semiconductor circuit of the present invention can reduce the
leakage current at the I/O pad.
[0021] In addition, the semiconductor circuit of the present
invention has an advantage that a trigger voltage when the ESD
stress of a positive voltage for the VSS pad is applied to the I/O
pad is low. In the case that the ESD stress of a positive voltage
for the VSS pad is applied to the I/O pad, the VDD pad is kept
floating to cause the gate and backgate of the PMOS transistor to
become a floating state. In addition, the ESD stress of a positive
voltage for the VSS pad is applied to the I/O pad to cause the
source potential of the PMOS transistor to become a positive
potential for the VSS pad. Accordingly, the potential of the I/O
pad required for lowering the gate-source voltage of the PMOS
transistor than a threshold voltage V.sub.TH is low. Accordingly,
the trigger voltage when the ESD stress of a positive voltage for
the VSS pad is applied to the I/O pad is reduced.
[0022] Preferably, a SCR is used as the protection element. In this
case, the anode of the SCR is connected to the I/O pad, its cathode
is connected to the VSS pad and its gate is connected to the source
of the PMOS transistor.
[0023] According to the present invention, it is possible to
provide an ESD protection circuit having a low leakage current
under a normal operating state and having a low trigger voltage at
the time of application of the ESD stress.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The above and other exemplary aspects, advantages and
features of the present invention will be more apparent from the
following description of certain exemplary embodiments taken in
conjunction with the accompanying drawings, in which:
[0025] FIG. 1 is a circuit diagram for showing an example of a
configuration of the related art ESD protection circuit;
[0026] FIG. 2 is a circuit diagram for showing another example of a
configuration of the related art ESD protection circuit;
[0027] FIG. 3A is a circuit diagram for showing a still further
example of a configuration of the related art ESD protection
circuit;
[0028] FIG. 3B is a sectional view for realizing the ESD protection
circuit in FIG. 3A;
[0029] FIG. 4A is a circuit diagram for showing a configuration of
the ESD protection circuit of a first embodiment of the present
invention;
[0030] FIG. 4B is a sectional view for showing a sectional
structure of a SCR included in the ESD protection circuit of FIG.
4A;
[0031] FIG. 5A is a graph for indicating an operating
characteristic of the PMOS transistor, in particular, a relation
between the gate-source voltage V.sub.GS and the drain current
I.sub.D;
[0032] FIG. 5B is a graph for indicating an operating point of a
leakage current under a normal operating state in the ESD
protection circuit of FIG. 4A;
[0033] FIG. 6 is a view for indicating an equivalent circuit for
the ESD protection circuit of the first embodiment when the ESD
stress of a positive polarity is applied to the I/O pad with
respect to the VSS pad;
[0034] FIG. 7 is a view for indicating an equivalent circuit for
the ESD protection circuit of the first embodiment when the ESD
stress of a positive polarity for the VDD pad is applied to the I/O
pad;
[0035] FIG. 8A is a circuit diagram for indicating a configuration
of the ESD protection circuit of a second embodiment of the present
invention; and
[0036] FIG. 8B is a sectional view for indicating a sectional
structure of a SCR included in the ESD protection circuit of FIG.
8A.
DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS
First Embodiment
[0037] FIG. 4A is a circuit diagram for showing a configuration of
the ESD protection circuit of a first embodiment of the present
invention. The ESD protection circuit of the first embodiment
comprises an N-gate type SCR 1, the PMOS transistor 2 for a trigger
and a backward diode 3.
[0038] The SCR 1 acts as a protection element for discharging a
load accumulated in the I/O pad 5 when the ESD stress (or surge) of
a positive polarity is applied to the I/O pad 5. In FIG. 4A, the
SCR 1 is equivalently expressed as it comprises NPN transistor Q1
and PNP transistor Q2. The anode of the SCR 1 is connected to the
I/O pad 5 and its cathode is connected to the VSS pad 6. In this
case, the I/O pad 5 is a pad connected to a signal line 22 for
inputting or outputting a signal in respect to an internal circuit
8, and the VSS pad 6 is a pad to which the ground potential VSS is
supplied from an external unit. The VSS pad 6 is connected to a VSS
power supply line 23.
[0039] The PMOS transistor 2 for a trigger has a function for
turning on the SCR 1. The PMOS transistor 2 for a trigger has its
source connected to the gate of the SCR 1, its drain connectcd to
the VSS power supply line 23 (i.e. VSS pad 6) and its gate and
backgate connected to the VDD pad 4. In this case, the VDD pad 4 is
a pad to which the power supply potential VDD is supplied from an
external unit. The VDD pad 4 is connected to the VDD power supply
line 21.
[0040] The backward diode 3 has a function for discharging a load
accumulated in the VSS pad 6 when the ESD stress (or surge) of a
positive polarity for the I/O pad 5 is applied to the I/O pad with
respect to the VSS pad 6. The cathode of backward diode 3 is
connected to the I/O pad 5 and the anode of backward diode 3 is
connected to the VSS pad 6.
[0041] Supplying of the power supply voltage to the internal
circuit 8 is carried out by the VDD power supply line 21 and the
VSS power supply line 23. A power clamp diode 7 is connected
between the VDD power supply line 21 and the VSS power supply line
23. The power clamp diode 7 may act as a protection element between
the VDD pad 4 and the VSS pad 6.
[0042] FIG. 4B is a view for showing a sectional structure of the
SCR 1. The SCR 1 is integrated on a P-type substrate 11 having an
N-well 12 formed thereon. The P-type substrate 11 is formed with
P.sup.+ region 13 and N.sup.+ region 14, and the P.sup.+ region 13
and N.sup.+ region 14 are connected to the VSS pad 6. N.sup.+
region 14 may act as a cathode for the SCR 1. In addition, P.sup.+
region 15 and N.sup.+ region 16 are formed in the N-well 12.
P.sup.+ region 15 is connected to the I/O pad 5, and N.sup.+ region
16 is connected to the source of the PMOS transistor 2 for a
trigger. P.sup.+ region 15 acts as the anode of the SCR and N.sup.+
region 16 acts as a gate. P+ region 13, N.sup.+ region 14, P.sup.+
region 15 and N.sup.+ region are separated from each other by the
field oxide film 17. A resistor R.sub.PSUM of P-type substrate 11
acts as a resistor for applying a bias to NPN transistor Q1, and a
resistor R.sub.NW of N-well 12 acts as a resistor connected between
the gate of the SCR 1 and the base of PNP transistor Q2.
[0043] The ESD protection circuit having such a configuration as
above enables a leakage current at the I/O pad 5 to be reduced
under a normal operating state, and also enables the trigger
voltage to be reduced when the ESD stress of a positive voltage for
the VSS pad 6 is applied to the I/O pad 5. A reason why such an
advantage as above will be described in detail.
[0044] At first, a principle of reduction in leakage current of the
I/O pad 5 under a normal operating state will be described. A
reason why the leakage current at the I/O pad 5 is reduced under
the normal operating condition consists in the fact that the
potential at the source of the PMOS transistor for a trigger is
kept at a lower potential than that of the gate and the backgate of
the PMOS transistor 2 for a trigger (even if the I/O pad 5 is a
power supply voltage level VDD) due to a voltage drop at the pn
junction between the anode and the gate of the SCR 1. The leakage
current at the I/O pad 5 under the normal operating state is mainly
determined by a sub-threshold current at the PMOS transistor 2 for
a trigger (since currents flowing in the SCR 1 and the backward
diodes 3 are quite low as compared with the current flowing at the
PMOS transistor 2 for a trigger, it can be ignored). The
sub-threshold current flowing at the PMOS transistor 2 for a
trigger is decreased in a manner of an exponential function as the
gate-source voltage V.sub.GS and the gate-backgate voltage V.sub.BS
of the PMOS transistor 2 for a trigger are increased. In this case,
the gate-source voltage V.sub.GS and the gate-backgate voltage
V.sub.BS of the PMOS transistor 2 are the potential of the gate and
the potential of the backgate, respectively, when the source is
applied as a reference value. Under the normal operating state, the
gate and the backgate of the PMOS transistor for a trigger are kept
at the power source voltage level VDD and in turn the source of the
PMOS transistor 2 for a trigger is kept at a lower potential than
that of the power source voltage level VDD only by a value of the
voltage drop of the anode-gate (i.e. the emitter/base junction of
PNP transistor Q2) of the SCR 1. In other words, the gate-source
voltage V.sub.GS and the gate-backgate voltage V.sub.BS of the PMOS
transistor 2 for a trigger are increased only by an amount
corresponding to the voltage drop between the anode-gate of the SCR
1. Accordingly, the ESD protection circuit of the embodiment can
extremely decrease the sub-threshold current flowing at the PMOS
transistor 2 for a trigger, i.e. a leakage current at the I/O pad
5.
[0045] The reduction in the leakage current at the ESD protection
circuit of the embodiment would be understood more clearly if it is
compared with that of the ESD protection circuit shown in FIG. 1.
In the ESD protection circuit in FIG. 1, the leakage current of the
I/O pad 102 under the normal operating state coincides with the
sub-threshold current of the PMOS transistor 105 when the
gate-source voltage V.sub.GS and the backgate-source voltage
V.sub.BS are 0 V. In turn, in the ESD protection circuit of the
embodiment is quite low as compared with the sub-threshold current
flowing at the PMOS transistor 105 in the ESD protection circuit in
FIG. 1.
[0046] FIG. 5A and FIG. 5B are graphs for showing a more detailed
illustration of a principle in which a leakage current at the I/O
pad 5 is reduced during normal operation. In the following
description, a "High" level signal is inputted to the I/O pad 5.
That is, it should be noted about a consideration in the case that
the potential of the I/O pad 5 is a power supply voltage level
VDD.
[0047] FIG. 5A is a graph for showing a dependency of a drain
current I.sub.D (a current flowing into the drain of the PMOS
transistor) of the PMOS transistor on the gate-source voltage
V.sub.GS. In the case that the gate-source voltage V.sub.GS is
lower than the threshold voltage V.sub.PTH (<0V), the PMOS
transistor is kept in a high reversing region (a saturation region)
and then a saturated drain current I.sub.D flows. As the
gate-source voltage V.sub.GS becomes higher than the threshold
voltage V.sub.PTH, the PMOS transistor becomes a weak reversing
region and the drain current I.sub.D is decreased in an exponential
function manner as the gate-source voltage V.sub.GS is increased.
In the weak reversing region, the sub-threshold current I.sub.S
determines the drain current I.sub.D. As the gate-source voltage
V.sub.GS becomes further high (in FIG. 5A, as it becomes higher
than a potential V.sub.X (>0)), the drain current I.sub.D is
governed not by the sub-threshold current I.sub.S but by the
backward current I.sub.B of the drain/backgate junction and the
gate oxidization film tunnel current I.sub.G. In this case,
noticing only the sub-threshold current I.sub.S, a voltage where
the sub-threshold current I.sub.S starts to flow is defined as
V.sub.STH.
[0048] In addition, the drain current I.sub.D of the PMOS
transistor is also influenced by the backgate-source voltage
V.sub.BS. More practically, when the backgate-source voltage
V.sub.BS is increased from 0V, the drain current I.sub.D of the
PMOS transistor is decreased. That is, when the backgate-source
voltage V.sub.BS is increased, the sub-threshold current I.sub.S of
the PMOS transistor is lowered.
[0049] In the circuit configuration of the ESD protection circuit
in this embodiment, since the gate and the backgate of the PMOS
transistor for a trigger are connected to a VDD Power source line
21, the backward current I.sub.B and the gate oxidization film
tunnel current I.sub.G contributes as a leakage current between the
VDD pad 4 and the VSS pad 6, but does not contribute to the leakage
current of the I/O pad 5. Accordingly, only the sub-threshold
current I.sub.S of THE PMOS transistor 2 for a trigger contributes
to the leakage current of the I/O pad 5.
[0050] FIG. 5B is a graph for showing operating points of PNP
transistor Q2 of the SCR 1 and the PMOS transistor 2 for a trigger
at the time of normal operating state. X-axis denotes a potential
of N-well 12 (i.e. the drain-source voltage of the PMOS transistor
2 for a trigger) and Y-axis denotes a base current I.sub.PNP of PNP
transistor Q2 and a sub-threshold current I.sub.PMOS of the PMOS
transistor 2 for a trigger.
[0051] Operating points of PNP transistor Q2 and the PMOS
transistor 2 for a trigger become the crossing point between the
graph of the base current I.sub.PNP and the graph of the
sub-threshold current I.sub.PNP because the base current I.sub.PNP
of PNP transistor Q2 and the sub-threshold current I.sub.PMOS of
the PMOS transistor 2 for a trigger are coincided to each other
during normal operation. That is, during normal operation, the
leakage current I.sub.LEAKAGE of the I/O pad 5 is coincided with a
current at the crossing point between the graph of base current
I.sub.PNP and the graph of sub-threshold current I.sub.PMOS.
[0052] In the ESD protection circuit of the embodiment, the
operating point is moved toward a direction where the leakage
current I.sub.LEAKAGE is reduced due to a voltage drop caused by
the emitter-base voltage of PNP transistor Q2. Although it is
certain that a value of the emitter-base voltage is slight (more
typically, several tens mV), it may produce a substantial effect in
which the voltage drop caused by the emitter-base voltage reduces
the leakage current I.sub.LEAKAGE because the sub-threshold current
I.sub.PMOS is decreased in a manner of exponential function in
respect to the gate-source voltage V.sub.GS. More practically, the
leakage current I.sub.LEAKAGE is reduced by one digit due to the
emitter-base voltage of several tens mV. Test production and
evaluation of the ESD protection circuit of the embodiment through
CMOS process of 65 nm showed that the leakage current of 10-13 (A)
or less could be realized through application of the PMOS
transistor 2 for a trigger with V.sub.STH being 0.2 V.
[0053] Subsequently, a principle in which a trigger voltage when an
ESD stress of positive voltage for the VSS pad 6 is applied to the
I/O pad 5 is reduced will be described in reference to the
configuration of the ESD protection circuit of the embodiment. In
regard to the case in which the ESD stress of a positive voltage
for the VSS pad 6 is applied to the I/O pad 5, it should be noticed
that a potential of the VDD pad 4 is a floating one.
[0054] In reference to FIG. 6, when the ESD stress of a positive
voltage for the VSS pad 6 is applied to the I/O pad 5, the gate and
the backgate of the PMOS transistor 2 for a trigger are also a
floating one because the potential of the VDD pad 4 is a floating
one. Accordingly, the potential of the I/O pad 5 required for
making a state in which the PMOS transistor 2 for a trigger is ON
(i.e. a state in which the gate-source voltage V.sub.GS of the PMOS
transistor 2 for a trigger is lower than the threshold voltage
V.sub.TH) is low. Accordingly, it is possible to generate a trigger
current I.sub.TRIG by turning on the PMOS transistor 2 for a
trigger even with a low trigger voltage. Upon flowing of the
trigger current I.sub.TRIG, the SCR 1 starts to operate and the SCR
current I.sub.SCR flows. The SCR current I.sub.SCR flows into the
VSS pad 6 through the SCR 1. With this operation, an electrical
load accumulated in the I/O pad 5 is electrically discharged to the
VSS pad 6.
[0055] Although current I.sub.INT also flows into the VDD power
supply line 21 through a parasitic diode between the source and the
backgate of the PMOS transistor 2 for a trigger, this current
I.sub.INT does not prevent the PMOS transistor 2 from being turned
on and starting an operation of the SCR 1. Since the VDD power
supply line 21 connected to the internal circuit 8 has a sufficient
capacity, a state in which the gate-source voltage V.sub.GS is
lower than the threshold voltage V.sub.TH is kept until the VDD
power source line 21 is charged up, and then the channel current of
the PMOS transistor 2 for a trigger is continued to flow.
[0056] Since channel current in the PMOS transistor 2 for a trigger
becomes a trigger current I.sub.TRIG of the SCR 1, a trigger
voltage of the SCR 1 is determined by dimensions of the PMOS
transistor 2 for a trigger (i.e. a gate length L and a gate width
W), a film thickness T.sub.OX and the threshold voltage V.sub.TH of
the PMOS transistor 2 for a trigger. In this case, the threshold
voltage V.sub.TH is defined as a gate-source voltage V.sub.GS when
the drain-source current I.sub.DS shows a value of -1 .mu.A. As a
result of test manufacturing and evaluation of the ESD protection
circuit of the embodiment through a 65 nm CMOS process, the trigger
voltage of the SCR 1 could be reduced down to 1.8V under the
following conditions.
L=0.2 (.mu.m)
W=10 (.mu.m)
T.sub.OX=1.3 (nm)
V.sub.TH=-0.2 (V)
[0057] In addition, the ESD protection circuit of the embodiment
also has an advantage that it has also a low trigger voltage when
the ESD stress of a positive polarity for the VDD pad 4 is applied.
FIG. 7 is a view for illustrating a principle where such advantage
as above can be attained. In the case that the ESD stress of a
positive polarity for the VDD pad 4 is applied to the I/O pad 5,
current flows from the I/O pad 5 to the VDD power source line 21
through two forward diodes connected in series (i.e. emitter/base
junction of PNP transistor Q2 and source-backgate junction of the
PMOS transistor 2 for a trigger). Accordingly, when it does not
depend on the structure of the PMOS transistor 2 for a trigger and
a potential of about 1.5 V (=approximately 0.7 V.times.2) of
potential of forward bias of the two series-connected diodes occurs
between the I/O pad 5 and the VDD pad 4, the trigger current
I.sub.TRIG flows. Upon flowing of the trigger current I.sub.TRIG,
the SCR 1 starts to operate and the SCR current I.sub.SCR flows.
The SCR current I.sub.SCR flows into the VDD pad 4 through the SCR
1 and the power clamp diode 7. With this operation, the electrical
load accumulated in the I/O pad 5 is dischargcd to the VDD pad 4.
Actually, test production and evaluation of the ESD protection
circuit of the embodiment through a 65 nm CMOS process enabled the
trigger voltage of the SCR 1 to be reduced down to 1.5V without
being dependent on the structure of the PMOS transistor 2 for a
trigger. This value is a value that cannot be obtained by the
related art ESD protection circuit shown in FIGS. 1, 2 and 3.
Second Embodiment
[0058] FIG. 8A is a circuit diagram for showing a configuration of
the ESD protection circuit of a second embodiment of the present
invention. In this embodiment, the PMOS transistor is not used, but
the NMOS transistor is used as a trigger element for triggering the
SCR. Along with this usage, a connecting relation among the SCR,
pad and trigger element is changed from that of the first
embodiment.
[0059] More practically, the ESD protection circuit of the second
embodiment comprises an N-gate type SCR 1, the NMOS transistor 2A
for a trigger, and a backward diode 3. The anode of the SCR 1 is
connected to the VDD pad 4 and its cathode is connected to the I/O
pad 5. The gate of the SCR 1 is connected to the drain of the NMOS
transistor 2A for a trigger. The source of the NMOS transistor 2A
for a trigger is connected to the I/O pad 5 and its gate and
backgate are connected to the VSS pad 6.
[0060] FIG. 8B is a sectional view for showing a connected relation
among the SCR 1 and each of the pads 4 to 6. The P.sup.+ region 13
formed at the p-type substrate 11 is connected to the VSS pad 6 and
the N.sup.+ region 14 is connected to the I/O pad 5. The N.sup.+
region 14 may act as the cathode for the SCR 1. The P.sup.+ region
15 formed at the N-well 12 is connected to the VDD pad 4 and the
N.sup.+ region 16 is connected to the drain of the NMOS transistor
2A for a trigger. The P.sup.+ region 15 may act as an anode for the
SCR 1 and the N.sup.+ region 16 may act as a gate for it.
[0061] According to the configurations shown in FIG. 8A and FIG.
8B, it is possible to reduce a trigger voltage when the ESD stress
of a negative polarity for the VDD pad 4 is applied to the I/O pad
5 due to the same reasons as that for the ESD protection circuit of
the first embodiment. For a detail, since the VSS pad 6 is of a
floating condition, the gate and backgate of the NMOS transistor 2A
for a trigger are also of a floating condition. Thus, an amplitude
of the ESD stress of negative polarity required for making a state
in which NMOS transistor 2A for a trigger is turned on (i.e. the
gate-source voltage V.sub.GS ecomes higher than the threshold
voltage V.sub.TH) is low. Accordingly, the ESD protection circuit
of the second embodiment enables a trigger voltage when the ESD
stress of negative polarity for the VDD pad 4 is applied to the I/O
pad 5 to be lowered.
[0062] In addition, the ESD protection circuit of the second
embodiment enables the leakage current in the ESD protection
circuit to be reduced due to the same principle as that of the
first embodiment by defining a restriction in which a signal level
of a signal inputted or outputted for the I/O pad 5 is always
higher than the ground level VSS (i.e. "Low" level of a signal
inputted or outputted for the I/O pad 5 is defined as a
predetermined potential higher than the ground level VSS). For more
details, according to such an operation as above, since the VSS pad
6 is kept at the ground level VSS during normal operation, the gate
and the backgate of the NMOS transistor 2A for a trigger are also
kept at the ground level VSS. In turn, since the I/O pad 5 is
always kept at a higher potential than the ground level VSS, the
source of the NMOS transistor 2 for a trigger is kept at a higher
potential than the ground level VSS. Accordingly, the gate-source
voltage V.sub.GS of the NMOS for a trigger becomes a negative
voltage. Since a threshold current of the NMOS transistor 2A for a
trigger becomes quite low if the gate-source voltage V.sub.GS is
negative, the leakage current in the ESD protection circuit becomes
quite low. In this way, the ESD protection circuit of the second
embodiment can reduce the leakage current in the ESD protection
circuit by properly operating the semiconductor integrated
circuit.
[0063] Although the embodiments of the present invention have been
described in various manners, it should not be interpreted that the
present invention is restricted to the above-mentioned embodiments.
In particular, although the configuration having P.sup.+ region 13
and N.sup.+ region formed in the P-type substrate 11 has been
indicated, it is also possible to cause P.sup.+ region 13 and
N.sup.+ region 14 to be formed into P-wells. In this case, the
P-wells are formed to be connected adjacent to the N-well 12.
[0064] Further, it is noted that, Applicant's intent is to
encompass equivalents of all claim elements, even if amended later
during prosecution.
* * * * *