U.S. patent application number 12/962546 was filed with the patent office on 2011-03-31 for semiconductor device and manufacturing method of the same.
This patent application is currently assigned to RENESAS ELECTRONICS CORPORATION. Invention is credited to Kazuo KUDO, Takumi SOBA, Hideaki TAMIMOTO, Toru UEGURI.
Application Number | 20110073921 12/962546 |
Document ID | / |
Family ID | 40752112 |
Filed Date | 2011-03-31 |
United States Patent
Application |
20110073921 |
Kind Code |
A1 |
TAMIMOTO; Hideaki ; et
al. |
March 31, 2011 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
Abstract
The bonding time of a metallic ribbon is shortened in the
semiconductor device which connects a lead frame with the bonding
pad of a semiconductor chip with a metallic ribbon. The bottom of
the wedge tool is divided into two by the V-groove at the first
branch and the second branch. In order to do bonding of the Al
ribbon to the source pad of the silicon chip, and the source post
of the lead frame, first, the first branch and second branch of the
wedge tool are contacted by pressure to Al ribbon on the source
pad, and supersonic vibration is applied to it. Subsequently, the
first branch is contacted by pressure to Al ribbon on the source
post, and supersonic vibration is applied to it. Here, since the
width of the first branch is narrower than the width of the source
post, Al ribbon is not joined at the end surface of the width
direction of the source post.
Inventors: |
TAMIMOTO; Hideaki; (Tokyo,
JP) ; SOBA; Takumi; (Tokyo, JP) ; UEGURI;
Toru; (Tokyo, JP) ; KUDO; Kazuo; (Tokyo,
JP) |
Assignee: |
RENESAS ELECTRONICS
CORPORATION
|
Family ID: |
40752112 |
Appl. No.: |
12/962546 |
Filed: |
December 7, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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12334318 |
Dec 12, 2008 |
7863107 |
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12962546 |
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Current U.S.
Class: |
257/288 ;
257/741; 257/773; 257/E23.01; 257/E29.255 |
Current CPC
Class: |
H01L 2224/48465
20130101; H01L 2224/84205 20130101; H01L 2224/85439 20130101; H01L
2924/1306 20130101; H01L 24/03 20130101; H01L 2224/48465 20130101;
H01L 2924/01074 20130101; H01L 2224/45014 20130101; H01L 24/73
20130101; H01L 2224/45144 20130101; H01L 2224/73265 20130101; H01L
2224/8385 20130101; H01L 24/45 20130101; H01L 2224/05554 20130101;
H01L 2224/32245 20130101; H01L 2224/85205 20130101; H01L 2224/29339
20130101; H01L 2224/48247 20130101; H01L 2924/01079 20130101; H01L
2924/014 20130101; H01L 2224/92247 20130101; H01L 2924/01013
20130101; H01L 2224/48247 20130101; H01L 2924/181 20130101; H01L
2224/37124 20130101; H01L 2224/45014 20130101; H01L 2224/45124
20130101; H01L 2224/45144 20130101; H01L 24/95 20130101; H01L
2224/48465 20130101; H01L 2224/73221 20130101; H01L 2924/00011
20130101; H01L 24/37 20130101; H01L 2224/45014 20130101; H01L
23/49524 20130101; H01L 2924/01014 20130101; H01L 24/29 20130101;
H01L 2224/0603 20130101; H01L 2224/78313 20130101; H01L 2924/01028
20130101; H01L 2224/48247 20130101; H01L 2924/00 20130101; H01L
2224/37147 20130101; H01L 2224/48465 20130101; H01L 2224/48739
20130101; H01L 2924/10253 20130101; H01L 2224/05639 20130101; H01L
2224/40245 20130101; H01L 2924/1305 20130101; H01L 2924/1306
20130101; H01L 2224/48739 20130101; H01L 2224/48639 20130101; H01L
2224/45015 20130101; H01L 2224/48639 20130101; H01L 2224/92247
20130101; H01L 2224/73265 20130101; H01L 2224/04042 20130101; H01L
2224/92 20130101; H01L 2924/13091 20130101; H01L 2224/48091
20130101; H01L 24/05 20130101; H01L 2224/85205 20130101; H01L
2924/01006 20130101; H01L 2924/01046 20130101; H01L 2924/01047
20130101; H01L 2224/83801 20130101; H01L 2224/45014 20130101; H01L
2924/01322 20130101; H01L 2224/4007 20130101; H01L 2224/73219
20130101; H01L 2924/01005 20130101; H01L 2924/01022 20130101; H01L
2924/3512 20130101; H01L 2924/00014 20130101; H01L 2924/00
20130101; H01L 2924/206 20130101; H01L 2224/48465 20130101; H01L
2224/45144 20130101; H01L 2924/00012 20130101; H01L 2924/00014
20130101; H01L 2924/00 20130101; H01L 2924/00 20130101; H01L
2224/48091 20130101; H01L 2224/48247 20130101; H01L 2224/32245
20130101; H01L 2924/00 20130101; H01L 2924/00 20130101; H01L
2224/48247 20130101; H01L 2924/13091 20130101; H01L 2924/00
20130101; H01L 2224/48247 20130101; H01L 2924/00 20130101; H01L
2924/00 20130101; H01L 2224/48247 20130101; H01L 2224/45124
20130101; H01L 2224/73265 20130101; H01L 2224/48247 20130101; H01L
2224/84 20130101; H01L 2924/00 20130101; H01L 2924/00 20130101;
H01L 2924/00014 20130101; H01L 2924/01015 20130101; H01L 2224/32245
20130101; H01L 2924/00 20130101; H01L 2924/00 20130101; H01L
2924/00 20130101; H01L 2224/45144 20130101; H01L 2924/00014
20130101; H01L 2924/00 20130101; H01L 2924/00015 20130101; H01L
2224/83 20130101; H01L 2924/00 20130101; H01L 2924/00 20130101;
H01L 2924/00 20130101; H01L 2924/00012 20130101; H01L 2224/48465
20130101; H01L 24/41 20130101; H01L 2924/00011 20130101; H01L
2924/01033 20130101; H01L 2924/01082 20130101; H01L 23/49562
20130101; H01L 2224/85205 20130101; H01L 24/40 20130101; H01L
2924/1305 20130101; H01L 24/84 20130101; H01L 2224/48091 20130101;
H01L 2924/13055 20130101; H01L 2924/01023 20130101; H01L 2224/40091
20130101; H01L 24/85 20130101; H01L 24/48 20130101; H01L 2224/85205
20130101; H01L 24/77 20130101; H01L 2224/37147 20130101; H01L
2924/01029 20130101; H01L 2224/83801 20130101; H01L 2224/45015
20130101; H01L 2224/85207 20130101; H01L 2924/181 20130101; H01L
2224/45144 20130101; H01L 2224/45124 20130101; H01L 2224/92
20130101; H01L 2224/45124 20130101 |
Class at
Publication: |
257/288 ;
257/773; 257/741; 257/E29.255; 257/E23.01 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 23/48 20060101 H01L023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 14, 2007 |
JP |
2007-322808 |
Claims
1-15. (canceled)
16. A semiconductor device, comprising: a chip mounting portion
having an obverse surface, and a reverse surface opposite the
obverse surface; a semiconductor chip having a front surface, a
back surface opposite the front surface, and a first electrode
formed over the front surface, the semiconductor chip being mounted
over the obverse surface of the chip mounting portion; a first lead
arranged near the chip mounting portion; a belt-like connection
material electrically connecting the first electrode and the first
lead; and a sealing body sealing the semiconductor chip and a part
of the first lead; wherein a size of a connection area of the first
electrode and the belt-like connection material is different from a
size of a connection area of the first lead and the belt-like
connection material.
17. A semiconductor device according to claim 16, wherein the
connection area of the first electrode and the belt-like connection
material has a first connection portion and a second connection
portion, wherein the connection area of the first lead and the
belt-like connection material has a third connection portion, and
wherein an area of the first connection portion is equal to an area
of the third connection portion.
18. A semiconductor device according to claim 17, wherein a
distance from the first connection portion to the first lead is
greater than a distance from the second connection portion to the
first lead.
19. A semiconductor device according to claim 17, wherein an area
of the second connection portion is larger than an area of the
first connection portion.
20. A semiconductor device according to claim 17, wherein a total
width of the first and the second connection portions is smaller
than a width of the first electrode in a direction toward the first
lead from the semiconductor chip.
21. A semiconductor device according to claim 17, wherein the first
lead has a first lead post, the belt-like connection material
connecting with the first lead post, and wherein a width of the
third connection portion is smaller than a width of the first lead
post in a direction toward the first lead from the semiconductor
chip.
22. A semiconductor device according to claim 17, wherein a space
is formed between the first connection portion and the second
connection portion.
23. A semiconductor device according to claim 22, wherein the space
is filled with a portion of the sealing body.
24. A semiconductor device according to claim 16, wherein the
belt-like connection material is a metallic ribbon.
25. A semiconductor device according to claim 24, wherein the
metallic ribbon includes Al.
26. A semiconductor device according to claim 16, wherein the
belt-like connection material is a plurality of metallic
ribbons.
27. A semiconductor device according to claim 16, further
comprising: a second lead arranged near the chip mounting portion;
a third lead coupled to the chip mounting portion; a second
electrode formed on the front surface of the semiconductor chip;
and a third electrode formed on the back surface of the
semiconductor chip; wherein the second electrode connects with the
second lead using Au wire.
28. A semiconductor device according to claim 27, wherein the
semiconductor chip is mounted over the obverse surface of the chip
mounting portion with Ag paste.
29. A semiconductor device according to claim 27, wherein an area
of the first electrode is larger than an area of the second
electrode.
30. A semiconductor device according to claim 27, wherein the
sealing body has a first side surface and a second side surface
face opposite the first side surface, and wherein the first and the
second leads are exposed from the first side surface, and the third
lead is exposed from the second side surface.
31. A semiconductor device according to claim 27, wherein a power
MOSFET is formed in the semiconductor chip, and wherein the first
electrode is a source electrode, the second electrode is a gate
electrode, and the third electrode is a drain electrode.
32. A semiconductor device, comprising: a chip mounting portion
having an obverse surface, and a reverse surface opposite the
obverse surface; a semiconductor chip having a front surface, a
back surface opposite the front surface, and a first electrode
formed over the front surface, the semiconductor chip being mounted
over the obverse surface of the chip mounting portion; a first lead
arranged near the chip mounting portion; a belt-like connection
material electrically connecting the first electrode and the first
lead; and a sealing body sealing the semiconductor chip and a
portion of the first lead; wherein a connection portion of the
first electrode and the belt-like connection material has a first
connection portion and a second connection portion, wherein a
connection portion of the first lead and the belt-like connection
material has a third connection portion, and wherein an area of the
first connection portion is equal to an area of the third
connection portion.
33. A semiconductor device according to claim 32, wherein the
second connection portion is positioned between the first and the
third connection portions.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present application claims priority from Japanese patent
application No. 2007-322808 filed on Dec. 14, 2007, the content of
which is hereby incorporated by reference into this
application.
1. FIELD OF THE INVENTION
[0002] The present invention relates to a semiconductor device and
its manufacturing technology, and particularly relates to an
effective technology in the application to the semiconductor device
which connects a lead frame with the bonding pad of the
semiconductor chip sealed in the surface mounting package with a
metallic ribbon.
2. DESCRIPTION OF THE BACKGROUND ART
[0003] Power MOSFET (Metal Oxide Semiconductor Field Effect
Transistor) used for a power control switch, a charge-and-discharge
protection circuit switch, etc. of a portable information device,
and Insulated Gate Bipolar Transistor (IGBT) are sealed in small
surface mounting packages, such as SOP8. For example, the general
structure of publicly known SOP8 where power MOSFET was sealed is
as follows.
[0004] On the die pad part of the lead frame, the semiconductor
chip sealed with mold resin is mounted, where the main surface is
turned upwards. The back surface of the semiconductor chip
constitutes the drain of power MOSFET, and is joined to the die pad
part via electroconductive adhesives, such as Ag paste. The source
pad connected to the source of power MOSFET and the gate pad
connected to the gate electrode are formed in the top layer of the
main surface of the semiconductor chip. The source pad is formed in
the area wider than the gate pad, in order to reduce the on
resistance of power MOSFET. With the same reason, as for the back
surface of the semiconductor chip, the whole surface constitutes
the drain of power MOSFET.
[0005] A plurality of leads which constitute the external
connection terminal of SOP8 are exposed to the outside of mold
resin. These leads consist of a source lead, a drain lead, and a
gate lead. The gate lead is electrically connected with the gate
pad by one Au wire, and the source lead is electrically connected
with the source pad by a plurality of Au wires. The drain lead is
formed in one with the die pad part. The drain lead is electrically
connected with the back surface (drain of power MOSFET) of the
semiconductor chip mounted on this die pad part.
[0006] However, SOP8 of the above structures is difficult to fully
lower the source resistance of power MOSFET. Since the
cross-section area of the Au wire which connects a source lead with
a source pad is small, this is because it is difficult to secure
sufficient connection area to a source pad even if the number of an
Au wire is increased. In this case, since the size of the silicon
chip will also become large when area of the source pad tends to be
enlarged and it is going to connect many Au wires, package size
will become large. Since much time is needed for the bonding of an
Au wire, the problem that the productivity of SOP8 falls is also
generated.
[0007] Then, technology of connecting a source lead with a source
pad is put in practical use in recent years using a metallic ribbon
with flexibility which was described, for example to Japanese
patent laid-open No. 2004-336043 (Patent Reference 1). Although
this metallic ribbon comprises Al foil, Cu foil, etc. whose
thickness is about hundreds .mu.m, for example and the width
changes also with width of a source pad, generally it is around 1
mm. In order to connect a metallic ribbon to a source pad and a
source lead, the wedge-bonding method using supersonic vibration is
used.
[0008] Since the width of the ribbon is quite large compared with
the diameter of an Au wire, there is an advantage of the
above-mentioned metallic ribbon in the ability of at least one
metallic ribbon to secure sufficient connection area to a source
pad. Since a ribbon is constituted from Al cheaper than Au, it is
effective in the material cost of SOP8 being reduced.
[0009] Japanese patent laid-open No. 2006-196629 (Patent Reference
2) is disclosing the improvement technology of the wedge tool used
for connection of the above-mentioned metallic ribbon. A plurality
of trenches or notches are formed in the under surface of the wedge
tool described in this official report along the direction parallel
to the extending direction of the metallic ribbon. Therefore, when
this wedge tool is contacted by pressure to the metallic ribbon
arranged on a semiconductor chip, a part of under surface of the
tool will contact the metallic ribbon. Since excessive ultrasonic
vibration energy can be prevented from being transmitted from the
wedge tool to the front surface of the semiconductor chip by this,
the defect which breakage of a crack, a crack, etc. generates in a
semiconductor chip is reduced. [0010] [Patent Reference 1] Japanese
patent laid-open No. 2004-336043 [0011] [Patent Reference 2]
Japanese patent laid-open No. 2006-196629
SUMMARY OF THE INVENTION
[0012] The present inventor examined the wedge tool used for
connection of the above-mentioned metallic ribbon. FIG. 28A is a
side view showing the neighborhood of a point of the wedge tool
which the present inventor examined, and FIG. 28B is the plan view
which observed the point of this wedge tool from the lower part. Al
ribbon was used as a metallic ribbon and the silicon chip with
which power MOSFET was formed was used as a semiconductor chip.
[0013] As shown in FIG. 28A, the ribbon guide 14 is attached to one
side surface of the wedge tool 18, and the Al ribbon 10 passing
through the inside of this ribbon guide 14 is sent out to the point
of the wedge tool 18. The cutter 15 which cuts the Al ribbon 10
sent out to the point of the wedge tool 18 is attached to another
side surface of the wedge tool 18 so that up-and-down motion is
possible. The reference 3 in a figure is the silicon chip with
which power MOSFET was formed, 19D is the die pad part on which
this silicon chip 3 was mounted, and 19S is a source lead.
[0014] As shown in FIG. 28B, the bottom of the wedge tool 18 is a
flat surface which has a rectangular plane form. This bottom is
formed so that the length (f) of the shorter side may become
narrower than the width (c) of the source lead 19S shown in FIG.
28A.
[0015] Bonding of the Al ribbon 10 is done to the silicon chip 3
and the source lead 19S using the above-mentioned wedge tool 18.
First, as shown in FIG. 29, the point of the Al ribbon 10 sent out
from the ribbon guide 14 is positioned on the source pad 7 of the
silicon chip 3. Then, the bottom of the wedge tool 18 is contacted
by pressure to the Al ribbon 10, and supersonic vibration is
applied. Hereby, the Al ribbon 10 of the region adjacent to the
bottom of the wedge tool 18 is joined to the front surface of the
source pad 7.
[0016] Next, as shown in FIG. 30, after moving the wedge tool 18,
the bottom is contacted by pressure to the Al ribbon 10 once again,
and supersonic vibration is applied. Hereby, the Al ribbon 10 of
the region adjacent to the bottom of the wedge tool 18 is joined to
the front surface of the source pad 7. Thus, the connection area of
the Al ribbon 10 and the source pad 7 is securable by doing wedge
bonding of the Al ribbon 10 at two places of the source pad 7.
[0017] Next, as shown in FIG. 31, after moving the wedge tool 18
further and positioning the center of the bottom at the center of
the source lead 19S, the bottom of the wedge tool 18 is contacted
by pressure to the Al ribbon 10 on the source lead 19S, and
supersonic vibration is applied to it. Hereby, the Al ribbon 10 of
the region adjacent to the bottom of the wedge tool 18 is joined to
the front surface of the source lead 19S. However, since the bottom
of the wedge tool 18 is formed more narrowly than the width of the
source lead 19S as shown in FIG. 28B, the Al ribbon 10 is not
joined to the end surface of the source lead 19S.
[0018] Next, as shown in FIG. 32, on the end portion of the source
lead 19S, the cutter 15 is positioned and is descended. The Al
ribbon 10 of a region which is not joined to the source lead 19S is
cut by this, and the work which connects the Al ribbon 10 with the
source pad 7 and the source lead 19S is completed.
[0019] However, to use the above wedge tools 18, it is necessary to
secure the connection area of the Al ribbon 10 and the source pad
7. Therefore, since bonding of the Al ribbon 10 must be done at two
places of the source pad 7, much time is needed for bonding.
[0020] Ultrasonic vibration energy required for the bonding of the
Al ribbon 10 is larger than ultrasonic vibration energy required
for the bonding of an Au wire. Therefore, since excessive
ultrasonic vibration energy will travel to electroconductive
adhesives, such as Ag paste which intervenes between the silicon
chip 3 and the die pad part 19D, when bonding of the Al ribbon 10
is done at two places of the source pad 7, there is a possibility
that breakage of a crack, a crack, etc. may generate also in
electroconductive adhesive.
[0021] As the measure, as shown, for example in FIG. 33, area of
the bottom of the wedge tool 18 tends to be enlarged and it is
going to secure the connection area of the Al ribbon 10 and the
source pad 7 with 1 time of bonding. Then, as shown in FIG. 34,
when bonding of the Al ribbon 10 is done to the front surface of
the source lead 19S whose width is narrower than the source pad 7,
the Al ribbon 10 will be joined to the whole front surface of the
source lead 19S. Therefore, the problem that the excessive Al
ribbon 10 cannot peel from the front surface of the source lead 19S
even if the cutter 15 cuts the Al ribbon 10 of the end portion of
the source lead 19S generates.
[0022] A purpose of the present invention is to provide the
technology in which the bonding time of a metallic ribbon can be
shortened in the semiconductor device which connects a lead frame
with the bonding pad of a semiconductor chip with a metallic
ribbon.
[0023] Another purpose of the present invention is in providing the
technology which can suppress the drop of a manufacturing yield and
reliability resulting from the excessive ultrasonic vibration
energy applied at the time of the bonding of a metallic ribbon in
the semiconductor device which connects the bonding pad of a
semiconductor chip and lead frame with a metallic ribbon.
[0024] The above-described and the other purposes and novel
features of the present invention will become apparent from the
description herein and accompanying drawings.
[0025] Of the inventions disclosed in the present application,
typical ones will next be summarized briefly.
[0026] The semiconductor device of the present invention
comprises:
[0027] a lead frame having a die pad part and a first lead arranged
near the die pad part;
[0028] a semiconductor chip mounted over the die pad part;
[0029] a metallic ribbon electrically connecting a first pad formed
in a front surface of the semiconductor chip, and the first lead;
and
[0030] a resin sealing the semiconductor chip, the first lead, and
the metallic ribbon;
[0031] wherein
[0032] the metallic ribbon is connected to the first pad in a first
junction and a second junction of a front surface of the first pad;
and
[0033] a connection area of the metallic ribbon and the first pad
in the first junction differs from a connection area of the
metallic ribbon and the first pad in the second junction.
[0034] The manufacturing method of the semiconductor device of the
present invention comprises the steps of:
[0035] (a) providing a lead frame which has a die pad part, and a
first lead arranged near the die pad part;
[0036] (b) providing a semiconductor chip in which a first pad is
formed in a front surface;
[0037] (c) mounting the semiconductor chip over the die pad
part;
[0038] (d) electrically connecting one end of a metallic ribbon to
a front surface of the first pad, and electrically connecting the
other end of the metallic ribbon to a front surface of the first
lead by a wedge-bonding method using supersonic vibration; and
[0039] (e) sealing the semiconductor chip, the first lead, and the
metallic ribbon with a resin;
[0040] wherein in the step (d), a point of a wedge tool which
applies the supersonic vibration to the metallic ribbon over an
each front surface of the first pad and the first lead is branched
by a long groove extending in a first direction which intersects
perpendicularly with a direction which tends toward the first lead
from the first pad.
[0041] Al ribbon as used in the present invention means a beltlike
connection material which comprised a conductive material which
uses Al as a principal component. Usually, Al ribbon is installed
in a bonding device in the state where it was wound around the
spool. There are ultrasonic jointing and laser jointing as a method
which connects Al ribbon to a lead or a pad. Since Al ribbon is
very thin, when connecting it with a lead or a pad, the length and
the loop shape can be set up arbitrarily.
[0042] Advantages achieved by some of the most typical aspects of
the invention disclosed in the present application will be briefly
described below.
[0043] In the semiconductor device which connects a lead frame with
the bonding pad of a semiconductor chip with a metallic ribbon, it
becomes possible to shorten the bonding time of a metallic
ribbon.
[0044] In the semiconductor device which connects a lead frame with
the bonding pad of a semiconductor chip with a metallic ribbon, it
becomes possible to suppress the drop of a manufacturing yield and
reliability resulting from the excessive ultrasonic vibration
energy applied at the time of the bonding of a metallic ribbon.
BRIEF DESCRIPTION OF THE DRAWINGS
[0045] FIG. 1 is a plan view showing the appearance of the
semiconductor device which is the 1 embodiment of the present
invention;
[0046] FIG. 2 is a side view showing the appearance of the
semiconductor device which is the 1 embodiment of the present
invention;
[0047] FIG. 3 is a plan view showing the internal structure of the
semiconductor device which is the 1 embodiment of the present
invention;
[0048] FIG. 4 is the cross-sectional view which took along the A-A
line of FIG. 3;
[0049] FIG. 5 is the cross-sectional view which took along the B-B
line of FIG. 3;
[0050] FIG. 6 is a principal part cross-sectional view showing
power MOSFET formed in the silicon chip;
[0051] FIG. 7 is a plan view showing the conducting film of the top
layer including a source pad, a gate pad, and gate wiring and the
lower layer gate electrode which were formed in the silicon
chip;
[0052] FIG. 8 is a flow diagram showing the manufacturing process
of the semiconductor device which is the 1 embodiment of the
present invention;
[0053] FIG. 9 is a principal part cross-sectional view showing the
manufacturing method of the semiconductor device which is the 1
embodiment of the present invention;
[0054] FIG. 10A is a side view showing the neighborhood of a point
of the wedge tool with which the wedge bonder used for the bonding
of Al ribbon was equipped, and FIG. 10B is the plan view which
observed the point of this wedge tool from the lower part;
[0055] FIG. 11 is a principal part cross-sectional view showing the
manufacturing method of the semiconductor device following FIG.
9;
[0056] FIG. 12 is a principal part cross-sectional view showing the
manufacturing method of the semiconductor device following FIG.
11;
[0057] FIG. 13 is a principal part cross-sectional view showing the
manufacturing method of the semiconductor device following FIG.
12;
[0058] FIG. 14A is a side view showing the neighborhood of a point
of the wedge tool used in other embodiment of the present
invention, and FIG. 14B is the plan view which observed the point
of this wedge tool from the lower part;
[0059] FIG. 15 is a principal part cross-sectional view showing the
manufacturing method of the semiconductor device which is other
embodiment of the present invention;
[0060] FIG. 16 is a principal part cross-sectional view showing the
manufacturing method of the semiconductor device following FIG.
15;
[0061] FIG. 17 is a principal part cross-sectional view showing the
manufacturing method of the semiconductor device following FIG.
16;
[0062] FIG. 18 is a plan view showing the internal structure of the
semiconductor device which is other embodiment of the present
invention;
[0063] FIG. 19 is a principal part perspective view showing the
manufacturing method of the semiconductor device which is other
embodiment of the present invention;
[0064] FIG. 20 is a principal part perspective view showing the
manufacturing method of the semiconductor device following FIG.
19;
[0065] FIG. 21 is a principal part perspective view showing the
manufacturing method of the semiconductor device which is other
embodiment of the present invention;
[0066] FIGS. 22 and 23 are perspective views of the wedge tool used
in other embodiment of the present invention;
[0067] FIG. 24A is a side view showing the neighborhood of a point
of the wedge tool used in other embodiment of the present
invention, and FIG. 24B is the plan view which observed the point
of this wedge tool from the lower part;
[0068] FIG. 25 is a principal part cross-sectional view showing the
manufacturing method of the semiconductor device which is other
embodiment of the present invention;
[0069] FIGS. 26 and 27 are side views showing the neighborhood of a
point of the wedge tool used in other embodiment of the present
invention;
[0070] FIG. 28A is a side view showing the neighborhood of a point
of the wedge tool which the present inventor examined, and FIG. 28B
is the plan view which observed the point of this wedge tool from
the lower part;
[0071] FIG. 29 is a principal part cross-sectional view showing the
manufacturing method of the semiconductor device which the present
inventor examined;
[0072] FIG. 30 is a principal part cross-sectional view showing the
manufacturing method of the semiconductor device following FIG.
29;
[0073] FIG. 31 is a principal part cross-sectional view showing the
manufacturing method of the semiconductor device following FIG.
30;
[0074] FIG. 32 is a principal part cross-sectional view showing the
manufacturing method of the semiconductor device following FIG.
31;
[0075] FIG. 33 is a principal part cross-sectional view showing
another example of the manufacturing method of the semiconductor
device which the present inventor examined; and
[0076] FIG. 34 is a principal part cross-sectional view showing the
manufacturing method of the semiconductor device following FIG.
33.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0077] Hereafter, embodiments of the invention are explained in
detail based on drawings. In all the drawings for describing the
embodiments, members of a like function will be identified by like
reference numerals in principle and overlapping descriptions will
be omitted.
[0078] Al ribbon as used in following embodiments means a beltlike
connection material which comprised a conductive material which
uses Al as a principal component. Usually, Al ribbon is installed
in a bonding device in the state where it was wound around the
spool. Since Al ribbon is very thin, when connecting it with a lead
or a pad, it can set up length and loop shape arbitrarily.
[0079] There are some which are called a clip as a connection
material similar to Al ribbon. This forms beforehand the thin metal
plate which consists of a Cu alloy, Al, etc. to predetermined loop
shape and predetermined length. When connecting this to a lead or a
pad, while placing the one end on a lead, the other end is placed
on a pad. A clip and a lead, and a clip and a pad are connected
simultaneously. As a connection type, there are a soldering joint,
Ag paste junction, ultrasonic jointing, etc.
[0080] The ribbon as used in the present invention means the
connection material including the above-mentioned clip. The ribbon
which can set up length and loop shape arbitrarily according to a
lead, the area of a pad, or the distance of a lead and a pad is
more preferred than the clip with which length and loop shape were
decided beforehand.
Embodiment 1
[0081] The semiconductor device of this embodiment is applied to
"SOP8" which is a kind of a small surface mounting package. FIG. 1
is a plan view showing the appearance of SOP8 of this embodiment,
FIG. 2 is a side view showing the appearance of this SOP8, FIG. 3
is a plan view showing the internal structure of this SOP8, FIG. 4
is the cross-sectional view which took along the A-A line of FIG.
3, and FIG. 5 is the cross-sectional view which took along the B-B
line of FIG. 3.
[0082] The outer lead portion of the eight leads 4 which constitute
the external connection terminal of SOP8 is exposed to the outside
of the mold resin 2 which consists of epoxy system resin to which
impregnation of the silicon filler was done. Among the leads 4
shown in FIG. 1, the No. 1 lead to the No. 3 lead is a source lead,
the No. 4 lead is a gate lead, and the No. 5 lead to the No. 8 lead
is a drain lead.
[0083] The silicon chip 3 is sealed inside the mold resin 2. The
plane size of the silicon chip 3 is long side.times.shorter
side=3.9 mm.times.2.2 mm, for example. Power MOSFET used, for
example for a power control switch, a charge-and-discharge
protection circuit switch, etc. of a portable information device is
formed in the main surface of the silicon chip 3. On the die pad
part 4D formed in one with the four leads 4 (the No. 5 lead-the No.
8 lead) which constitute a drain lead, the silicon chip 3 is
mounted, where the main surface is turned upwards. The die pad part
4D and the lead 4 (the No. 1 lead-the No. 8 lead) of eight consist
of a Cu or Fe--Ni alloy.
[0084] As shown in FIG. 3, the source pad (source electrode) 7 and
the gate pad 8 are formed in the front surface of the silicon chip
3. The lead 4 (the No. 1 lead-the No. 3 lead) of three which
constitutes a source lead is connected inside the mold resin 2.
This connected portion (it is hereafter called the source post 4P)
and the source pad 7 are electrically connected by the Al ribbon
10. The Al ribbon 10 comprises Al foil of about 1 mm wide and about
0.1 mm thick. On the other hand, the lead 4 (the No. 4 lead) of one
which constitutes a gate lead, and the gate pad 8 are electrically
connected by one Au wire 11. The source pad 7 and the gate pad 8
are constituted by the conducting film which was formed in the top
layer of the silicon chip 3 and which makes an Al film a main body
as is mentioned later. The source pad 7 comprises an area wider
than the gate pad 8, in order to reduce the on resistance of power
MOSFET.
[0085] The back surface of the silicon chip 3 constitutes the drain
of power MOSFET, and is joined to the upper surface of the die pad
part 4D via Ag paste 5. In order to reduce the on resistance of
power MOSFET, as for the back surface of the silicon chip 3, the
whole surface constitutes the drain of power MOSFET.
[0086] FIG. 6 is a principal part cross-sectional view showing
trench gate type n channel power MOSFET formed in the
above-mentioned silicon chip 3. n.sup.- type single crystal silicon
layer 21 is formed in the main surface of n.sup.+ type single
crystal silicon substrate 20 by the epitaxial grown method. n.sup.+
type single crystal silicon substrate 20 and n.sup.- type single
crystal silicon layer 21 constitute the drain of power MOSFET.
[0087] The p type well 22 is formed in a part of n.sup.- type
single crystal silicon layer 21. The silicon oxide film 23 is
formed in a part of front surface of n.sup.- type single crystal
silicon layer 21, and a plurality of trenches 24 are formed in
other parts. The region covered with the silicon oxide film 23
among the front surfaces of n.sup.- type single crystal silicon
layer 21 constitutes an isolation region, and the region in which
the trench 24 was formed constitutes the element formation region
(active region). Although illustration is not done, the plane forms
of the trench 24 are polygons, such as a quadrangle, a hexagon, and
an octagon, or a stripe extending to one way.
[0088] The silicon oxide film 25 which constitutes the gate oxide
film of power MOSFET is formed in the bottom and side wall of the
trench 24. In the inside of the trench 24, the polycrystalline
silicon film 26A which constitutes the gate electrode of power
MOSFET is embedded. On the other hand, the gate drawing electrode
26B which consists of a polycrystalline silicon film deposited at
the same step as the polycrystalline silicon film 26A which
constitutes the above-mentioned gate electrode is formed in the
upper part of the silicon oxide film 23. The gate electrode
(polycrystalline silicon film 26A) and the gate drawing electrode
26B are electrically connected in the region which is not
illustrated.
[0089] The p.sup.- type semiconductor region 27 shallower than the
trench 24 is formed in n.sup.- type single crystal silicon layer 21
of an element formation region. This p.sup.- type semiconductor
region 27 constitutes the channel layer of power MOSFET. The p type
semiconductor region 28 where impurity concentration is higher than
the p.sup.- type semiconductor region 27 is formed in the upper
part of the p.sup.-type semiconductor region 27, and the n.sup.+
type semiconductor region 29 is further formed in the upper part of
the p type semiconductor region 28. The p type semiconductor region
28 constitutes the punch through stopper layer of power MOSFET, and
the n.sup.+ type semiconductor region 29 constitutes the
source.
[0090] The two-layer silicon oxide films 30 and 31 are formed in
the upper part of the element formation region in which
above-mentioned power MOSFET was formed, and the upper part of the
isolation region in which the gate drawing electrode 26B was
formed. The connection hole 32 which penetrates the silicon oxide
films 31 and 30, the p type semiconductor region 28, and the
n.sup.+ type semiconductor region 29, and reaches the p.sup.- type
semiconductor region 27 is formed in the element formation region.
The connection hole 33 which penetrates the silicon oxide films 31
and 30 and reaches the gate drawing electrode 26B is formed in the
isolation region.
[0091] The source pad 7 and the gate wiring 34 which consist of a
laminated film of a thin TiW (titanium tungsten) film and a thick
Al film are formed in the upper part of the silicon oxide film 31
including the inside of the connection holes 32 and 33. The source
pad 7 formed in the element formation region is electrically
connected to the source (n.sup.+ type semiconductor region 29) of
power MOSFET through the connection hole 32. The p.sup.+ type
semiconductor region 35 for doing ohmic contact of the source pad 7
and the p.sup.- type semiconductor region 27 is formed in the
bottom of this connection hole 32. The gate wiring 34 formed in the
isolation region is connected to the gate electrode
(polycrystalline silicon film 26A) of power MOSFET via the gate
drawing electrode 26B of the lower part of the connection hole
33.
[0092] The end of the Al ribbon 10 is electrically connected to the
source pad 7 by the wedge-bonding method. As for the source pad 7,
when doing bonding of the Al ribbon 10, in order to ease the impact
power MOSFET is shocked, it is desirable to make thickness in the
upper part of the silicon oxide films 32 and 33 more than 3
.mu.m.
[0093] FIG. 7 is a plan view showing the conducting film of the top
layer including the source pad 7, the gate pad 8, and the gate
wiring 34 and the lower layer gate electrode (polycrystalline
silicon film 26A) which were formed in the silicon chip 3. The gate
wiring 34 is electrically connected to the gate pad 8, and the
source pad 7 is electrically connected to Al wiring 36. Al wiring
37 and 38 is formed in the outer peripheral part of the silicon
chip 3. The gate pad 8 and Al wiring 36, 37, and 38 comprise a
conducting film (laminated film of a TiW film and an Al film) of
the same layer as the source pad 7 and the gate wiring 34. As for
the actual silicon chip 3, since the gate wiring 34 and Al wiring
36, 37, and 38 are covered with the surface protection film which
is not illustrated, only the source pad 7 and the gate pad 8 have
exposed to the front surface of the silicon chip 3 among the
above-mentioned conducting films of the top layer. In the example
shown in FIG. 7, since the plane form of the trench 24 in which a
gate electrode (polycrystalline silicon film 26A) is formed was
made into the quadrangle, the plane form of the gate electrode
(polycrystalline silicon film 26A) also constitutes a
quadrangle.
[0094] Next, the manufacturing method of SOP8 of this embodiment is
explained. FIG. 8 is a flow diagram showing the manufacturing
process of SOP8. First, in order to manufacture SOP8, after forming
power MOSFET (refer to FIG. 6) in a silicon wafer using well-known
art, dicing of this silicon wafer is done and the silicon chip 3 is
obtained. The lead frame in which the lead 4, the die pad part 4D,
and the source post 4P were formed is prepared. The lead frame
consists of a Cu or Fe--Ni alloy. In order to improve adhesive
strength with the Al ribbon 10 and Au wire 11, the plated layer of
the three-layer structure (nickel/Pd/Au) which stacked the Ni film
and the Au film to the upper and lower sides of Pd film is formed
in the front surface, for example.
[0095] Next, as shown in FIG. 9, the silicon chip 3 is mounted on
the die pad part 4D of the lead frame using Ag paste 5 (die
bonding). When doing wedge bonding of the Al ribbon 10 to the front
surface of the silicon chip 3 as it may mention later, big
ultrasonic vibration energy is applied not only to the front
surface of the silicon chip 3 but to Ag paste 5 which intervenes
between the silicon chip 3 and the die pad part 4D. Therefore, in
order to prevent originating in this ultrasonic vibration energy
and a crack occurring in Ag paste 5, it is desirable to use
selectively Ag paste 5 with the optimal elastic modulus (Pa). The
reference c of FIG. 9 shows the width of the source post 4P formed
in the lead frame, and the reference d shows the width of the
source pad 7 along the width direction of the source post 4P.
[0096] Next, bonding of the Al ribbon 10 is done to the source pad
7 of the silicon chip 3, and the source post 4P of the lead frame
by the following methods.
[0097] FIG. 10A is a side view showing the neighborhood of a point
of the wedge tool with which the wedge bonder used for the bonding
of the Al ribbon 10 was equipped, and FIG. 10B is the plan view
which observed the point of the wedge tool from the lower part.
[0098] As shown in FIG. 10A, the ribbon guide 14 is attached to one
side surface of the wedge tool 12, and the Al ribbon 10 passing
through the inside of this ribbon guide 14 is sent out to the point
of the wedge tool 12. The cutter 15 which cuts the Al ribbon 10
sent out to the point of the wedge tool 12 is attached to another
side surface of the wedge tool 12 so that up-and-down motion is
possible.
[0099] The point of the wedge tool 12 has branched to two by
V-groove 13. When equipping a wedge bonder with the wedge tool 12,
it equips so that the extending direction of this V-groove 13 may
intersect perpendicularly to the width (c) direction of the source
post 4P shown in FIG. 9.
[0100] As shown in FIG. 10B, the bottom of the wedge tool 12
sandwiches the above-mentioned V-groove 13, and is divided into two
at the first branch 12A and the second branch 12B in which each has
a rectangular plane form. Here, the bottom of the wedge tool 12 is
formed so that the width (e) of the direction which intersects
perpendicularly with the extending direction of V-groove 13 may be
the same as that (d) of the source pad 7 shown in FIG. 9 or may
become narrow slightly from this width (d). The width (a) of the
first branch 12A in this width (d) direction is formed so that it
may become narrower than the width (c) of the source post 4P shown
in FIG. 9. Although the width (b) of the second branch 12B is
suitably changed according to the size of the silicon chip 3, i.e.,
the width of the source pad 7, (d), let it be a thing wider than
the width (a) of the first branch 12A here.
[0101] Bonding of the Al ribbon 10 is done to the source pad 7 and
the source post 4P using the above-mentioned wedge tool 12. First,
as shown in FIG. 11, the point of the Al ribbon 10 sent out from
the ribbon guide 14 is positioned on the source pad 7 of the
silicon chip 3. Then, the first branch 12A and the second branch
12B of the wedge tool 12 are simultaneously contacted by pressure
to the Al ribbon 10, and the supersonic vibration of the energy of
about several W is applied. Hereby, the Al ribbon 10 of the region
which is in contact with the first branch 12A and the second branch
12B is joined to the front surface of the source pad 7. The Al
ribbon 10 of the lower part of V-groove 13 does not contact the
bottom of the wedge tool 12, but loses slightly (about 8
.mu.m.about.25 .mu.m) touch with the front surface of the source
pad 7.
[0102] Next, as shown in FIG. 12, the wedge tool 12 is moved and
the center of the width (a) of the first branch 12A is positioned
at the center of the width (c) of the source post 4P. Then, the
first branch 12A is contacted by pressure to the Al ribbon 10 on
the source post 4P, and the supersonic vibration of the energy of
about several W is applied. Hereby, the Al ribbon 10 of the region
which is in contact with the first branch 12A is joined to the
front surface of the source post 4P. However, since the width (a)
of the first branch 12A is narrower than the width (c) of the
source post 4P, the Al ribbon 10 is not joined by the end surface
of the width (c) direction of the source post 4P.
[0103] Next, as shown in FIG. 13, on the end portion of the source
post 4P, the cutter 15 is positioned and is descended. The Al
ribbon 10 of a region which is not joined to the source post 4P is
cut by this, and bonding of the Al ribbon 10 is done to the source
pad 7 and the source post 4P, respectively.
[0104] Next, although illustration is omitted, bonding of Au wire
11 is done to the gate pad 8 of the silicon chip 3, and the lead 4
(the No. 4 lead which constitutes a gate lead) by the ball-bonding
method of common knowledge using heat and an ultrasonic wave,
respectively. Then, the silicon chip 3 (and the die pad part 4D,
the source post 4P, the Al ribbon 10, Au wire 11, the inner lead
part of the lead 4) is sealed with the mold resin 2 using a metal
mold. Then, marking of a product name, the manufacturing number,
etc. is done to the front surface of the mold resin 2. Next, the
unwanted part of the lead 4 exposed to the outside of the mold
resin 2 is cut and removed, and the outer lead portion of the lead
4 is formed in the shape of a gull wing. Then, SOP8 of this
embodiment shown in FIG. 1-FIG. 5 is completed by passing through
the sorting process which distinguishes the good and the defect of
a product.
[0105] Here, the wedge tool 12 whose width (b) of the second branch
12B is wider than the width (a) of the first branch 12A was used.
However, when the width of the silicon chip 3, i.e., the width of
the source pad 7, (d) is narrow, as shown in FIGS. 14A and 14B, the
wedge tool 12 whose width (b) of the second branch 12B is narrower
than the width (a) of the first branch 12A is used.
[0106] Bonding of the Al ribbon 10 is done to the source pad 7 and
the source post 4P using this wedge tool 12. First, as shown in
FIG. 15, the Al ribbon 10 is joined to the front surface of the
source pad 7 by contacting by pressure simultaneously the first
branch 12A and the second branch 12B of the wedge tool 12 to the Al
ribbon 10 on the source pad 7, and applying supersonic vibration.
Next, as shown in FIG. 16, the Al ribbon 10 is joined to the front
surface of the source post 4P by contacting the first branch 12A by
pressure to the Al ribbon 10 on the source post 4P, and applying
supersonic vibration to it. Next, as shown in FIG. 17, the cutter
15 cuts the end portion 10 of the source post 4P, i.e., Al ribbon
of a region which is not joined to the source post 4P.
[0107] Thus, when doing bonding of the Al ribbon 10 to the source
pad 7 and the source post 4P, the wedge tool 12 which has the
bottom divided into the first branch 12A and the second branch 12B
is used. Hereby, it becomes possible to join the Al ribbon 10 to
the source pad 7 with 1 time of bonding, securing the junction area
of the source pad 7 and the Al ribbon 10.
[0108] By this, the ultrasonic vibration energy applied to Ag paste
5 which intervenes between the silicon chip 3 and the die pad part
4D can be reduced compared with the conventional technology which
joins the Al ribbon 10 to the source pad 7 with 2 times of bonding.
Therefore, the crack generation of Ag paste 5 resulting from this
ultrasonic vibration energy is suppressed, and the joining
reliability of the silicon chip 3 and the die pad part 4D improves.
Since the ultrasonic vibration energy applied to silicon chip 3
itself is also reduced, the damage applied to the silicon chip 3 is
also reduced.
[0109] Bonding time can be shortened compared with the conventional
technology which joins the Al ribbon 10 to the source pad 7 with 2
times of bonding. Therefore, the productivity of SOPS can improve
and the manufacturing cost can be reduced.
Embodiment 2
[0110] FIG. 18 is a plan view showing the internal structure of
SOP8 of this embodiment. There is the feature of this SOP8 in the
source pad 7 being connected with the source post 4P by a plurality
of Al ribbons 10. Although the number of the Al ribbon 10 may be
three or more, the example connected by the two Al ribbons 10 is
shown here.
[0111] By the kind or generation, SOP8 differs in the size of the
silicon chip 3, and it differs also in the size of the source pad 7
in connection with this. Therefore, when two or more kinds of Al
ribbons 10 in which width differs are prepared each time according
to the size of the source pad 7, management of the Al ribbon 10
will become complicated. On the other hand, when preparing the Al
ribbon 10 with comparatively narrow width of one kind and changing
the connection number of the Al ribbon 10 according to the size of
the source pad 7, management of the Al ribbon 10 will not become
complicated.
[0112] Thus, the junction area of the source pad 7 and the Al
ribbon 10 becomes large by connecting the source pad 7 with the
source post 4P by a plurality of Al ribbons 10. Therefore, source
resistance can be made smaller. Bonding time can be shortened in
this case by doing bonding of a plurality of Al ribbons 10
simultaneously with the one bonding tool 12.
[0113] The wedge tool 12 which has the bottom divided into the
first branch 12A and the second branch 12B on both sides of
V-groove 13 is prepared like the Embodiment 1 also in this case.
And first, as shown in FIG. 19, the first branch 12A and the second
branch 12B of the wedge tool 12 are simultaneously contacted by
pressure to the Al ribbon 10, and ultrasonic vibration energy is
applied. And bonding of the two Al ribbons 10 is simultaneously
done to the front surface of the source pad 7. Next, as shown in
FIG. 20, the first branch 12A of the wedge tool 12 is contacted by
pressure to the Al ribbon 10, ultrasonic vibration energy is
applied, and bonding of the two Al ribbons 10 is simultaneously
done to the front surface of the source post 4P. Hereby, the same
effect as the Embodiment 1 can be acquired. In FIG. 19 and FIG. 20,
illustration of the ribbon guide 14 and the cutter 15 is
omitted.
Embodiment 3
[0114] Generally, in the manufacturing process of a resin molded
type semiconductor device like SOPS, the lead frame which formed a
plurality of die pad parts 4D as shown in FIG. 21 is used. Here,
lead frame LF which formed the three die pad parts 4D is shown.
[0115] When connecting the source post 4P with the source pad 7 of
the three silicon chips 3 mounted in such lead frame LF by the Al
ribbon 10, as shown in FIG. 21, the three wedge tools 12 are
connected. Bonding time can be shortened by connecting the Al
ribbon 10 to the source pad 7 of the three silicon chips 3
simultaneously. In FIG. 21, illustration of the ribbon guide 14 and
the cutter 15 is omitted.
[0116] Also in this case, the wedge tool 12 which has the bottom
divided into the first branch 12A and the second branch 12B on both
sides of V-groove 13 is used like the Embodiment 1. Hereby, since
the Al ribbon 10 is joinable to each source pad 7 of the three
silicon chips 3 with 1 time of bonding, the same effect as the
Embodiment 1 can be acquired.
[0117] FIG. 22 is a perspective view showing an example of the
wedge tool 12 which connects the Al ribbon 10 to the two source
pads 7 simultaneously. FIG. 23 is a perspective view showing an
example of the wedge tool 12 which connects the Al ribbon 10 to the
four source pads 7 simultaneously. The bottom is divided into the
first branch 12A and the second branch 12B also when using these
wedge tools 12. Hereby, since the Al ribbon 10 is joinable to each
source pad 7 of a plurality of silicon chips 3 with 1 time of
bonding, the same effect as the Embodiment 1 can be acquired.
Embodiment 4
[0118] FIG. 24A is a side view showing the neighborhood of a point
of the wedge tool of this embodiment, and FIG. 24B is the plan view
which observed the point of this wedge tool from the lower
part.
[0119] The vacuum hole 40 for decompressing the inside of V-groove
13 is formed in this wedge tool 12. Therefore, as shown in FIG. 25,
when joining the Al ribbon 10 to the source pad 7 using this wedge
tool 12 and the inside of V-groove 13 is decompressed, vacuum
suction of the Al ribbon 10 of the lower part of V-groove 13 will
be done to the internal direction of V-groove 13, and space (S)
will generate between the source pads 7.
[0120] As mentioned above, when the bottom of the wedge tool 12 is
divided into two by V-groove 13, the Al ribbon 10 of the lower part
of V-groove 13 does not contact the bottom of the wedge tool 12,
but loses slightly (about 8 .mu.m.about.25 .mu.m) touch with the
front surface of the source pad 7. Therefore, when this quantity of
floating is small and the silicon chip 3 is sealed with the mold
resin 2, the mold resin 2 cannot be entered between the Al ribbon
10 and the source pad 7, but few cavities (void) may generate.
[0121] On the other hand, since the mold resin 2 enters the inside
of this space (S) surely when space (S) is formed between the Al
ribbon 10 and the source pad 7 of the lower part of V-groove 13, it
can prevent a cavity (void) generating between the Al ribbon 10 and
the source pad 7.
[0122] In the foregoing, the present invention accomplished by the
present inventors is concretely explained based on above
embodiments, but the present invention is not limited by the above
embodiments, but variations and modifications may be made, of
course, in various ways in the limit that does not deviate from the
gist of the invention.
[0123] According to the embodiment, the Al ribbon 10 was used as a
conductive material which connects the source post 4P with the
source pad 7. However, also when using the ribbon which comprised
other metallic materials with small electric resistance like Au or
a Cu alloy, it can apply. Materials other than Au wire 11, for
example, an Al wire, may be used as a conductive material which
connects the gate pad 8 with the lead (gate lead) 4.
[0124] The sectional shape of the long groove which branches the
bottom of the wedge tool 12 is not limited to V-groove 13 like the
embodiment, and arbitrary form, such as the U trench 16 as shown,
for example in FIG. 26, and the square trench 17 as shown in FIG.
27, can be used for it.
[0125] In the embodiment, although the silicon chip 3 was mounted
on the die pad part 4D using Ag paste 5, pellet attachment
materials, for example, soldering paste, solder eutectics, etc.
other than Ag paste 5 can also be used.
[0126] In the embodiment, bonding of the Al ribbon 10 was done to
the source pad 7 of the silicon chip 3 with which power MOSFET was
formed. However, when it is a chip which has a pad of the large
area which can do bonding of the Al ribbon 10, it can be used even
if it is the semiconductor chip in which elements other than power
MOSFET were formed. For example, when it is the chip with which the
insulated gate bipolar transistor (IGBT) was formed, in order to
reduce the on resistance of IGBT, an emitter pad consists of area
wider than a gate pad. Therefore, the present invention can be
applied also when doing bonding of the Al ribbon to an emitter
pad.
[0127] The form of a package is not limited to SOPS and can be
applied, for example to various small size surface mounting
packages, such as VSON8 and WPAK.
[0128] The present invention relates to an effective technology in
the application to the semiconductor device which connects a lead
frame with the bonding pad of a semiconductor chip with a metallic
ribbon.
* * * * *