U.S. patent application number 12/889537 was filed with the patent office on 2011-03-24 for image sensor pixel circuit.
This patent application is currently assigned to STMicroelectronics S.A.. Invention is credited to Frederic Barbier, Francois Roy.
Application Number | 20110068381 12/889537 |
Document ID | / |
Family ID | 41572304 |
Filed Date | 2011-03-24 |
United States Patent
Application |
20110068381 |
Kind Code |
A1 |
Barbier; Frederic ; et
al. |
March 24, 2011 |
IMAGE SENSOR PIXEL CIRCUIT
Abstract
A pixel circuit of an image sensor includes a sense node for
storing a charge transferred from one or more photodiodes, a source
follower transistor having its gate coupled to the sense node and
its source node coupled to an output line of the pixel circuit via
a read transistor, wherein a body contact of the source follower
transistor is connected to the output line.
Inventors: |
Barbier; Frederic;
(Grenoble, FR) ; Roy; Francois; (Seyssins,
FR) |
Assignee: |
STMicroelectronics S.A.
Montrouge
FR
STMicroelectronics (Crolles 2) SAS
Crolles
FR
|
Family ID: |
41572304 |
Appl. No.: |
12/889537 |
Filed: |
September 24, 2010 |
Current U.S.
Class: |
257/292 ;
257/E31.001; 257/E31.073; 438/73 |
Current CPC
Class: |
H04N 5/365 20130101;
H01L 27/14609 20130101; H01L 27/1463 20130101; H04N 5/378 20130101;
H04N 5/3745 20130101; H01L 27/14683 20130101 |
Class at
Publication: |
257/292 ; 438/73;
257/E31.073; 257/E31.001 |
International
Class: |
H01L 31/112 20060101
H01L031/112; H01L 31/18 20060101 H01L031/18 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 24, 2009 |
FR |
09/56600 |
Claims
1. A pixel circuit of an image sensor comprising: a sense node for
storing a charge transferred from one or more photodiodes; and a
source follower transistor having a gate coupled to the sense node
and its source coupled to an output line of the pixel circuit via a
read transistor, wherein a body contact of the source follower
transistor is connected to said output line.
2. The image sensor of claim 1, wherein said source follower
transistor and said read transistor are formed in a same well, the
body contact of said well being connected to said output line.
3. The image sensor of claim 2, wherein said well is surrounded by
a shallow trench isolation.
4. The image sensor of claim 2, wherein said well is surrounded by
a deep trench isolation.
5. The image sensor of claim 2, wherein the body contact of said
well is formed adjacent to a source of said read transistor.
6. The image sensor of claim 2, further comprising a reset
transistor coupled between the sense node and a supply voltage,
wherein the gate of the reset transistor is arranged to receive a
reset voltage and a body contact of the reset transistor is
connected to said output line.
7. The image sensor of claim 6, wherein said reset transistor is
formed in the same well as the source follower transistor and read
transistor.
8. The image sensor of claim 1, wherein said sense node is coupled
to the one or more photodiodes via one or more transfer
transistors.
9. The image sensor of claim 1, comprising an array of said pixel
circuits.
10. An electronics device comprising the image sensor of claim
1.
11. A method of manufacturing a pixel circuit of an image sensor
comprising: forming a source follower transistor having its gate
coupled to a sense node and its source coupled to an output line of
the pixel circuit via a read transistor; and forming a connection
between a body contact of the source follower transistor and the
output line.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the priority benefit of French
patent application Ser. No. 09/56600, filed on Sep. 24, 2009,
entitled "IMAGE SENSOR PIXEL CIRCUIT," which is hereby incorporated
by reference to the maximum extent allowable by law.
FIELD OF THE INVENTION
[0002] The present invention relates to an image sensor, and in
particular to the pixel circuit of an image sensor and method of
manufacturing the same.
BACKGROUND TO THE INVENTION
[0003] Monolithic image sensors comprise photodiodes and
transistors formed in a silicon substrate. More specifically, such
image sensors comprise an array of pixels each having a photodiode
coupled to a sense node via a transfer transistor. A voltage
accumulated by the photodiode during an integration period can be
transferred to the sense node via the transfer transistor.
[0004] FIG. 1 illustrates a pixel circuit 100 of an image sensor,
comprising a photodiode 102, coupled via a transfer transistor 104
to a sense node 106. The sense node 106 has a capacitance 107,
which is, for example, formed of parasitic capacitances of the
surrounding components etc. The sense node 106 is coupled to a
supply voltage VRT via a reset transistor 108, which receives a
reset signal RST at its gate, and has its body contact connected to
ground. The sense node 106 is also coupled to the gate of a source
follower transistor 110, which has its drain coupled to the supply
voltage VRT and its body contact (also sometimes referred to as the
bulk contact) connected to ground. The source of the source
follower transistor 110 is coupled, via a read transistor 112, to
an output line 114 of the pixel circuit 100. The read transistor
receives at its gate a read signal RD, and also has its body
contact coupled to ground.
[0005] In order to improve the image quality of an image sensor
comprising an array of the pixel circuits of FIG. 1, there is a
need to improve the sensitivity of the pixel circuit.
SUMMARY OF THE INVENTION
[0006] It is one aim of embodiments of the present invention to at
least partially address one or more needs in the prior art.
[0007] According to one aspect of the present invention, there is
provided a pixel circuit of an image sensor comprising a sense node
for storing a charge transferred from one or more photodiodes; a
source follower transistor having its gate coupled to the sense
node and its source coupled to an output line of the pixel circuit
via a read transistor, wherein a body contact of the source
follower transistor is connected to said output line.
[0008] According to one embodiment, the source follower transistor
and the read transistor are formed in a same well, the body contact
of the well being connected to the output line.
[0009] According to another embodiment, the well is surrounded by a
shallow trench isolation, or a deep trench isolation.
[0010] According to another embodiment, the body contact of the
well is formed adjacent to a source of the read transistor.
[0011] According to another embodiment, the image sensor further
comprises a reset transistor coupled between the sense node and a
supply voltage, and the gate of the reset transistor is arranged to
receive a reset voltage and a body contact of the reset transistor
is connected to said output line.
[0012] According to another embodiment, the reset transistor is
formed in the same well as the source follower transistor and read
transistor.
[0013] According to another embodiment, the sense node is coupled
to the one or more photodiodes via one or more transfer
transistors.
[0014] According to another embodiment, the image sensor comprises
an array of the pixel circuits.
[0015] According to a further aspect of the present invention,
there is provided an electronics device comprising the above image
sensor.
[0016] According to yet a further aspect of the present invention,
there is provided a method of manufacturing a pixel circuit of an
image sensor comprising forming a source follower transistor having
its gate coupled to a sense node and its source coupled to an
output line of the pixel circuit via a read transistor; and forming
a connection between a body contact of the source follower
transistor and the output line.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The foregoing and other purposes, features, aspects and
advantages of the invention will become apparent from the following
detailed description of embodiments, given by way of illustration
and not limitation with reference to the accompanying drawings, in
which:
[0018] FIG. 1 (described above) illustrates schematically a pixel
circuit;
[0019] FIG. 2 illustrates schematically a pixel circuit according
to an embodiment of the present invention;
[0020] FIG. 3A illustrates, in plan view, the pixel circuit of FIG.
2 according to an embodiment of the present invention;
[0021] FIG. 3B illustrates a cross-section of the pixel circuit of
FIG. 3A according to an embodiment of the present invention;
[0022] FIG. 3C illustrates a cross-section of the pixel circuit of
FIG. 3A according to an alternative embodiment of the present
invention; and
[0023] FIG. 4 illustrates schematically an electronics device
according to an embodiment of the present invention.
DETAILED DESCRIPTION
[0024] FIG. 2 illustrates a pixel circuit 200, which has many parts
in common with the pixel circuit 100 of FIG. 1, and like features
have been labelled with like reference numerals. However, in pixel
circuit 200, the reset transistor 108, source follower transistor
110, and read transistor 112 have been replaced by a reset
transistor 208, source follower transistor 210 and read transistor
212 respectively. The source follower transistor 210, and
optionally also the reset and read transistors 208, 212, have a
body contact connected to the output column line 114. In
particular, rather than having body contacts connected to ground,
the body contact of at least the source follower transistor 210 is
connected to the output line 114.
[0025] The inventors of the present application have found that the
body effect of the source follower transistor limits its gain, and
thus reduces the charge to column voltage conversion factor (CVF)
of the source follower transistor. The gain A of the source
follower transistor, equal to the change in voltage at its source
divided by the change in voltage at its gate node,
.DELTA.VS/.DELTA.VG, can be determined as follows:
A = 1 1 + .gamma. 2 .phi. B - V BS ##EQU00001##
[0026] where .gamma. is equal to
((2q.epsilon..sub.siN.sub.A).sup.1/2)/C.sub.ox, in which q is the
elementary charge of the electron, .epsilon..sub.si is the relative
permittivity of silicon, N.sub.A is the density of acceptors in the
gate, C.sub.ox is the gate oxide capacitance per unit area,
.phi..sub.B is the surface potential equal to 2(kT/q)ln(NA/Ni), in
which k is the Boltzmann constant, T is the temperature, N.sub.A is
the density of acceptors in the gate, N.sub.i is the intrinsic
carrier concentration, and V.sub.BS is the voltage difference
between the body and the source.
[0027] To achieve a gain A that is close to unity, the voltage
V.sub.BS should be low, preferably very close to zero, and be
constant. The present inventors have found that this can be
achieved by coupling the body to the output line of the pixel, as
the output line provides a voltage level that closely follows the
source voltage of the source follower transistor.
[0028] In alternative embodiments, the body contacts of the reset
transistor 208 and/or read transistor 212 could be connected to a
reference voltage such as ground, or to their respective source
nodes.
[0029] FIG. 3A is a plan view showing an example of the arrangement
of the three transistors 210, 212 and 208 of FIG. 2. The source
follower transistor 210 and read transistor 212 are formed in a
same well, surrounded by a shallow trench isolation (STI) 302. The
source follower transistor 210 comprises a drain, formed of a
heavily doped N-type region 304 connected to a supply voltage rail
303, and a gate stack 306. The source of transistor 210 and drain
of read transistor 212 are formed of a heavily doped N-type region
308. Read transistor 212 further comprises a gate stack 309, and a
source formed of a heavily doped P-type region 310, which is
connected to the output line 114. Within the well of the source
follower transistor 210 and read transistor 212, a body contact 312
is formed of a heavily doped P-type region formed adjacent to the
source 310. The body contact 312 is connected to the output line
114.
[0030] In a separate well surrounded by an STI 314, the reset
transistor 208 is formed having a drain formed of a heavily doped
N-type region 316 coupled to the supply voltage rail 303, a gate
stack 318, and a source formed of a heavily doped N-type region
320. A body contact for the well of the reset transistor 208 is
formed of a heavily doped P-type region 322, formed alongside the
source region 320, but separated therefrom by a non-implanted
zone.
[0031] FIG. 3B illustrates a cross-section A-A of FIG. 3A, showing
the STI trench 302 surrounding the P-well of transistors 210 and
212, labelled 324, and the STI trench 314 surrounding the P-well of
the reset transistor 208, labelled 326. The P-wells 324 and 326 are
formed in an N-type substrate 328. As shown, the source contact 310
and body contact 312 are for example formed adjacent to each other
and in contact, as in any case these contacts are both connected to
the same voltage on the output line.
[0032] FIG. 3C illustrates the cross-section A-A of FIG. 3A
according to an alternative embodiment to that of FIG. 3B. In the
cross-section of FIG. 3C, the shallow trench isolations 302, 314
are replaced by deep trench isolations (DTI) 330, 332, which extend
the whole depth of P-wells 324, 326, which in this example are
formed through the whole thickness of the P-type layer 334 formed
over an underlying oxide insulation 336.
[0033] In an alternative embodiment to that of FIGS. 3A, 3B and 3C,
a single well could contain the three transistors 210, 212 and 208,
and a single or multiple body contacts could be provided within
this well for connecting it to the output line 114.
[0034] FIG. 4 illustrates an electronic device 400 comprising an
image sensor 402 including an array of pixels connected to pixel
circuits each having a structure as described above in relation to
the embodiments of FIG. 2, 3A, 3B or 3C. Control circuitry 404
provides control signals for the image sensor 402, in particular
transfer voltages TG, reset voltages RST, and read voltages RD to
the pixel circuits. Column circuitry 406 is provided for detecting
and temporarily storing the output voltages from each pixel
circuit, and storing the image data in a memory 408, under control
of a micro-processor 410. A display 412 allows images stored in
memory 408 to be displayed.
[0035] Electronic device 400 is for example a digital still and/or
video camera, mobile device or portable games console having image
capturing capabilities, a webcam, laptop computer or other digital
image capturing device having an image sensor adapted to capture
still images and/or video.
[0036] An advantage of coupling the body contact of the source
follower transistor to the output line is that this enables a
significant improvement in the charge to column voltage conversion
factor, leading to a higher SNR, and thus improved sensitivity of
the image sensor, and thus better image quality. For example, it
has been found that a typical gain of the source follower
transistor of approximately 0.75 can be increased by over 25
percent to gain that is very close to 1.
[0037] Furthermore, by coupling the body contact of both the source
follower transistor and the read transistor to the output line,
these transistors can advantageously be formed in a same well.
[0038] While the present invention has been described in relation
to a number of specific embodiments, it will be apparent to those
skilled in the art that various alterations and modifications could
be applied.
[0039] For example, while the pixel circuit of FIG. 2 comprises a
single photodiode, alternatively multiple photodiodes could be
provided, each coupled to the sense node 106 via a corresponding
transfer transistor. Furthermore, the invention could be applied to
other pixel circuits in which a source follower transistor has its
source coupled to an output line via a read transistor.
[0040] Furthermore, the embodiments described herein can apply to a
wide range of image sensors, including image sensors with
photodiodes and/or source follower transistors with junction
isolation, DTI or STI isolation, or oxide isolation.
[0041] Furthermore, while the source follower, reset and read
transistors are N-channel MOS transistors in the described
embodiments, alternatively one or more of these transistors could
be replaced by a P-channel MOS transistor.
[0042] Furthermore, while the source follower, reset and read
transistors are N-channel MOS transistors in the described
embodiments, alternatively one or more of these transistors could
be replaced by a P-channel MOS transistor.
[0043] Such alterations, modifications, and improvements are
intended to be part of this disclosure, and are intended to be
within the spirit and the scope of the present invention.
Accordingly, the foregoing description is by way of example only
and is not intended to be limiting. The present invention is
limited only as defined in the following claims and the equivalents
thereto.
* * * * *