U.S. patent application number 12/841257 was filed with the patent office on 2011-01-27 for light emitting structure with integral reverse voltage protection.
This patent application is currently assigned to RFMD (UK) LIMITED. Invention is credited to Matthew Francis O'Keefe.
Application Number | 20110017972 12/841257 |
Document ID | / |
Family ID | 43496489 |
Filed Date | 2011-01-27 |
United States Patent
Application |
20110017972 |
Kind Code |
A1 |
O'Keefe; Matthew Francis |
January 27, 2011 |
LIGHT EMITTING STRUCTURE WITH INTEGRAL REVERSE VOLTAGE
PROTECTION
Abstract
A light emitting structure having reverse voltage protection
(RVP) is provided along with disclosure of a method for fabricating
the light emitting structure. The light emitting structure includes
a substrate having a first face, a second face, and a p-n junction
formed within the substrate between a p-type layer and an n-type
layer, wherein the p-type layer and the n-type layer are adapted as
a RVP diode. A buffer layer is provided on the substrate, and a
light emitting diode (LED) is fabricated on the buffer layer. The
LED is then electrically coupled to the RVP diode in an
anti-parallel diode pair (APDP) configuration.
Inventors: |
O'Keefe; Matthew Francis;
(Newton Aycliffe, GB) |
Correspondence
Address: |
WITHROW & TERRANOVA, P.L.L.C.
100 REGENCY FOREST DRIVE, SUITE 160
CARY
NC
27518
US
|
Assignee: |
RFMD (UK) LIMITED
Newton Aycliffe
GB
|
Family ID: |
43496489 |
Appl. No.: |
12/841257 |
Filed: |
July 22, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61227630 |
Jul 22, 2009 |
|
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|
Current U.S.
Class: |
257/13 ;
257/E33.008; 257/E33.074; 438/29 |
Current CPC
Class: |
H01L 33/22 20130101;
H01L 27/15 20130101 |
Class at
Publication: |
257/13 ; 438/29;
257/E33.008; 257/E33.074 |
International
Class: |
H01L 33/04 20100101
H01L033/04; H01L 33/22 20100101 H01L033/22 |
Claims
1. A light emitting structure having reverse voltage protection
(RVP), the light emitting structure comprising: a substrate having
a first face, a second face, and a p-n junction formed within the
substrate between a p-type layer and an n-type layer, wherein the
p-type layer and the n-type layer are adapted as a RVP diode; a
buffer layer provided on the substrate; and a light emitting diode
(LED) fabricated onto the buffer layer, wherein the LED is
electrically coupled to the RVP diode in an anti-parallel diode
pair (APDP) configuration.
2. The light emitting structure of claim 1 wherein the substrate
comprises silicon (Si).
3. The light emitting structure of claim 1 wherein the LED
comprises: a first doped layer provided on the buffer layer; a
multiple quantum well (MQW) structure layer fabricated on the first
doped layer; and a second doped layer provided on the MQW structure
layer.
4. The light emitting structure of claim 3 wherein the first doped
layer is made of n-doped gallium nitride (GaN).
5. The light emitting structure of claim 3 wherein the second doped
layer is made of p-doped GaN.
6. The light emitting structure of claim 1 wherein the buffer layer
is deposited or grown on the first face of the substrate.
7. The light emitting structure of claim 1 wherein the buffer layer
comprises sub-layers of aluminum nitride (AlN) and aluminum gallium
nitride (Al.sub.xGa.sub.1-xN) (0<x.ltoreq.1).
8. The light emitting structure of claim 1 wherein the buffer layer
is made of AlN.
9. The light emitting structure of claim 1 wherein the buffer layer
is made of Al.sub.xGa.sub.1-xN (0<x.ltoreq.1).
10. The light emitting structure of claim 1 wherein the buffer
layer comprises a plurality of layers made of Al.sub.xGa.sub.1-xN
(0<x.ltoreq.1).
11. The light emitting structure of claim 1 wherein the first face
of the substrate is a <111> plane.
12. The light emitting structure of claim 1 wherein the first face
of the substrate comprises a <100> plane having a plurality
of grooves therein, wherein each of the plurality of grooves
include sidewalls that are <111> planes.
13. The light emitting structure of claim 12 wherein a minimum
channel width of the each of the plurality of grooves is two to ten
times greater than a given wavelength of a light emission of the
LED.
14. A method of fabricating a light emitting structure, the method
comprising: providing a silicon (Si) substrate having a first face,
a second face, and a p-n junction formed within the substrate
between a p-type layer and an n-type layer, wherein the p-type
layer and the n-type layer are adapted as an RVP diode; depositing
or growing a buffer layer onto the first face of the substrate;
fabricating a LED via steps comprising: depositing or growing a
first doped layer onto the buffer layer; fabricating an MQW
structure layer on the first doped layer; depositing or growing a
second doped layer onto the MQW structure layer; providing a first
electrical contact on the second doped layer; etching through the
second doped layer and the MQW structure layer to expose the first
doped layer; providing a second electrical contact on the first
doped layer; etching through the first doped layer and the buffer
layer to expose the first face of the substrate; providing a third
electrical contact on the first face of the substrate; providing a
fourth electrical contact on the second face of the substrate; and
coupling electrically the first electrical contact to the fourth
electrical contact and the second electrical contact to the third
electrical contact such that the LED and RVP diode make up an APDP
configuration.
15. The method of claim 14 wherein providing the substrate with the
p-n junction comprises diffusing a p-type dopant into an n-type
silicon (Si) layer of the substrate.
16. The method of claim 14 wherein providing the substrate with the
p-n junction comprises bonding an n-type Si wafer to a p-type Si
wafer.
17. The method of claim 14 further including producing a plurality
of grooves in the first face of the substrate before depositing or
growing the buffer layer onto the first face of the substrate.
18. The method of claim 17 wherein producing the plurality of
grooves is accomplished via etching the first face of the substrate
using a wet chemistry etchant.
19. The method of claim 18 wherein the wet chemistry etchant is
potassium hydroxide (KOH).
20. The method of claim 17 wherein producing the plurality of
grooves is accomplished via mechanical etching.
21. The method of claim 14 further including mounting the light
emitting structure onto an LED sub-mount via adhering the fourth
electrical contact of the light emitting structure to the LED
sub-mount.
Description
RELATED APPLICATIONS
[0001] This application claims the benefit of provisional patent
application Ser. No. 61/227,630, filed Jul. 22, 2009, the
disclosure of which is hereby incorporated herein by reference in
its entirety. The application also relates to provisional patent
application Ser. No. 61/227,624, filed Jul. 22, 2009, and to
utility patent application Ser. No. 12/705,869 filed Feb. 15, 2010,
both of which are hereby incorporated herein by reference in their
entireties.
FIELD OF THE DISCLOSURE
[0002] The present disclosure relates to a light emitting structure
having a reverse voltage protection diode that is dimensionally
efficient and inexpensive to manufacture.
BACKGROUND OF THE DISCLOSURE
[0003] Semiconductor structures such as light emitting diodes
(LEDs) are susceptible to damage from accidental applications of
reverse voltages. A reverse voltage condition can occur if an LED
is inadvertently placed into a circuit backwards. For example,
someone may accidentally couple a cathode of the LED to an anode
pad of the circuit while coupling an anode of the LED to a cathode
pad of the circuit. As a result, the LED will likely be damaged to
a point of complete failure at the moment power is applied to the
LED.
[0004] Moreover, LEDs are susceptible to electrostatic discharge
(ESD). Triboelectric effects can lead to a large potential
difference across an electrically insulating material. An ESD may
occur if a large potential difference develops across a
semiconductor device. A resultant short-duration high-current pulse
flowing through the semiconductor device will likely damage the
semiconductor device to a point of complete failure. LEDs are
particularly vulnerable in that a reverse voltage resulting from an
ESD of only a few volts of reverse bias potential difference is
usually enough to damage an LED.
[0005] Prior art attempts to protect LEDs from accidental reverse
voltage and/or ESD include coupling a cathode of an external diode
to an anode of an LED to be protected along with coupling a cathode
of the LED to an anode of the external diode. In this
configuration, a potentially destructive current resulting from an
accidental reverse voltage or ESD will harmlessly pass through the
external diode while bypassing the LED being protected. While
external diodes do a good job of protecting LEDs, there are
disadvantages in using external diodes. One disadvantage is an
increased manufacturing cost due to additional assembly processes
that are needed to add an external diode to an LED. Another
disadvantage is an undesirable increase in package size needed to
accommodate the external diode. This disadvantage is especially
evident when it is desirable to minimize the size of a reverse
voltage protected LED. For example, an external diode used to
protect an LED designed for a flip chip-type package would defeat
the purpose of the flip chip-type package, which is to minimize the
space taken up by the LED. Therefore, a need remains for an LED
that preserves the smallest-size package intended for the LED while
including a reverse voltage protection (RVP) diode that is
relatively inexpensive to add to the LED.
SUMMARY OF THE DISCLOSURE
[0006] The present disclosure describes the use of standard silicon
technology to fabricate a p-n junction into a substrate prior to
fabricating a light emitting structure on top of the substrate. In
this way, the p-n junction is integral with the light emitting
structure and is usable to protect the light emitting structure
from reverse voltage events such as accidental reverse voltage
application and/or an electrostatic discharge (ESD). The
combination of the p-n junction within the substrate of the light
emitting structure forms a light emitting diode (LED) that is
integral with a protective diode formed by the p-n junction. Since
the protective diode is integrally formed with the light emitting
structure, the protective diode is relatively inexpensive to add to
the LED, while at the same time, it allows the manufacturer to
preserve the smallest-size package intended for the LED.
[0007] In particular, the present disclosure provides a gallium
nitride (GaN) LED that is reverse voltage protected and well suited
for flip chip-type packaging. A process of manufacture for the GaN
LED uses standard silicon manufacturing processes to fabricate a
p-n junction into a substrate onto which the light emitting
structure making up the GaN LED is grown. The p-n junction may be
fabricated into the substrate prior to growing the light emitting
structure of the GaN LED. The p-n junction can be formed by
impurity diffusion or by ion implantation. A buffer layer for
reducing strain between the substrate and the light emitting
structure is formed on the substrate before the light emitting
structure of the GaN LED is grown.
[0008] Fabrication of the light emitting structure of the GaN LED
may be accomplished using standard semiconductor fabrication
techniques. However, the formation of electrical contacts for the
light emitting structure may include mesa or trench processing
steps to access the doped material within the substrate.
[0009] Those skilled in the art will appreciate the scope of the
present disclosure and realize additional aspects thereof after
reading the following detailed description of the preferred
embodiments in association with the accompanying drawing
figures.
BRIEF DESCRIPTION OF THE DRAWING FIGURES
[0010] The accompanying drawing figures incorporated in and forming
a part of this specification illustrate several aspects of the
disclosure, and together with the description serve to explain the
principles of the disclosure.
[0011] FIG. 1A is a cross-section view of one embodiment of a light
emitting structure according to the present disclosure.
[0012] FIG. 1B is a symbolic representation of a anti-parallel
diode pair (APDP) that is realized in the light emitting structure
of FIG. 1A.
[0013] FIG. 2 is a cross-section view of another embodiment of a
light emitting structure, which includes grooves in the substrate
for scattering light in accordance with the present disclosure.
[0014] FIG. 3 is a flowchart of a method of manufacture for a light
emitting structure according to the present disclosure.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0015] The embodiments set forth below represent the necessary
information to enable those skilled in the art to practice the
disclosure and illustrate the best mode of practicing the
disclosure. Upon reading the following description in light of the
accompanying drawing figures, those skilled in the art will
understand the concepts of the disclosure and will recognize
applications of these concepts not particularly addressed herein.
It should be understood that these concepts and applications fall
within the scope of the disclosure and the accompanying claims.
[0016] FIG. 1A provides a cross-section view of one embodiment of a
light emitting structure 10 according to the present disclosure.
The light emitting structure 10 includes a substrate 12 having a
first face 14, a second face 16, and a p-n junction 18 formed from
a first substrate layer 20 that is adjacent to a second substrate
layer 22. In this particular embodiment, it is preferred that the
substrate be made of silicon. The first substrate layer 20 and the
second substrate layer 22 are adapted as a reverse voltage
protection (RVP) diode 24 shown symbolically in FIG. 1B. As
depicted in FIG. 1A, the first substrate layer 20 is made of p-type
silicon and the second substrate layer 22 is made of n-type
silicon. The p-n junction may be formed by bonding an n-type
silicon wafer to a p-type silicon wafer. Alternately, the p-n
junction may be formed by diffusing a p-type dopant into an n-type
silicon layer of the substrate.
[0017] The first face 14 of the substrate 12 may have a preferred
orientation of crystalline structure in order to minimize crystal
lattice mismatches between the first face 14 of the substrate 12
and a layer that may be grown or deposited onto the first face 14
of the substrate 12. For example, the first face 14 of the
substrate 12 may have a silicon (Si) crystal lattice that is
preferably directed in a <111> plane in order to minimize the
crystal lattice mismatch and hence mechanical strain between the
substrate 12 and another layer deposited or grown on the first face
14. However, other planes of a Si crystal lattice may provide a
nucleation needed to minimize the crystal lattice mismatch between
the substrate and another layer deposited or grown on the first
face 14.
[0018] A buffer layer 26 is provided on the substrate 12. The
buffer layer 26 may be grown or deposited on the substrate 12. The
buffer layer 26 may comprise sub-layers of aluminum nitride (AlN)
and various compounds of aluminum gallium nitride
(Al.sub.xGa.sub.1-xN), wherein x is greater than zero but less than
or equal to one. Alternately, the substrate 12 may comprise AlN.
Further still, the substrate 12 may be made of a plurality of
layers of Al.sub.xGa.sub.1-xN (0<x.ltoreq.1).
[0019] A first doped layer 28 is provided on the buffer layer 26.
The first doped layer 28 may be deposited or grown on the buffer
layer 26. Preferably the first doped layer 28 is made of n-type
gallium nitride (GaN). A multiple quantum well (MQW) structure
layer 30 is grown onto the first doped layer 28, and a second doped
layer 32 is deposited onto the MQW structure layer 30. The first
doped layer 28, the MQW structure layer 30, and the second doped
layer 32 make up a light emitting diode (LED) 34 that is
electrically coupled to the RVP diode 24 in an anti-parallel diode
pair (APDP) configuration 36 as shown symbolically in FIG. 1B. The
APDP configuration 36 of the present disclosure electrically
couples the cathode of the RVP diode 24 to the anode of the LED 34
and also electrically couples the cathode of the LED 34 to the
anode of the RVP diode 24. The RVP diode 24 acts as a reverse
voltage protection device that electrically conducts a potentially
damaging reverse voltage urged current to bypass the LED 34 if the
reverse voltage across the LED 34 exceeds a predetermined
voltage.
[0020] Turning attention back to FIG. 1A, a first electrical
contact 38 is provided on the second doped layer 32, a second
electrical contact 40 is provided on the first doped layer 28, a
third electrical contact 42 is provided onto the first face 14 of
the substrate 12, and a fourth electrical contact 44 is provided
onto the second face 16 of the substrate 12. The APDP configuration
36 (FIG. 1B) is realized by electrically coupling the first
electrical contact 38 to the fourth electrical contact 44 via a
first conductor 46, and by electrically coupling the second
electrical contact 40 to the third electrical contact 42 via a
second conductor 48.
[0021] FIG. 2 depicts an alternate embodiment of the light emitting
structure 10 of FIG. 1. In this embodiment, the substrate 12
includes a plurality of grooves 50 that are fabricated into the
first face 14 of the substrate 12. The plurality of grooves 50 may
be fabricated via etching the first face 14 of the substrate 12
using a wet chemistry etchant such as potassium hydroxide (KOH) or
by mechanical etching. The first face 14 has a crystal lattice that
is directed in the <100> plane and the each of the plurality
of grooves 50 has sidewalls 52 that are formed within <111>
planes. The preferred shape for the plurality of grooves 50 is a V,
as shown in FIG. 2. However, other shapes for the plurality of
grooves 50 are possible. Moreover, the first face 14 may have
orientations other than the preferred <100> plane
orientation. Further still, a minimum channel width of the each of
the plurality of grooves 50 is two to ten times greater than a
given wavelength of a light emission of the LED 34.
[0022] The plurality of grooves 50 scatters the light produced by
the LED 34 with an efficiency that is significant enough to reduce
a need for external reflective surfaces. Thus, the light emitting
structure 10 is suitable for flip chip packaging. For example, as
shown in FIG. 2, the light emitting structure 10 may be mounted on
a flip chip-sized LED sub-mount 54. The LED sub-mount 54 preferably
has a metalized and patterned surface that includes metal contacts
56.
[0023] FIG. 3 depicts a method of fabricating the light emitting
structure 10 (FIGS. 1A and 2). An embodiment of the disclosure uses
Si as a base material making up the substrate 12. The method may
begin by providing the substrate 12 having the first face 14 and
the second face 16, wherein the plurality of grooves 50 (FIG. 2)
are etched into the first face 14 of the substrate 12 (step 100).
Next, the p-n junction 18 is formed within the substrate 12 between
the first substrate layer 20 and the second substrate layer 22
(step 102). The first substrate layer 20 and the second substrate
layer 22 are adapted to be the RVP diode 24 (FIG. 1B). Various
methods for forming the p-n junction 18 of the RVP diode 24 are
known in the prior art. For example, a p-type dopant can be
diffused into an n-type layer to produce the first substrate layer
20, and thus the p-n junction 18. Alternately, the first substrate
layer 20 can be grown on the second substrate layer 22 (or vice
versa). Further still, the p-n junction 18 can be formed by bonding
an n-type wafer to a p-type wafer. Step 100 and step 102 may be
exchanged, but it is generally preferable for the plurality of
grooves 50 to be etched before the p-n junction 18 is formed.
[0024] Another step includes providing the buffer layer 26 onto the
first face 14 of the substrate 12 (step 104). The buffer layer 26
may be grown or deposited on the substrate 12. The buffer layer 26
may comprise sub-layers of AlN and various compounds of
Al.sub.xGa.sub.1-xN, wherein x is greater than zero but less than
or equal to one. Alternately, the buffer layer 26 may comprise only
AlN. Further still, the buffer layer 26 may be made of a plurality
of layers made of Al.sub.xGa.sub.1-xN (0<x.ltoreq.1).
[0025] Other steps include fabricating the LED 34 (FIG. 1B). The
fabrication of the LED 34 begins by providing the first doped layer
28 on the buffer layer 26 (step 106). Preferably, the step 106 is
accomplished by depositing or growing the first doped layer 28 on
the buffer layer 26. It is also preferable for the first doped
layer 28 to be made of n-type doped GaN.
[0026] In order to allow the light emitting structure to emit light
efficiently, a step of fabricating the MQW structure layer 30 onto
the first doped layer 28 is performed using standard MQW
fabrication technology (step 108). Another step completes the LED
34 by providing the second doped layer 32 onto the MQW structure
layer 30 (step 110). The step 110 providing the second doped layer
32 is preferably accomplished by depositing or growing p-type doped
GaN onto the MQW structure layer 30.
[0027] Next, a series of steps are performed to make electrical
connections between the RVP diode 24 and the LED 34. These steps
may begin by providing the first electrical contact 38 on the
second doped layer 32 (step 112). The first electrical contact 38
is preferably made of a material that is the same type as the
second doped layer 32. For example, if the second doped layer 32 is
made of n-type material, then the first electrical contact 38
should also be made of n-type material. A next step includes
etching through the second doped layer 32 and the MQW structure
layer 30 to expose a section of the first doped layer 28 (step
114). Another step involves providing the second electrical contact
40 onto the first doped layer 28 (step 116). Yet another step
includes etching through the first doped layer 28 and the buffer
layer 26 to expose a section of the first face 14 of the substrate
12 (step 118). A further step includes providing the third
electrical contact 42 on the first face 14 of the substrate 12
(step 120). Another step involves providing the fourth electrical
contact 44 onto the second face 16 of the substrate 12 (step
122).
[0028] Other steps involve making electrical connections such that
the LED 34 and RVP diode 24 make up the APDP configuration 36. One
of these steps involves coupling electrically the first electrical
contact 38 to the fourth electrical contact 44 via the first
conductor 46 (step 124). Another step includes coupling
electrically the second electrical contact 40 to the third
electrical contact 42 via the second conductor 48 (step 126).
[0029] Those skilled in the art will recognize improvements and
modifications to the preferred embodiments of the present
disclosure. All such improvements and modifications are considered
within the scope of the concepts disclosed herein and the claims
that follow.
* * * * *