U.S. patent application number 12/853700 was filed with the patent office on 2010-12-23 for semiconductor device including independent active layers and method for fabricating the same.
This patent application is currently assigned to PANASONIC CORPORATION. Invention is credited to Yutaka HIROSE, Tsuyoshi Tanaka.
Application Number | 20100320559 12/853700 |
Document ID | / |
Family ID | 36582780 |
Filed Date | 2010-12-23 |
United States Patent
Application |
20100320559 |
Kind Code |
A1 |
HIROSE; Yutaka ; et
al. |
December 23, 2010 |
SEMICONDUCTOR DEVICE INCLUDING INDEPENDENT ACTIVE LAYERS AND METHOD
FOR FABRICATING THE SAME
Abstract
A semiconductor device includes a semiconductor substrate of
n-type silicon including, in an upper portion thereof, a first
polarity inversion region and a second polarity inversion regions
spaced from each other and doped with a p-type impurity. A first
HFET including a first active layer and a second HFET including a
second active layer both made of a group III-V nitride
semiconductor are independently formed on the respective polarity
inversion regions in the semiconductor substrate, and the HFETs are
electrically connected to each other through interconnects.
Inventors: |
HIROSE; Yutaka; (Kyoto,
JP) ; Tanaka; Tsuyoshi; (Osaka, JP) |
Correspondence
Address: |
MCDERMOTT WILL & EMERY LLP
600 13TH STREET, NW
WASHINGTON
DC
20005-3096
US
|
Assignee: |
PANASONIC CORPORATION
Osaka
JP
|
Family ID: |
36582780 |
Appl. No.: |
12/853700 |
Filed: |
August 10, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11299818 |
Dec 13, 2005 |
7800097 |
|
|
12853700 |
|
|
|
|
Current U.S.
Class: |
257/506 ;
257/615; 257/E21.598; 257/E23.169; 257/E27.013; 438/401 |
Current CPC
Class: |
H01L 29/66462 20130101;
H01L 29/2003 20130101; H01L 27/0605 20130101; H01L 29/7787
20130101; H01L 27/1203 20130101; H01L 21/84 20130101 |
Class at
Publication: |
257/506 ;
438/401; 257/615; 257/E21.598; 257/E27.013; 257/E23.169 |
International
Class: |
H01L 27/06 20060101
H01L027/06; H01L 21/77 20060101 H01L021/77; H01L 23/538 20060101
H01L023/538 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 13, 2004 |
JP |
2004-359447 |
Claims
1-7. (canceled)
8. A method for fabricating a semiconductor device comprising the
steps of: forming, in an upper portion of a semiconductor substrate
of a first conductivity type, a plurality of polarity inversion
regions spaced from one another by selectively introducing a first
impurity of a second conductivity type into said semiconductor
substrate; forming a semiconductor layer made of a group III-V
nitride over said semiconductor substrate including said polarity
inversion regions; forming insulating isolation regions extending
from said semiconductor layer to said semiconductor substrate by
selectively introducing a second impurity into portions of said
semiconductor layer and said semiconductor substrate disposed
around said polarity inversion regions, whereby respectively
forming, on said polarity inversion regions, a plurality of element
forming regions each including an active layer in said
semiconductor layer; forming a plurality of semiconductor elements
by forming electrodes on said element forming regions; and forming
interconnects for electrically connecting said semiconductor
elements to one another on said plurality of semiconductor
elements.
9. The method for fabricating a semiconductor device of claim 8,
further comprising, before the step of forming a semiconductor
layer made of a group III-V nitride, a step of forming, in said
semiconductor substrate, a mark for identifying a position of each
of said polarity inversion regions, wherein said mark is used for
identifying the position of each of said polarity inversion regions
in said semiconductor substrate in selectively forming said
isolation regions between said polarity inversion regions in
forming said plurality of element forming regions.
10. A semiconductor device comprising: a semiconductor substrate
having buried insulating layers formed, from a principal face
thereof toward an inner portion thereof, to be spaced from one
another; a plurality of semiconductor elements formed to be spaced
from one another on said semiconductor substrate and respectively
including independent active layers made of a group III-V nitride
semiconductor; and interconnects for electrically connecting said
semiconductor elements to one another.
11. The semiconductor device of claim 10, wherein each of said
semiconductor elements has at least one terminal, and at least one
of said semiconductor elements is electrically connected to a
portion above said buried insulating layer of said semiconductor
substrate at said terminal.
12. The semiconductor device of claim 10, wherein each of said
semiconductor elements has at least one terminal, and at least one
of said semiconductor elements is electrically connected to a
portion underneath said buried insulating layer of said
semiconductor substrate at said terminal.
13. The semiconductor device of claim 10, further comprising an
insulating isolation region formed in said semiconductor substrate
around said semiconductor elements.
14. A method for fabricating a semiconductor device comprising the
steps of: forming a semiconductor layer made of a group III-V
nitride on a conducting semiconductor substrate that includes
buried insulating layers formed, from a principal face thereof
toward an inner portion thereof, to be spaced from one another;
forming insulating isolation regions extending to said buried
insulating layers by selectively introducing an impurity into said
semiconductor layer and said semiconductor substrate, whereby
forming, on said semiconductor substrate, a plurality of element
forming regions each including an active layer in said
semiconductor layer; forming a plurality of semiconductor elements
by forming electrodes on said element forming regions; and forming
interconnects for electrically connecting said semiconductor
elements to one another on said plurality of semiconductor
elements.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority under 35 U.S.C. .sctn.119
on Patent Application Nos. 2004-359447 and 2005-316247 filed in
Japan respectively on Dec. 13, 2004 and Oct. 31, 2005, the entire
contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a semiconductor device and
a method for fabricating the same, and more particularly it relates
to a semiconductor device including a plurality of high power
elements using a group III-V nitride semiconductor.
[0003] A group III-V nitride semiconductor is a compound
semiconductor of a compound composed of aluminum (Al), boron (B),
gallium (Ga) or indium (In) and nitride (N) represented by a
general formula of B.sub.wAl.sub.xGa.sub.yIn.sub.zN (wherein
w+x+y+z=1 and 0.ltoreq.w, x, y, z.ltoreq.1).
[0004] A group III-V nitride semiconductor has various advantages
such as a large band gap, a high breakdown voltage derived from the
large band gap, a high electron saturation velocity and high
electron mobility, and a high electron concentration attained in
forming a heterojunction, and therefore, various examinations and
developments are now being made on application to a
short-wavelength light emitting device, a high power high-frequency
device, a high-frequency low-noise amplifier device, a high power
switching device and the like.
[0005] Conventionally, such devices are developed as simplex
devices for attaining performances that are realized by utilizing
good material characteristics (physical properties) of a group
III-V nitride semiconductor itself but cannot be realized by using
other materials.
[0006] FIG. 11 is a cross-sectional view of a conventional group
III-V nitride semiconductor device using a heterojunction (see, for
example, Japanese Patent Publication No. 2996169 or 3409958). As
shown in FIG. 11, the conventional group III-V nitride
semiconductor device includes an operation layer 102 of gallium
nitride (GaN) and a barrier layer 103 of aluminum gallium nitride
(AlGaN) successively stacked on a semiconductor substrate 101 with
a conducting property, and a heterojunction is formed on an
interface between the operation layer 102 and the barrier layer 103
having different band gaps.
[0007] The barrier layer 103 is partitioned by an insulating
isolation region 104 reaching an upper portion of the operation
layer 102, a Schottky gate electrode 105 is formed on the
partitioned barrier layer 103, and an ohmic source electrode 106
and an ohmic drain electrode 107 are formed on both sides of the
gate electrode 105 along the gate length direction. Thus, the
semiconductor device is operated as a heterojunction field effect
transistor (hereinafter referred to as the HFET).
[0008] In the vicinity of the interface in the operation layer 102
of the heterojunction between the operation layer 102 and the
barrier layer 103, electrons derived from a difference in
spontaneous polarization and piezo-electric polarization between
the operation layer 102 and the barrier layer 103, an n-type
impurity doped in the barrier layer 103 and other uncontrollable
defects caused in the operation layer 102 and the barrier layer 103
are accumulated in a high concentration so as to form a
two-dimensional electron gas (2DEG), and the thus formed 2DEG works
as a channel carrier of the field effect transistor.
[0009] The source electrode 106 is electrically connected to the
semiconductor substrate 101 set to ground potential through a
surface via interconnect 108, so as to reduce a parasitic component
in a high-frequency or high-speed switching operation. Also, the
semiconductor substrate 101 set to the ground potential functions
also as a field plate (field releasing plate), and therefore, it
exhibits an effect to release concentration of the electric field
in a device active region, and particularly at an end of the gate
electrode 105 closer to the drain electrode 107.
[0010] In the conventional group III-V nitride semiconductor
device, however, current leakage is caused through the
semiconductor substrate 101 in a high voltage operation, and
therefore, it is difficult to electrically connecting or
integrating a plurality of elements (HFETs) formed on one
semiconductor substrate 101.
SUMMARY OF THE INVENTION
[0011] The present invention was devised for overcoming the
aforementioned conventional problem, and an object of the invention
is integrating a plurality of elements made of a group III-V
nitride semiconductor on a semiconductor substrate with a
conducting property.
[0012] In order to achieve the object, in the semiconductor device
according to the invention, a plurality of semiconductor elements
each having an active layer made of a group III-V nitride
semiconductor are formed on polarity inversion regions with a
polarity different from the conductivity type of a semiconductor
substrate or on a semiconductor substrate having a buried
insulating layer.
[0013] The first semiconductor device of this invention includes a
semiconductor substrate of a first conductivity type having, in an
upper portion thereof, a plurality of polarity inversion regions
spaced from one another and formed by introducing an impurity of a
second conductivity type; a plurality of semiconductor elements
selectively formed respectively on the polarity inversion regions
and respectively including independent active layers made of a
group III-V nitride semiconductor; and interconnects for
electrically connecting the semiconductor elements to one
another.
[0014] In the first semiconductor device, semiconductor elements
are electrically insulated from each other even within the
semiconductor substrate owing to a depletion layer formed by a pn
junction between each polarity inversion region and the
semiconductor substrate. Therefore, even when the respective
semiconductor elements are electrically connected to one another
through interconnects and operated at a high voltage, a leakage
current caused between the semiconductor elements through the
semiconductor substrate can be suppressed to be very small.
Accordingly, a semiconductor device including a plurality of
semiconductor elements respectively having independent active
layers made of a group III-V nitride semiconductor and electrically
connected to one another can be integrated on a semiconductor
substrate with a conducting property.
[0015] In the first semiconductor device, each of the semiconductor
elements preferably has at least one terminal, and at least one of
the semiconductor elements is preferably electrically connected to
the semiconductor substrate at the terminal. Thus, the
semiconductor substrate connected to one terminal of the
semiconductor element functions as a field plate for releasing the
electric field, and therefore, a higher breakdown voltage can be
attained. Furthermore, since the semiconductor substrate has the
same potential with respect to the plural semiconductor elements,
if the semiconductor substrate is connected to a terminal for
supplying common potential to the semiconductor elements, such as
ground potential, a ground interconnect can be reduced.
[0016] In the first semiconductor device, preferably, the first
conductivity type is p-type, the second conductivity type is
n-type, and the III-V group nitride semiconductor includes an
n-type layer. Accordingly, the positive source voltage applied at
operation of the active layer made of the n-type III-V group
nitride semiconductor forms a depletion layer at the interface of
the p-n junction between each p-type polarity inversion region and
the n-type active layer, thereby realizing higher breakdown voltage
and smaller leakage current.
[0017] In the first semiconductor device, a concentration of the
impurity in each of the polarity inversion regions is preferably
lower in a peripheral portion thereof than in an inner portion
thereof on a principal face of the semiconductor substrate. Thus, a
breakdown voltage between the polarity inversion region and another
region becomes higher, and hence, the semiconductor device can be
operated at a higher voltage.
[0018] The first semiconductor device preferably further includes
insulating isolation regions formed in the semiconductor substrate
between the polarity inversion regions. Thus, a breakdown voltage
between the polarity inversion region and another region becomes
higher, the semiconductor device can be operated at a higher
voltage.
[0019] In the first semiconductor device, a mark for identifying a
position of each of the polarity inversion regions is preferably
formed in the semiconductor substrate. Thus, after forming the
semiconductor layer including the active layers made of the group
III-V nitride semiconductor, alignment between the semiconductor
layer and each polarity inversion region is eased.
[0020] In this case, the mark is preferably exposed on the
semiconductor substrate.
[0021] The first method for fabricating a semiconductor device of
this invention includes the steps of forming, in an upper portion
of a semiconductor substrate of a first conductivity type, a
plurality of polarity inversion regions spaced from one another by
selectively introducing a first impurity of a second conductivity
type into the semiconductor substrate; forming a semiconductor
layer made of a group III-V nitride over the semiconductor
substrate including the polarity inversion regions; forming
insulating isolation regions extending from the semiconductor layer
to the semiconductor substrate by selectively introducing a second
impurity into portions of the semiconductor layer and the
semiconductor substrate disposed around the polarity inversion
regions, whereby respectively forming, on the polarity inversion
regions, a plurality of element forming regions each including an
active layer in the semiconductor layer; forming a plurality of
semiconductor elements by forming electrodes on the element forming
regions; and forming interconnects for electrically connecting the
semiconductor elements to one another on the plurality of
semiconductor elements.
[0022] In the first method for fabricating a semiconductor device,
semiconductor elements are electrically insulated from each other
even within the semiconductor substrate owing to a depletion layer
formed by a pn junction between each polarity inversion region and
the semiconductor substrate. Therefore, even when the respective
semiconductor elements are electrically connected to one another
through interconnects and operated at a high voltage, a leakage
current caused between the semiconductor elements through the
semiconductor substrate can be suppressed to be very small.
[0023] The first method for fabricating a semiconductor device
preferably further includes, before the step of forming a
semiconductor layer made of a group III-V nitride, a step of
forming, in the semiconductor substrate, a mark for identifying a
position of each of the polarity inversion regions, and the mark is
preferably used for identifying the position of each of the
polarity inversion regions in the semiconductor substrate in
selectively forming the isolation regions between the polarity
inversion regions in forming the plurality of element forming
regions. Thus, after forming the semiconductor layer including the
active layers made of the group III-V nitride semiconductor,
alignment between each element forming region of the semiconductor
layer and each polarity inversion region is eased.
[0024] The second semiconductor device of the invention includes a
semiconductor substrate having buried insulating layers formed,
from a principal face thereof toward an inner portion thereof, to
be spaced from one another; a plurality of semiconductor elements
formed to be spaced from one another on the semiconductor substrate
and respectively including independent active layers made of a
group III-V nitride semiconductor; and interconnects for
electrically connecting the semiconductor elements to one
another.
[0025] In the second semiconductor device, even semiconductor
elements are electrically connected to each other as an integrated
circuit on a semiconductor substrate having a buried insulating
layer, a high voltage operation can be performed.
[0026] In the second semiconductor device, each of the
semiconductor elements preferably has at least one terminal, and at
least one of the semiconductor elements is preferably electrically
connected to a portion above the buried insulating layer of the
semiconductor substrate at the terminal. Thus, the semiconductor
layer disposed above the buried insulating layer attains the same
potential as the terminal of the semiconductor element so as to
function as a field plate, and therefore, even when the
semiconductor elements are electrically connected to one another,
the semiconductor device can be operated at a higher voltage.
[0027] In the second semiconductor device, wherein each of the
semiconductor elements preferably has at least one terminal, and at
least one of the semiconductor elements is preferably electrically
connected to a portion underneath the buried insulating layer of
the semiconductor substrate at the terminal. Thus, potential of the
semiconductor layer disposed below the buried insulating layer of
the semiconductor substrate can be the same, and therefore,
interconnect resistance can be reduced. In addition, since the
semiconductor layer disposed below the buried insulating layer
functions as a field plate, even when the semiconductor elements
are electrically connected to one another, the semiconductor device
can be operated at a higher voltage.
[0028] The second semiconductor device preferably further includes
an insulating isolation region formed in the semiconductor
substrate around the semiconductor elements. Thus, the breakdown
voltage between the semiconductor elements can be increased, and
hence, the semiconductor device can be operated at a higher
voltage.
[0029] The second method for fabricating a semiconductor device of
this invention includes the steps of forming a semiconductor layer
made of a group III-V nitride on a conducting semiconductor
substrate that includes buried insulating layers formed, from a
principal face thereof toward an inner portion thereof, to be
spaced from one another; forming insulating isolation regions
extending to the buried insulating layers by selectively
introducing an impurity into the semiconductor layer and the
semiconductor substrate, whereby forming, on the semiconductor
substrate, a plurality of element forming regions each including an
active layer in the semiconductor layer; forming a plurality of
semiconductor elements by forming electrodes on the element forming
regions; and forming interconnects for electrically connecting the
semiconductor elements to one another on the plurality of
semiconductor elements.
[0030] In the second method for fabricating a semiconductor device,
a plurality of element forming regions each including an active
layer made of a group III-V nitride in the semiconductor layer are
independently formed by forming a plurality of insulating isolation
regions reaching the buried insulating layers. Therefore, even when
the respective semiconductor elements are electrically connected to
one another as an integrated circuit, a high voltage operation can
be performed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0031] FIGS. 1A and 1B are diagrams of a semiconductor device
according to Embodiment 1 of the invention, wherein FIG. 1A is a
plan view thereof and FIG. 1B is a cross-sectional view thereof
taken along line Ib-Ib of FIG. 1A;
[0032] FIG. 2 is an enlarged cross-sectional view for showing the
structure of an active layer of the semiconductor device of
Embodiment 1;
[0033] FIG. 3 is a characteristic diagram for showing the
relationship between an applied voltage and a leakage current
between elements of the semiconductor device of Embodiment 1
compared with that of a conventional semiconductor device;
[0034] FIGS. 4A, 4B and 4C are cross-sectional views for showing
procedures in a method for fabricating the semiconductor device of
Embodiment 1;
[0035] FIGS. 5A, 5B and 5C are cross-sectional views for showing
other procedures in the method for fabricating the semiconductor
device of Embodiment 1;
[0036] FIGS. 6A and 6B are cross-sectional views for showing other
procedures in the method for fabricating the semiconductor device
of Embodiment 1;
[0037] FIG. 7 is a cross-sectional view of a semiconductor device
according to Embodiment 2 of the invention;
[0038] FIG. 8 is a characteristic diagram for showing the
relationship between an applied voltage and a leakage current
between elements of the semiconductor device of Embodiment 2
compared with that of a conventional semiconductor device;
[0039] FIGS. 9A, 9B and 9C are cross-sectional views for showing
procedures in a method for fabricating the semiconductor device of
Embodiment 2;
[0040] FIGS. 10A, 10B and 10C are cross-sectional views for showing
other procedures in the method for fabricating the semiconductor
device of Embodiment 2; and
[0041] FIG. 11 is a cross-sectional view of a conventional
semiconductor device (HFET) using a group III-V nitride
semiconductor.
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1
[0042] Embodiment 1 of the invention will now be described with
reference to the accompanying drawings.
[0043] FIGS. 1A and 1B show a semiconductor device of Embodiment 1
in which two high power HFETs are integrated, and specifically,
FIG. 1A is a plan view thereof and FIG. 1B is a cross-sectional
view thereof taken on line Ib-Ib of FIG. 1A.
[0044] As shown in FIG. 1B, a first polarity inversion region 12A
and a second polarity inversion region 12B both of p-type
conductivity spaced from each other are selectively formed in an
upper portion of a semiconductor substrate 11 of, for example,
n-type silicon (Si). The bottoms and the side faces of the polarity
inversion regions 12A and 12B are covered with a p-type low
concentration impurity region 13 including a p-type impurity in a
lower concentration than in the polarity inversion regions 12A and
12B. Since the p-type low concentration impurity region 13 is thus
provided, a larger depletion layer extends in the semiconductor
substrate 11 when a high voltage is applied to the semiconductor
device, and hence, the breakdown voltage is increased by
approximately 20% as compared with the case where the polarity
inversion regions alone are provided.
[0045] As shown in FIGS. 1A and 1B, a first active layer 14A and a
second active layer 14B in each of which a plurality of group III-V
nitride semiconductor layers are stacked are formed respectively on
the first polarity inversion region 12A and the second polarity
inversion region 12B on the principal face of the semiconductor
substrate 11.
[0046] At this point, the detailed structure of the first active
layer 14A and the second active layer 14B is shown in FIG. 2. Each
of the active layers 14A and 14B includes an initial buffer layer
141 of aluminum nitride (AlN) with a thickness of approximately 50
nm, a superlattice layer composed of fifteen gallium nitride (GaN)
layers 142 and fifteen aluminum nitride (AlN) layers 143 each
having a thickness of 25 nm and alternately stacked, and a channel
layer 144 with a thickness of 1 .mu.m, which are successively
epitaxially grown from the substrate side. In this case, the
superlattice layer guarantees a high breakdown voltage peculiar to
GaN-based materials.
[0047] As shown in FIGS. 1A and 1B, a first gate electrode 15A, a
first source electrode 16A and a first drain electrode 17A provided
on the both sides of and spaced from the first gate electrode 15A
are formed on the first active layer 14A, and a second gate
electrode 15B, a second source electrode 16B and a second drain
electrode 17B provided on the both sides of and spaced from the
second gate electrode 15B are formed on the second active layer
14B. In this manner, a first HFET 10A including the first active
layer 14A and a second HFET 10B including the second active layer
14B are constructed on the semiconductor substrate 11. In this
embodiment, the first drain electrode 17A of the first HFET 10A and
the second drain electrode 17B of the second HFET 10B are adjacent
to each other.
[0048] An insulating isolation region 18 is formed around the HFETs
10A and 10B for insulating them from each other. The bottom of the
isolation region 18 is placed at a level equivalent to the bottoms
of the first active layer 14A and the second active layer 14B, and
the HFETs 10A and 10B exhibit high isolation characteristics also
within the semiconductor substrate 11.
[0049] An interlayer insulating film 20 of silicon nitride
(Si.sub.3N.sub.4) with a thickness of, for example, 300 nm is
formed on the isolation region 18 over the whole top face including
the HFETs 10A and 10B. A first contact 21A penetrating through the
interlayer insulating film 20 and the isolation region 18 to be
connected to the semiconductor substrate 11 is formed in a portion
of the interlayer insulating film 20 on a side of the first source
electrode 16A. Also, a second contact 21B penetrating through the
interlayer insulating film 20 and the isolation region 18 to be
connected to the semiconductor substrate 11 is formed in a portion
of the interlayer insulating film 20 on a side of the second source
electrode 16B.
[0050] Interconnects 22 respectively for connecting the first
contact 21A and the first source electrode 16A to each other, for
connecting the first drain electrode 17A and the second gate
electrode 15B to each other, for connecting the second contact 21B
and the second source electrode 16B to each other, etc. are formed
on the interlayer insulating film 20.
[0051] FIG. 3 shows comparison of a leakage current caused between
elements in the semiconductor device of Embodiment 1 and a
conventional semiconductor device. In the semiconductor device of
this embodiment, the leakage current is smaller by two or more
figures than in the conventional semiconductor device under
application of a high voltage of 300 V or more. Thus, a high
breakdown voltage is realized in the present semiconductor
device.
[0052] Now, a method for fabricating the semiconductor device
having the aforementioned architecture will be described with
reference to the accompanying drawings.
[0053] FIGS. 4A through 4C, 5A through 5C, 6A and 6B are
cross-sectional views for showing procedures in the method for
fabricating the semiconductor device of Embodiment 1.
[0054] First, as shown in FIG. 4A, a first resist film is applied
on a semiconductor substrate 11 of n-type silicon, and thereafter,
the first resist film is formed, by lithography, into a first
resist pattern 61 having openings in a plurality of regions where
p-type low concentration impurity regions are to be formed.
Subsequently, by using the first resist pattern 61 as a mask, first
ion beams 71 including boron (B) are ion implanted at acceleration
energy of 50 keV and a dose of 1.times.10.sup.12 cm.sup.-2, thereby
forming a plurality of p-type low concentration regions 13 in an
upper portion of the semiconductor substrate 11.
[0055] Next, as shown in FIG. 4B, after removing the first resist
pattern 61, a second resist film is applied on the principal face
of the semiconductor substrate 11. Subsequently, the second resist
film is formed, by the lithography, into a second resist pattern 62
having openings in regions between the p-type low concentration
impurity regions 13 on the principal face of the semiconductor
substrate 11 where polarity inversion regions are to be formed.
Thereafter, by using the second resist pattern 62 as a mask, second
ion beams 72 including boron (B) are ion implanted at acceleration
energy of 50 keV and a dose of 1.times.10.sup.13 cm.sup.-2, thereby
forming a first polarity inversion region 12A and a second polarity
inversion region 12B both of the p-type conductivity within the
respective p-type low concentration impurity regions 13 in the
semiconductor substrate 11.
[0056] Then, as shown in FIG. 4C, after removing the second resist
pattern 62, a concave mark 11a to be used as an alignment
identifying mark in a subsequent exposure step of forming an active
layer (element forming region) made of a GaN-based semiconductor
layer is formed, by dry etching using an etching gas including
chlorine (Cl.sub.2) as a principal component, in a region on the
principal face of the semiconductor substrate 11 where neither the
polarity inversion regions 12A and 12B nor the p-type low
concentration impurity regions 13 are formed. At this point,
regions on the principal face of the substrate excluding the region
where the mark 11a is to be formed are protected by covering with a
third resist film (not shown) with a thickness of 2 through 3
.mu.m.
[0057] Next, as shown in FIG. 5A, by using the third resist mask as
a mask, a protection film 63 of silicon oxide is deposited by
chemical vapor deposition (CVD) so as to fill the mark 11a and to
attain a thickness of approximately 2 .mu.m on the mark 11a.
Subsequently, after removing the third resist film, a semiconductor
layer 14 of a group III-V nitride is epitaxially grown by metal
organic chemical vapor deposition (MOCVD) on the semiconductor
substrate 11 including the polarity inversion regions 12A and 12B
and the p-type low concentration impurity regions 13.
[0058] Then, as shown in FIG. 5B, after aligning a mask by using
the mark 11a, third ion beams 73 including boron (B) are
selectively ion implanted at acceleration energy of 500 keV and a
dose of 1.times.10.sup.14 cm.sup.-2 into portions of the
semiconductor layer 14 sandwiched between the p-type low
concentration impurity regions 13 in the semiconductor substrate
11, thereby forming insulating isolation regions 18 in the portions
of the semiconductor layer 14 sandwiched between the p-type low
concentration impurity regions 13. Thus, a first active layer 14A
and a second active layer 14B both made of the group III-V nitride
are independently formed from the semiconductor layer 14
respectively on the polarity inversion regions 12A and 12B. It is
noted that the mark 11a is not shown in FIG. 5B.
[0059] Next, as shown in FIG. 5C, a fourth resist pattern (not
shown) having openings in regions where source electrodes and drain
electrodes are to be formed is formed on the active layers 14A and
14B including the isolation regions 18 by the lithography.
Thereafter, by using the fourth resist pattern as a mask, a first
metal film of a multilayered body of titanium (Ti) and aluminum
(Al) is deposited by, for example, vacuum deposition or sputtering.
Then, a first source electrode 16A and a first drain electrode 17A,
and a second source electrode 16B and a second drain electrode 17B
all having an ohmic property are formed respectively on the first
active layer 14A and the second active layer 14B by what is called
a lift-off method for removing the fourth resist pattern.
Subsequently, a fifth resist pattern (not shown) having openings in
regions where gate electrodes are to be formed is formed on the
active layers 14A and 14B including the isolation regions 18 by the
lithography. Then, by using the fifth resist pattern as a mask, a
second metal film of palladium (Pd) is deposited by, for example,
the vacuum deposition. Thereafter, a first gate electrode 15A and a
second gate electrode 15B both having a Schottky property are
respectively formed on the first active layer 14A and the second
active layer 14B by the lift-off method for removing the fifth
resist pattern. Thus, a first HFET 10A including the first active
layer 14A and a second HFET 10B including the second active layer
14B are formed.
[0060] Next, as shown in FIG. 6A, an interlayer insulating film 20
of silicon nitride (Si.sub.3N.sub.4) with a thickness of 300 nm is
deposited by the CVD so as to cover the first HFET 10A and the
second HFET 10B. Subsequently, openings for exposing contact
forming regions and connecting portions for connecting the gate
electrodes 15A and 15B, the source electrodes 16A and 16B and the
drain electrodes 17A and 17B to interconnects are formed in the
interlayer insulating film 20 by the lithography and the dry
etching using an etching gas including fluorocarbon as a principal
component. Thereafter, contact holes 18a for forming substrate
contacts of the HFETs 10A and 10B are formed in the isolation
regions 18 so as to expose the semiconductor substrate 11 therein
by the lithography and the dry etching using chlorine.
[0061] Then, as shown in FIG. 6B, a sixth resist pattern (not
shown) for exposing the contact holes 18a, one ends of the gate
electrodes 15A and 15B, the source electrodes 16A and 16B and the
drain electrodes 17A and 17B is formed on the interlayer insulating
film 20 by the lithography. Subsequently, by using the sixth resist
pattern as a mask, a metal film of titanium (Ti) and gold (Au) for
forming interconnects is deposited by a plating method, thereby
forming contacts 21A and 21B and interconnects 22.
[0062] It is noted that the semiconductor substrate 11 may be a
p-type semiconductor substrate instead of the n-type substrate.
Embodiment 2
[0063] Embodiment 2 of the invention will now be described with
reference to the accompanying drawings.
[0064] FIG. 7 is a cross-sectional view of a semiconductor device
of Embodiment 2 in which two high power HFETs are integrated. The
plan structure of this semiconductor device is similar to that of
Embodiment 1 shown in FIG. 1B. Also, like reference numerals are
used in FIG. 7 to refer like elements shown in FIG. 1 and the
description is omitted.
[0065] In Embodiment 1, the semiconductor substrate 11 of n-type
silicon is used as the substrate on which the group III-V nitride
semiconductor layer 14 is epitaxially grown. In contrast, an n-type
SOI substrate 31 including an n-type upper silicon layer 30a, a
buried oxide layer 30b and an n-type lower silicon layer 30c is
used in Embodiment 2 as shown in FIG. 7.
[0066] Specifically, the SOI substrate 31 includes the n-type upper
silicon layer 30a with a thickness of 0.2 .mu.m, the buried oxide
layer 30b of silicon oxide with a thickness of 100 nm formed under
the n-type upper silicon layer 30a, and the n-type lower silicon
layer 30c formed under the buried oxide layer 30b.
[0067] In the upper silicon layer 30a, a first p-type low
concentration impurity region 32A and a second p-type low
concentration impurity region 32B are formed respectively below a
first HFET 10A and a second HFET 10B so as to be in contact with
the buried oxide layer 30b.
[0068] In Embodiment 2, an isolation region 18 reaches the buried
oxide layer 30b. Thus, the HFETs 10A and 10B exhibit high isolation
characteristics also in the SOI substrate 31.
[0069] Each of a first contact 21A and a second contact 21B
penetrates through the buried oxide layer 30b so as to reach the
n-type lower silicon layer 30c.
[0070] It is noted that the lower end of the isolation region 18
may be placed at a level within the n-type upper silicon layer 30a
of the SOI substrate 31 so as to allow the contacts 21A and 21B to
be in contact with the n-type upper silicon layer 30a. Also in this
case, the n-type upper silicon layer 30a attains potential
equivalent to that of source electrodes 16A and 16B of the HFETs
10A and 10B so as to function as a field plate, and therefore, even
when the HFETs 10A and 10B are electrically connected to each
other, a high voltage operation can be performed.
[0071] FIG. 8 shows comparison of a leakage current caused between
elements in the semiconductor device of Embodiment 2 and a
conventional semiconductor device. In the semiconductor device of
this embodiment, the leakage current is smaller by three or more
figures than in the conventional semiconductor device under
application of a high voltage of 300 V or more. Thus, a higher
breakdown voltage is realized in the present semiconductor
device.
[0072] Now, a method for fabricating the semiconductor device
having the aforementioned architecture will be described with
reference to the accompanying drawings.
[0073] FIGS. 9A through 9C and 10A through 10C are cross-sectional
views for showing procedures in the method for fabricating the
semiconductor device of Embodiment 2.
[0074] First, as shown in FIG. 9A, a first resist film is applied
on an n-type upper silicon layer 30a of a SOI substrate 31, and
thereafter, the first resist film is formed, by the lithography,
into a first resist pattern 61 having openings in a plurality of
regions where p-type low concentration impurity regions are to be
formed. Subsequently, by using the first resist pattern 61 as a
mask, first ion beams 74 including boron (B) are ion implanted at
acceleration energy of 50 keV and a dose of 1.times.10.sup.12
cm.sup.-2, thereby forming a plurality of p-type low concentration
impurity regions 32 in the n-type upper silicon layer 30a. Although
the p-type low concentration impurity regions 32 are not always
necessary, they are preferably provided because the breakdown
voltage of the semiconductor device is thus further increased.
[0075] Next, as shown in FIG. 9B, after removing the first resist
pattern 61, a second resist pattern 64 having openings for exposing
regions on the principal face of the SOI substrate 31 where the
p-type low concentration impurity regions 32A and 32B are not
formed is formed by the lithography. Subsequently, by using the
second resist pattern 64 as a mask, a hole-shaped mark 30d to be
used as an alignment identifying mark in a subsequent exposure step
of forming an active layer (element forming region) made of a
GaN-based semiconductor layer is formed in the n-type upper silicon
layer 30a by the dry etching using an etching gas including
chlorine as a principal component.
[0076] Then, as shown in FIG. 9C, by using the second resist
pattern 64 as a mask, a protection film 63 of a silicon oxide is
deposited by the CVD so as to fill the mark 30d and attain a
thickness of approximately 2 .mu.m on the mark 30d. Subsequently,
after removing the second resist pattern 64, a semiconductor layer
14 of a group III-V nitride is epitaxially grown by the MOCVD on
the n-type upper silicon layer 30a of the SOI substrate 31
including the p-type low concentration impurity regions 32A and
32B.
[0077] Next, as shown in FIG. 10A, after aligning a mask by using
the mark 30d, second ion beams 75 including boron (B) are
selectively ion implanted at acceleration energy of 500 keV and a
dose of 1.times.10.sup.14 cm.sup.-2 into portions of the
semiconductor layer 14 sandwiched between the p-type low
concentration impurity regions 32A and 32B, thereby forming
insulating isolation regions 18 in the portions of the
semiconductor layer 14 sandwiched between the p-type low
concentration impurity regions 32A and 32B. Thus, a first active
layer 14A and a second active layer 14B both made of the group
III-V nitride are independently formed from the semiconductor layer
14 respectively on the p-type low concentration impurity regions
32A and 32B. It is noted that the mark 30d is not shown in FIG.
10A.
[0078] Then, as shown in FIG. 10B, in the same manner as in
Embodiment 1, a first source electrode 16A and a first drain
electrode 17A, and a second source electrode 16B and a second drain
electrode 17B all made of a multilayered body of titanium and
aluminum are formed respectively on the first active layer 14A and
the second active layer 14B by the lithography and the lift-off
method. Subsequently, a first gate electrode 15A and a second gate
electrode 15B both of palladium are formed respectively on the
first active layer 14A and the second active layer 14B by the
lithography and the lift-off method. Thus, a first HFET 10A
including the first active layer 14A and a second HFET 10B
including the second active layer 14B are formed.
[0079] Next, as shown in FIG. 10C, an interlayer insulating film 20
of silicon nitride with a thickness of 300 nm is deposited by the
CVD so as to cover the first HFET 10A and the second HFET 10B.
Then, openings for exposing contact forming regions and connecting
portions for connecting the gate electrodes 15A and 15B, the source
electrodes 16A and 16B and the drain electrodes 17A and 17B to
interconnects are formed in the interlayer insulating film 20 by
the lithography and the dry etching using an etching gas including
fluorocarbon as a principal component. Thereafter, contact holes
18a for forming substrate contacts of the HFETs 10A and 10B are
formed in the isolation regions 18 by the lithography and the dry
etching using chlorine so as to expose the n-type lower silicon
layer 30c of the SOI substrate 31 therein.
[0080] Then, the lithography and the plating method are executed
for forming a first contact 21A and a second contact 21B and for
forming, on the interlayer insulating film 20, interconnects 22
connected to one ends of the gate electrodes 15A and 15B, the
source electrodes 16A and 16B and the drain electrodes 17A and 17B.
Thus, the semiconductor device of FIG. 7 is completed.
[0081] It is noted that the SOI substrate 31 including the n-type
layers may be replaced with a SOI substrate including p-type upper
and lower silicon layers.
[0082] Further, in each of Embodiments 1 and 2 when at least the
channel layer 144 and the GaN layer 142 as the supperlattice layers
of the first active layer 14A and the second active layer 14B are
n-type, a depletion layer is formed in the n-type layer within each
active layer 14A, 14B because the polarity inversion regions 12A,
12B in the semiconductor substrate 11 are p-type, resulting in
further reduction of the leakage current.
[0083] It is noted that in each of Embodiments 1 and 2, the
supperlattice layers made of the GaN layer 142 and the AlN layer
143 are not necessarily formed in the active layers 14A, 14B,
respectively. With no supperlattice layer provided, a pn junction
is formed between the p-type polarity inversion regions 12A, 12B of
the semiconductor substrate 11 if at least the channel layer 144 in
each active region 14A, 14B is n-type, so that the depletion layer
formed around the pn junction further expands even at application
of higher positive voltage to each active layer 14A, 14B. Hence,
the leakage current is suppressed, resulting in higher breakdown
voltage.
[0084] As described so far, in the semiconductor device and the
fabrication method for the same of this invention, a semiconductor
device including a plurality of semiconductor elements all of which
include independent active layers made of a group III-V nitride
semiconductor and are electrically connected to one another can be
integrated on a semiconductor substrate with a conducting property,
and therefore, the invention is useful for a semiconductor device
including high power elements or the like.
* * * * *