U.S. patent application number 12/805782 was filed with the patent office on 2010-12-23 for electronic device, method for manufacturing the same, and silicon substrate for electronic device.
Invention is credited to Shinji Uya.
Application Number | 20100320507 12/805782 |
Document ID | / |
Family ID | 39705916 |
Filed Date | 2010-12-23 |
United States Patent
Application |
20100320507 |
Kind Code |
A1 |
Uya; Shinji |
December 23, 2010 |
Electronic device, method for manufacturing the same, and silicon
substrate for electronic device
Abstract
An electronic device is formed by epitaxially growing a Si
substrate on a Si layer of an SOI substrate in which the Si layer
is deposited on a front surface of a substrate with an insulating
layer interposed therebetween; forming an element on a
front-surface side of the Si substrate; and forming a back-surface
element aligned with respect to the element, on a back-surface side
of the Si substrate after the substrate is etched. A mark is formed
by etching and removing the Si layer and the insulating layer in a
predetermined position of the SOI substrate. The element is formed
using a concave part as a reference position. The concave part
appears on the front surface of the Si substrate epitaxially grown
on the mark. The back-surface element is formed using the mark as a
reference position. The mark appears after the substrate is
etched.
Inventors: |
Uya; Shinji; (Kurokawa-gun,
JP) |
Correspondence
Address: |
BIRCH STEWART KOLASCH & BIRCH
PO BOX 747
FALLS CHURCH
VA
22040-0747
US
|
Family ID: |
39705916 |
Appl. No.: |
12/805782 |
Filed: |
August 19, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12032390 |
Feb 15, 2008 |
7825001 |
|
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12805782 |
|
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Current U.S.
Class: |
257/228 ;
257/E21.499; 257/E31.11; 438/106 |
Current CPC
Class: |
H01L 27/14687 20130101;
H01L 27/1464 20130101; H01L 27/12 20130101; H01L 27/14812 20130101;
H01L 27/0694 20130101; H01L 21/84 20130101; H01L 27/14843 20130101;
H01L 27/1463 20130101; H01L 27/14621 20130101; Y10S 438/975
20130101; H01L 27/14627 20130101 |
Class at
Publication: |
257/228 ;
438/106; 257/E31.11; 257/E21.499 |
International
Class: |
H01L 31/02 20060101
H01L031/02; H01L 21/50 20060101 H01L021/50 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 19, 2007 |
JP |
P2007-037881 |
Claims
1. An electronic device comprising: a silicon substrate for the
electronic device that is epitaxially grown on a silicon layer of
an SOI substrate in which the silicon layer is deposited on a front
surface of a semiconductor substrate with an insulating layer
interposed therebetween; a front-surface element formed on a
front-surface side of the silicon substrate for the electronic
device; and a back-surface element formed on a back-surface side of
the silicon substrate for the electronic device after the
semiconductor substrate of the SOI substrate is etched, with being
aligned with respect to the front-surface element, wherein: a
back-surface mark is formed by etching and removing the silicon
layer and the insulating layer in a predetermined position of the
SOI substrate, the front-surface element is formed using a concave
part as a reference position, the concave part appearing, on the
front surface of the silicon substrate for the electronic device
epitaxially grown on the back-surface mark, and the back-surface
element is formed using the back-surface mark as a reference
position, the back-surface mark appearing after the semiconductor
substrate is etched.
2. The electronic device according to claim 1, wherein the
electronic device is a back-illuminated solid-state imaging
element, the front-surface element comprises a photoelectric
conversion element and a signal reading-out unit, and the
back-surface element comprises an optical element opposed to the
photoelectric conversion element.
3. The electronic device according to claim 2, wherein the signal
reading-out unit comprises a charge transfer unit.
4. A silicon substrate for electronic device manufactured by
epitaxially growing a silicon substrate on a silicon layer of an
SOI substrate in which the silicon layer is deposited on a front
surface of a semiconductor substrate with an insulating layer
interposed therebetween; forming a front-surface element on a
front-surface side of the silicon substrate; and forming a
back-surface element, that is aligned with respect to the
front-surface element, on a back-surface side of the silicon
substrate after etching the semiconductor substrate of the SOI
substrate, wherein a back-surface mark is formed by etching and
removing the silicon layer and the insulating layer in a
predetermined position of the SOI substrate, the front-surface
element is formed using a concave part as a reference position, the
concave part appearing, on the front surface of the silicon
substrate for the electronic device formed on the back-surface
mark, and the back-surface element is formed using the back-surface
mark as a reference, the back-surface mark appearing after the
semiconductor substrate is etched.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Divisional of co-pending application
Ser. No. 12/032,390, filed on Feb. 15, 2008, which claims priority
to Application No. 2007-37881 filed in Japan on Feb. 19, 2007, the
entire contents of which are hereby incorporated by reference into
the present application and for which priority is claimed under 35
U.S.C. .sctn.120.
BACKGROUND OF THE INVENTION
[0002] 1. Technical Field
[0003] The invention relates to a silicon (Si) substrate or the
like for manufacturing an electronic device, and more particularly
to an electronic device that is manufactured by aligning elements
formed on a front surface thereof and elements formed on a back
surface thereof with high precision, a manufacturing method
thereof, and a silicon substrate for the electronic device.
[0004] 2. Description of the Related Art
[0005] When an electronic device is manufactured on a silicon
substrate, there is a case where elements are formed on both a
front surface and a back surface of the silicon substrate and the
elements formed on the front surface are aligned with respect to
the elements formed on the back surface. The "front surface" and
"back surface" mean "one face" and "the other face" of a substrate,
respectively.
[0006] For example, in a back-illuminated solid-state imaging
device, as described in Japanese Patent No. 3722367 (corresponding
to US 2004/005729 A), a plurality of photodiodes arranged in
two-dimensional array and a signal reading-out circuit for reading
out image signals detected by the photodiodes are formed on a
front-surface side of the semiconductor substrate, while color
filters and micro lenses are formed on a back-surface side of the
semiconductor substrate.
[0007] In the back-illuminated solid-state imaging device, light is
incident from a photographic subject to the back surface of the
semiconductor substrate, and is received by the photodiodes
provided on the front-surface side. Accordingly, when the color
filter and the micro lens provided for each photodiode are not
aligned with respect to the photodiode, color mixture or the like
occurs.
[0008] For this reason, it is necessary to align the elements
(color filers, micro lenses) provided on the back-surface side with
the elements (photodiodes, signal reading circuit, and the like)
provided on the front-surface side.
[0009] In Japanese Patent No. 3722367, a back-surface mark is
formed while viewing from the back-surface side through the
semiconductor substrate, a metal layer or a silicide layer that is
provided on the front-surface side. In this case, red or
near-infrared light for which Si has low absorption rate is used as
reference light. However, when a Si absorption layer is formed to
have a sufficient thick (e.g., 10 .mu.m) capable of absorbing most
of visible light, signal intensity is hardly caught in the red
reference light.
[0010] The near-infrared light having a wavelength of about 1.2
.mu.m or less is absorbed by Si. Accordingly, the near-infrared
light is not suitable for a thick Si-layer structure, and aligning
with high precision cannot be achieved.
[0011] US 2006/0186560 A proposes a method for manufacturing a
back-illuminated image sensor using a Si substrate in which a p
layer having concentration gradient is grown by epitaxial growth on
an SOI substrate with a thin seed layer deposited thereon. However,
US 2006/0186560 A does not mention about forming a lattice-shaped
light-shielding layer, a color filter, a micro lens, and the like
on a back-surface side with high positional precision.
[0012] In the back-illuminated solid-state imaging element, when
the light-shielding layer, the color filter, the micro lens, and
the like provided on the back-surface side deviates from a
structure of a pixel portion formed on the front-surface side of
the silicon substrate, color mixture occurs. For this reason, it is
important to reduce the deviation in a coordinate system between an
alignment mark provided on the front-surface side and an alignment
mark provided on the back-surface side.
[0013] When a size of a pixel becomes smaller than a thickness of a
Si layer of a photodiode in order to arrange a large number of
pixels in an imaging device, color mixture may further occur.
Accordingly, a micro lens, a light-shielding element, and the like
are required. As a width of the light-shielding element is
increased, the color-mixture margin between two adjacent colors is
also increased accordingly, but it means openings are narrowed as
the color-mixture margin is increased, causing loss of sensitivity.
It is noted that the color-mixture margin is the tendency of the
color not to be mixed. For a micro pixel image sensor which employs
a back-illuminated structure due to the decrease in pixel size and
the shortage of sensitivity, there is a demand that the
light-shielding element is formed as narrow as possible. Therefore,
it has been desired to make the deviation in structure between the
front-surface layer and the back-surface layer as narrow as
possible.
[0014] The back-illuminated solid-state imaging element has been
described above as an example. However, the above description is
also applicable to the overall semiconductor device for forming
elements aligned with high precision on the front and back
surfaces.
SUMMARY OF THE INVENTION
[0015] The invention provides an electronic device in which
elements formed on front and back surfaces are aligned with high
precision, a method for manufacturing the same, and a silicon
substrate for the electronic device.
[0016] According to an aspect of the invention, a method for
manufacturing an electronic device includes: forming a back-surface
mark by etching and removing a silicon layer and an insulating
layer in a predetermined position of an SOI substrate in which the
silicon layer is deposited on a front surface of a semiconductor
substrate with the insulating layer interposed between the silicon
layer and the semiconductor substrate; epitaxially growing a
silicon substrate for the electronic device, on the silicon layer
of the SOI substrate; forming a front-surface element on a
front-surface side of the silicon substrate for the electronic
device using a concave part as a reference position, wherein the
concave part appears, on the front surface of the silicon substrate
for the electronic device epitaxially grown on the back-surface
mark; and forming a back-surface element, that is aligned with
respect to the front-surface element, on a back-surface side of the
silicon substrate for the electronic device after etching the
semiconductor substrate of the SOI substrate, using the
back-surface mark as a reference position, wherein the back-surface
mark appears after the etching of the semiconductor substrate of
the SOI substrate.
[0017] According to another aspect of the invention, an electronic
device includes a silicon substrate, a front-surface element and a
back-surface element. The silicon substrate for the electronic
device is epitaxially grown on a silicon layer of an SOI substrate
in which the silicon layer is deposited on a front surface of a
semiconductor substrate with an insulating layer interposed
therebetween. The front-surface element is formed on a
front-surface side of the silicon substrate for the electronic
device. The back-surface element is formed on a back-surface side
of the silicon substrate for the electronic device after the
semiconductor substrate of the SOI substrate is etched, with being
aligned with respect to the front-surface element. A back-surface
mark is formed by etching and removing the silicon layer and the
insulating layer in a predetermined position of the SOI substrate.
The front-surface element is formed using a concave part as a
reference position, the concave part appearing, on the front
surface of the silicon substrate for the electronic device
epitaxially grown on the back-surface mark. The back-surface
element is formed using the back-surface mark as a reference
position. The back-surface mark appears after the semiconductor
substrate is etched.
[0018] Also, the electronic device may be a back-illuminated
solid-state imaging element. The front-surface element may include
a photoelectric conversion element and a signal reading-out unit.
The back-surface element may include an optical element opposed to
the photoelectric conversion element.
[0019] Also, the signal reading-out unit may include a charge
transfer unit.
[0020] According to further another aspect of the invention, a
silicon substrate for electronic device is manufactured by:
epitaxially growing a silicon substrate on a silicon layer of an
SOT substrate in which the silicon layer is deposited on a front
surface of a semiconductor substrate with an insulating layer
interposed therebetween; forming a front-surface element on a
front-surface side of the silicon substrate; and forming a
back-surface element, that is aligned with respect to the
front-surface element, on a back-surface side of the silicon
substrate after etching the semiconductor substrate of the SOI
substrate. A back-surface mark is formed by etching and removing
the silicon layer and the insulating layer in a predetermined
position of the SOI substrate. The front-surface element is formed
using a concave part as a reference position. The concave part
appears, on the front surface of the silicon substrate for the
electronic device formed on the back-surface mark. The back-surface
element is formed using the back-surface mark as a reference. The
back-surface mark appearing after the semiconductor substrate is
etched.
[0021] According to the invention, a concave part formed on the
basis of a back-surface mark is used as a front-surface mark,
front-surface elements are positioned with reference to the
front-surface mark, the hack-surface elements are positioned with
reference to the back-surface mark, and thus it is possible to
align the front and back-surface elements so as to be opposed to
each other with high precision.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] FIG. 1 is a sectional schematic diagram illustrating a
back-illuminated solid-state imaging element according to an
embodiment of the invention.
[0023] FIG. 2 is a diagram illustrating a manufacturing process of
the back-illuminated solid-state imaging element shown in FIG.
1.
[0024] FIG. 3 is a diagram illustrating a manufacturing process
after the manufacturing process shown in FIG. 2.
[0025] FIG. 4 is a diagram illustrating a manufacturing process
after the manufacturing process shown in FIG. 3.
[0026] FIG. 5 is a diagram illustrating a manufacturing process
after the manufacturing process shown in FIG. 4.
[0027] FIG. 6 is a diagram illustrating a manufacturing process
after the manufacturing process shown in FIG. 5.
[0028] FIG. 7 is a diagram illustrating a relation between a
front-surface mark and a back-surface mark shown in FIG. 6.
[0029] FIG. 8 is a sectional schematic diagram illustrating an
electronic device according to another embodiment of the
invention.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
[0030] Hereinafter, embodiments of the invention will be described
with reference to the drawings.
[0031] FIG. 1 is a sectional schematic view of a back-illuminated
solid-state imaging element 100 according to an embodiment of the
invention. The solid-state imaging element according to the
embodiment is an interline type CCD. Vertical charge transfer paths
(VCCD) 21 and photodiodes (photoelectric conversion elements) 22
are formed on a front-surface side of a p type semiconductor
substrate 1. A color filter (red (R), green (G) and blue (B)) layer
23 and micro lenses 24 are laminated on a back-surface side
thereof.
[0032] The back-illuminated solid-state imaging element 100
according to the embodiment is a CCD type. However, the invention
is applicable to a CMOS type solid-state imaging element or other
solid-state imaging elements in the same manner as described in
Japanese Patent No. 3722367.
[0033] A high-concentration p layer 25 is formed on a surface of
the semiconductor substrate 1 on the back-surface side, and the p
layer 25 is grounded. An insulating layer 26, such as silicon oxide
or silicon nitride, which is transparent with respect to incident
light, is deposited on the high-concentration p layer 25. A high
refractive index layer 27, which is transparent with respect to the
incident light, such as silicon nitride or a diamond-structured
carbon film, is deposited thereon. The color filter layer 23 and
the micro lens (top lens) layer 24 are sequentially deposited
thereon. Each micro lens 24 is formed based on an alignment mark
which will be described later so as to focus on the center of the
corresponding photodiode 22 opposed to each lens 24.
[0034] The color filter layer 23 is arranged in pixel (photodiode)
units, and a light-shielding element 28 for preventing color
mixture between pixels is provided in the color filter layer 23 on
one side of the color filter layer 23 close to the semiconductor
substrate 1 and between the adjacent pixel units.
[0035] The vertical charge transfer path (VCCD) 21 formed on the
front-surface side of the semiconductor substrate 1 includes a
buried channel 31 of a high-concentration n layer and a transfer
electrode film 33 which are deposited with a gate insulating film
32 interposed therebetween. The gate insulating layer 32 is formed
of a silicon oxide film or an insulating film having an ONO
(silicon-oxide film, silicon-nitride film, and silicon-oxide film)
structure formed on the outermost surface on the front-surface side
of the semiconductor substrate 1.
[0036] The vertical charge transfer paths 21 are formed to extend
in a direction perpendicular to a direction in which a horizontal
charge transfer path (HCCD) (not shown) extends. A number of
vertical charge transfer paths 21 are formed. Between the adjacent
vertical charge transfer paths 21, a plurality of photodiodes 22
are formed at a predetermined pitch in a direction along the
vertical charge transfer paths 21.
[0037] In the embodiment, each photodiode 22 includes an n layer 35
formed on the front-surface side of the p type semiconductor
substrate 1 and an n.sup.- layer 36 formed below the n layer 35. A
thin and high concentration p type layer 38 for suppressing dark
current is formed on a front-surface portion of the n layer 35. An
n.sup.+ layer 39 as a contact portion is formed on a central
surface portion of the surface layer 38.
[0038] A p layer 41 having a higher p concentration than that of
the substrate 1 is formed below the buried channel (n.sup.+ layer)
31 of the vertical charge transfer path 21. A p.sup.+ region 42
serving as an element separator is formed between (i) the n layer
31 and p layer 41 and (ii) the photodiode 22 located right from
then layer 31 and p layer 41, as shown in FIG. 1. A p.sup.+ region
42' having higher concentration than that of the semiconductor
layer 1 is formed below each p layer 41, and each p.sup.+ region
42' separates two adjacent photodiodes 22. Each p.sup.+ region 42'
is provided parting a boundary portion between adjacent pixel
units, that is, a portion corresponding to the light-shielding
member 28.
[0039] The p layer 41 formed below the buried channel 31 of the
vertical charge transfer path 21 extends to a surface end portion
of the n layer 35, which is located on the left side of the p layer
41, in the shown example. The p+ surface layer 38 at the end
portion is located at a portion retreating from a right end surface
of the n layer 35. The left end portion of the transfer electrode
film 33 extends to overlap with the p layer 41 up to the left end
portion of the p layer 41. The surface end portions of the transfer
electrode film 33 and the p layer 41 slightly overlap with the n
layer 35.
[0040] Such an overlapping configuration can be achieved because
there is a sufficient area on the front-surface side of the
semiconductor substrate 1 in the back-illuminated type. There is no
sufficient area in the front-surface illumination type where light
from a photograph subject is incident onto a front surface provided
with the photodiode and the signal reading circuit. Accordingly,
the end portion of the transfer electrode film can be extended only
up to a position corresponding to the end portion of the
photodiode. Thus, it is difficult to interpose a p layer
therebetween.
[0041] As in this embodiment, when the p layer 41 is interposed
between the transfer electrode film 33 and the n layer 35, it is
possible to decrease a reading-out voltage applied to the transfer
electrode film (used also as a reading-out electrode) 33 and to
reduce power consumption of the CCD solid-state imaging device.
[0042] On the insulating layer 32 formed on the outmost surface of
the semiconductor layer 1, the transfer electrode film 33 such as a
polysilicon film is formed. The insulating layer 45 is deposited
thereon. Openings are formed in the insulating layers 32 and 45 on
the n.sup.+ layer 39, and a metallic electrode 46 is deposited on
the insulating layer 45, thereby connecting the electrode 46 to the
n.sup.+ layer 39. The electrode 46 serves as an overflow drain of
the back-illuminated solid-state imaging device 100.
[0043] When an image of a photographic subject is imaged by the
back-illuminated solid-state imaging device 100 having such a
configuration, light from the photographic subject is incident
through the back surface of the semiconductor substrate 1. The
incident light is concentrated by the micro lens 24, passes through
the color filter layer 23, and then enters the semiconductor layer
1.
[0044] When the light concentrated by the micro lens 24 enters the
semiconductor substrate 1, the light travels while being
concentrated toward the photodiode 22 corresponding to the micro
lens 24 and the color filter 23. The light is gradually absorbed in
the semiconductor substrate 1, and the light is photoelectrically
converted to generate pairs of holes and electrons.
[0045] In the back-illuminated solid-state imaging device 100, a
distance from the back surface of the semiconductor 1 to the n
region 22 of the photodiode is about 9 .mu.m. Accordingly, all the
incident light is gradually absorbed in the semiconductor substrate
1 and photoelectrically converted until the light reaches the
n.sup.+ region provided on the front-surface side of the
semiconductor substrate 1, that is, the charge transfer path 21.
Therefore, it is unnecessary to shield the vertical charge transfer
path 21 from light.
[0046] The electrons generated in the photoelectric conversion
region (a region from the p layer 25 to the n region 35) of each
pixel are accumulated in the n region 35 of the corresponding
pixel. When the reading-out voltage is applied to the transfer
electrode film 33, which is also used as the reading-out electrode,
the electrons are read out from the n region 35 to the buried
channel 31 on the right side in the shown example. Then, the
electrons are transferred to the horizontal charge transfer path
(not shown) along the vertical charge transfer path 21, and are
transferred to an amplifier along the horizontal charge transfer
path. The amplifier outputs a signal voltage based on the amount of
signal charges as an image signal.
[0047] Next, a manufacturing process of the back-illuminated
solid-state imaging device 100 will be described with reference to
FIGS. 2 to 7. First, an SOI (Si-on-insulator) substrate 50 shown in
FIG. 2 is prepared. The SOI substrate 50 includes a thick silicon
substrate 51, an oxide film layer 52 formed on a surface of the
thick silicon substrate 51, and a thin silicon layer 53 formed on a
surface of the oxide film layer 52.
[0048] Then, as shown in FIG. 3, marks 54 are formed in
predetermined positions of the surface of the SOI substrate 50. The
marks 54 are formed by etching the thin silicon layer 53 and the
oxide film layer 52 therebelow to expose the surface of the silicon
substrate 51.
[0049] Then, as shown in FIG. 4, a p type silicon layer 1 having a
thickness of about 10 .mu.m is epitaxially grown on the surface of
the SOI substrate 50 provided with the marks 54. The p type silicon
layer 1 serves as the p type silicon substrate 1 in FIG. 1.
[0050] When the p type silicon layer 1 is epitaxially grown on the
Si layer 53 of the SOI substrate 50 and on the marks 54 that
exposes the silicon substrate 51, concave parts 55 are formed on a
surface of the p type silicon layer 1 while being aligned with the
mark 54.
[0051] As shown in FIG. 5, using the concave parts 55 serving as
alignment marks, front-surface elements such as the buried channel
31 and the transfer electrode film 33 formed thereon described with
reference to FIG. 1, the photodiodes (not shown in FIG. 5), and an
aluminum wiring layer 56 are formed on the front-surface side of
the p type silicon layer 1.
[0052] After the elements are formed on the front-surface side of
the p type silicon substrate 1, a supporting substrate 57 that
supports the p type silicon substrate 1 is laminated onto the front
surface.
[0053] Then, as shown in FIG. 6, the silicon substrate (original
substrate) 51 of the SOI substrate 50 shown in FIG. 5 is removed by
etching. For example, when chemical etching is performed using KOH,
the silicon substrate 51 is etched and the etching stops at the
oxide film layer 52. However, the etching slightly progresses in
positions of the marks 54 because there is no oxide film layer 52.
The marks 54 are exposed as concave parts on the back-surface side
of the p type semiconductor layer 1.
[0054] Then, although not shown, optical elements such as the color
filters 23, the light-shielding members 28, and the micro lenses 24
described in FIG. 1 are formed on the back-surface side of the p
type silicon substrate 1, using the alignment marks 54 as the
aligning basis.
[0055] Accordingly, it is possible to align the back-surface
elements with the front-surface elements with high precision, and
it is also possible to make the width of the light-shielding
element 28 as narrow as possible, thus preventing color
mixture.
[0056] In FIGS. 2 to 6, the marks 55 which are formed above the
mark 54 during the growth of the p type epitaxial layer 1 have the
same size as the marks 54. However, actually, the size of the marks
55 gets narrower and shallower as the epitaxial layer 1 gets
thicker as shown in FIG. 7. Accordingly, it is preferable to form
the marks 54, taking the decrease in size into consideration. And,
it is also preferable to form other marks based on the mark 55
instead of using the marks 55 directly as aligning basis, and then
to form elements on the front-side surface while the formed
elements are aligned with the other marks as the aligning
basis.
[0057] In the embodiment described above, the back-illuminated
solid-state imaging device 100 is described as an example. However,
the embodiment described above is also applicable to general
semiconductor devices in which elements and patterns are formed on
both front and back surfaces.
[0058] For example, in an electronic device shown in FIG. 8, a
semiconductor integrated circuit 59 is formed on the front surface
thereof, a Si substrate is used as the supporting substrate 57, and
the Si substrate 57 is attached to the front surface of a substrate
101 for an electronic device with the Van der Waals' force. When
the silicon substrate 51 of the SOI substrate 50 is etched, the
silicon substrate 51 below the oxide film 52 is left thinly as a Si
layer and devices such as an FET 58 are formed on the front surface
of the thinly-left Si layer 51.
[0059] When the electronic devices 58 are formed on the
back-surface side of the substrate 101, the marks 54 are not
exposed to outside as "concave parts." However, the marks 54 are
easily visible because the silicon layer 51 is thin. In addition,
the marks 54 are easily visible because the crystallinity at the
marks 54 is different from the vicinity of the mark 54 in the early
stage of the epitaxial growth.
[0060] A silicon layer may be formed on the oxide film layer 52
after wholly removing the silicon substrate 51 by etching and then,
an element may be formed on the silicon layer rather than on the
semiconductor substrate 51. For example, the electronic devices may
be formed on the oxide film layer 52 by the use of a polysilicon
layer or an amorphous silicon layer formed at low temperature, or a
silicon crystal layer formed by annealing them using a laser.
[0061] As described above, according to the embodiment, when the
elements are formed on both front and back surfaces of the silicon
substrate for electronic device 1, it is possible to align the
front-surface elements and the back-surface elements with high
precision and to manufacture the high-performance and high-quality
electronic devices with low cost.
[0062] In the silicon substrate for electronic device according to
the invention, it is possible to manufacture the high-performance
and high-quality electronic devices because it is possible to
perform highly precise alignment between the front surface and the
back surface. In addition, when the back-illuminated solid-state
imaging element is manufactured, it is possible to manufacture a
solid-state imaging element with high aperture ratio, preventing
color mixture.
* * * * *