U.S. patent application number 12/782217 was filed with the patent office on 2010-11-18 for method of layout of pattern.
This patent application is currently assigned to Elpida Memory, Inc.. Invention is credited to Michio INOUE, Yorio TAKADA.
Application Number | 20100293515 12/782217 |
Document ID | / |
Family ID | 43069539 |
Filed Date | 2010-11-18 |
United States Patent
Application |
20100293515 |
Kind Code |
A1 |
INOUE; Michio ; et
al. |
November 18, 2010 |
METHOD OF LAYOUT OF PATTERN
Abstract
A method of layout of pattern includes the following processes.
A graphic data of a first wiring in a first area of a semiconductor
wafer is extracted. The first area is a semiconductor chip forming
area. The first area is surrounded by a scribed area of the
semiconductor wafer. The first area includes a second area. The
second area is bounded with the scribed area. The second area has a
second distance from a boundary between the semiconductor chip
forming area and the scribed area to an boundary between the first
area and the second area. A first dummy pattern in the first area
is laid out. The first dummy pattern has at least a first distance
from the first wiring. A second dummy pattern in the second area is
laid out. The second dummy pattern has at least the first distance
from the first wiring. The second dummy pattern has at least a
third distance from the first dummy pattern.
Inventors: |
INOUE; Michio; (Tokyo,
JP) ; TAKADA; Yorio; (Tokyo, JP) |
Correspondence
Address: |
YOUNG & THOMPSON
209 Madison Street, Suite 500
Alexandria
VA
22314
US
|
Assignee: |
Elpida Memory, Inc.
Tokyo
JP
|
Family ID: |
43069539 |
Appl. No.: |
12/782217 |
Filed: |
May 18, 2010 |
Current U.S.
Class: |
716/130 ;
716/118 |
Current CPC
Class: |
H01L 21/76865 20130101;
G06F 30/394 20200101; H01L 23/538 20130101; G06F 30/39 20200101;
G06F 30/398 20200101; H01L 2924/0002 20130101; H01L 2924/14
20130101; H01L 23/5386 20130101; G06F 30/392 20200101; H01L 23/528
20130101; H01L 2924/0002 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
716/14 ;
716/8 |
International
Class: |
G06F 17/50 20060101
G06F017/50 |
Foreign Application Data
Date |
Code |
Application Number |
May 18, 2009 |
JP |
P2009-120291 |
Claims
1. A method of layout of pattern, the method comprising: extracting
a graphic data of a first wiring in a first area of a semiconductor
wafer, wherein the first area is a semiconductor chip forming area,
the first area is surrounded by a scribed area of the semiconductor
wafer, and the first area includes a second area, the second area
being bounded with the scribed area, the second area having a
second distance from a boundary between the semiconductor chip
forming area and the scribed area to an boundary between the first
area and the second area; laying out a first dummy pattern in the
first area, the first dummy pattern having at least a first
distance from the first wiring; and laying out a second dummy
pattern in the second area, the second dummy pattern having at
least the first distance from the first wiring, the second dummy
pattern having at least a third distance from the first dummy
pattern.
2. The method according to claim 1, wherein laying out the first
dummy pattern comprises: setting a third area that encompasses the
first wiring, the third area being included in the first area; and
laying out the first dummy pattern not to overlap the third
area.
3. The method according to claim 2, wherein the third area is set
such that a boundary between the first area and the third area has
the first distance from a pattern edge of the first wiring.
4. The method according to claim 1, wherein laying out the first
dummy pattern comprises: setting a third area that encompasses the
first wiring; laying out a third dummy pattern in the first area;
and removing an overlapping portion of the third dummy pattern
which is disposed over the third area to decide a layout of the
first dummy pattern.
5. The method according to claim 4, wherein the third area is set
such that a boundary between the first area and the third area has
the first distance from a pattern edge of the first wiring.
6. The method according to claim 1, wherein laying out the second
dummy pattern is performed after laying out the first dummy
pattern.
7. The method according to claim 6, wherein laying out the second
dummy pattern comprises: setting a fourth area encompassing the
first wiring; setting a fifth area encompassing the first dummy
pattern; setting a sixth area covering the first area without the
second area; and laying out the second dummy pattern in the first
area not to overlap the fourth, fifth and sixth areas.
8. The method according to claim 7, wherein the fourth area is set
such that a boundary between the first area and the fourth area has
the first distance from a pattern edge of the first wiring, and the
fifth area is set such that a boundary between the first area and
the fifth area has the third distance from a pattern edge of the
first dummy pattern.
9. The method according to claim 6, wherein laying out the second
pattern comprises: setting a fourth area encompassing the first
wiring; setting a fifth area encompassing the first dummy pattern;
setting a sixth area covering the first area without the second
area; laying out a fourth dummy pattern in the first area; and
removing an overlapping portion of the fourth dummy pattern which
is disposed over the fourth, fifth and sixth areas to decide a
layout of the second dummy pattern.
10. The method according to claim 9, wherein the fourth area is set
such that a boundary between the first area and the fourth area has
the first distance from a pattern edge of the first wiring, and the
fifth area is set such that a boundary between the first area and
the fifth area has the third distance from a pattern edge of the
first dummy pattern.
11. The method according to claim 10, further comprising: checking
a width of the second dummy pattern after deciding the layout of
the second dummy pattern; and removing a part of the second dummy
pattern, the width of the removed part of the second dummy pattern
being smaller than a predetermined value.
12. The method according to claim 10, further comprising: checking
an area dimension of the second dummy pattern after deciding the
layout of the second dummy pattern; and dividing a part of the
second dummy pattern into a plurality of divided patterns, the area
dimensions of the part of the second dummy pattern being larger
than a predetermined value before dividing, each of the divided
pattern having a smaller area dimension than the predetermined
value.
13. The method according to claim 1, wherein the first dummy
pattern comprises a plurality of fifth dummy patterns, each of the
fifth dummy pattern having a predetermined shape.
14. The method according to claim 13, wherein the fifth dummy
pattern comprises a plurality kind of sub-patterns, each kind of
sub-patterns having a predetermined shape.
15. The method according to claim 13, wherein the second dummy
pattern comprises a plurality of sixth dummy patterns, at least two
of the sixth dummy pattern having different shapes from each
other.
16. The method according to claim 13, wherein the predetermined
shape is a square shape or a rectangular shape.
17. The method according to claim 14, wherein the predetermined
shape is a square shape, and each kind of sub-patterns having a
different length at one side of the square shape.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a method of layout of
pattern.
[0003] Priority is claimed on Japanese Patent Application No.
2009-120291, filed May 18, 2009, the content of which is
incorporated herein by reference.
[0004] 2. Description of the Related Art
[0005] For manufacturing a semiconductor device including wirings,
a CMP (Chemical Mechanical Polishing) method is generally used to
planarize the upper surface of an interlayer insulating film, the
interlayer insulating film being formed over the wirings.
[0006] When the CMP method is performed to planarize the interlayer
insulating layer, the flatness of the upper surface of the
interlayer insulating film depends on the density of wiring layers
underlying the interlayer insulating film. Therefore, in an area
having a low density of wiring, a phenomenon such as dishing is
likely to be caused. The upper surface of the interlayer insulating
film is over-polished and a concave is formed on the upper surface
of the interlayer insulating film. Japanese Unexamined Patent
Applications, First Publications, Nos. JP-A-2002-158278 and
JP-A-2002-208676 each disclose a technique of adjusting the density
of wiring layers by laying out dummy patterns. The dummy patterns
are formed by the same layer as the wiring layer which is necessary
to operate circuits in the semiconductor device. The dummy patterns
are not used for operations of circuits of the semiconductor
device.
[0007] A scribed area (dicing area) is provided on the periphery of
each semiconductor chip. The semiconductor chips are arranged over
a semiconductor wafer. The scribed area (dicing area) has a width
in the range of approximately 50 .mu.m to approximately 100.mu.m.
The dicing process is carried out to dice the semiconductor wafer
into plural semiconductor chips. In the scribed area, various kinds
of marks such as an alignment mark are usually disposed. The
various kinds of marks such as an alignment mark can be used for
alignments of wirings in a previous manufacturing process including
diffusion processes for the semiconductor chip. In the scribed
area, check patterns are also disposed. The check patterns are laid
out to check the states during the manufacturing process of the
semiconductor chip. When the aforementioned marks or patterns are
optically measured, it is preferable not to lay out the
aforementioned marks or patterns near the dummy patterns, in order
to prevent malfunction due to interference with dummy patterns. The
scribed area has a lower density of wiring than the density of
wirings laid out in the semiconductor chip area. The scribed area
is lower in wiring density than the semiconductor chip area.
Therefore, when the polishing is performed by the CMP method, an
over-polishing is likely to be caused. The affection of the
over-polishing in the scribed area influences the semiconductor
chip forming area, the semiconductor chip forming area being
adjacent to the scribed area. The interlayer insulating film will
generally be thin in the semiconductor chip forming area.
Therefore, the reliability of the semiconductor chip is likely to
decreases, and predetermined patterns are likely to be difficult to
form during a manufacturing process after an interlayer insulating
film is formed.
[0008] Japanese Unexamined Patent Application, First Publication,
No. JP-A-2002-208676 discloses that to prevent the interlayer
insulating film from being thin near the scribed area, CMP dummy
patterns are laid out such that the density of the CMP dummy
patterns is over 50 percents, and enlarged dummy patterns are laid
out.
[0009] Japanese Unexamined Patent Application, First Publication,
No. JP-A-2002-208676 discloses that dummy patterns are changed in
size and the size-changed dummy patterns are then placed such that
the density of wirings is over 50 percents in a predetermined area.
Therefore, the process for laying out of the dummy patterns will be
complicated.
SUMMARY
[0010] In one embodiment, a method of layout of pattern may
include, but is not limited to, the following processes. A first
dummy pattern is laid out in a first area of a semiconductor wafer.
The first area includes a first wiring. The first dummy pattern has
a first distance from the first wiring. A second dummy pattern is
laid out in the first area, the second pattern having a second
distance from the first wiring. The second pattern has a third
distance from the first dummy pattern.
[0011] In another embodiment, a method of manufacturing a
semiconductor device may include, but is not limited to, the
following processes. A first wiring and first and second dummy
patterns are formed over a semiconductor wafer. The first wiring
and first and second dummy patterns are positioned in a first area
of the semiconductor wafer. The first dummy pattern has a first
distance from the first wiring. The second pattern has a second
distance from the first wiring. The second pattern has a third
distance from the first dummy pattern. The first area is bounded
with a second area of the semiconductor wafer. An interlayer
insulative film is formed over the first and second areas. The
interlayer insulative film covers the first wiring, the first and
second dummy patterns. A chemical mechanical polishing process is
performed to polish the interlayer insulative film. The first and
second dummy patterns prevent the interlayer insulative film in the
first area from being polished, while allowing the interlayer
insulative film in the second area to be polished.
[0012] In still another embodiment, a method of layout of pattern
may include, but is not limited to, the following processes. A
first dummy pattern is laid out in a first area which is included
in a chip area of a semiconductor wafer. The first area is bounded
with a scribed area of the semiconductor wafer. The first area
includes a first wiring. The first dummy pattern has a first
distance from the first wiring. A second dummy pattern is laid out
in the first area after laying out the first dummy pattern. The
second pattern has a second distance from the first wiring. The
second pattern has a third distance from the first dummy pattern.
The first, second and third distances are unchanged once the first
dummy pattern and the second dummy pattern have been laid out.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The above features and advantages of the present invention
will be more apparent from the following description of certain
preferred embodiments taken in conjunction with the accompanying
drawings, in which:
[0014] FIG. 1 is a plan view illustrating a part of a semiconductor
wafer including dummy patterns laid out according to an embodiment
of the invention;
[0015] FIG. 2 is a flowchart illustrating layout processes for
dummy patterns according to the embodiment of the invention;
[0016] FIG. 3 is a flowchart illustrating layout processes as a
modification to the layout process S3 in FIG. 2 according to
another embodiment of the invention;
[0017] FIG. 4 is a plan view showing a process for setting first
dummy pattern layout prohibition areas according to the embodiment
of the invention;
[0018] FIG. 5 is a plan view illustrating layout of first dummy
patterns according to the embodiment of the invention;
[0019] FIG. 6 is a plan view illustrating layout of first dummy
patterns according to another embodiment of the invention;
[0020] FIG. 7 is a plan view showing a process for setting second
dummy pattern layout prohibition areas according to the embodiment
of the invention;
[0021] FIG. 8 is a plan view illustrating layout of second dummy
patterns according to the embodiment of the invention;
[0022] FIG. 9 is a plan view showing a removal process for removing
second dummy patterns from the layout prohibition areas according
to the embodiment of the invention;
[0023] FIG. 10A is a plan view showing first dummy patterns
disposed along X and Y directions to form tetragonal lattice;
[0024] FIG. 10B is a plan view showing layout of first dummy
patterns having predetermined angles against X and Y
directions;
[0025] FIG. 11 is a plan view illustrating second dummy pattern
layout areas adjacent to scribed area according to the embodiment
of the invention;
[0026] FIG. 12A is a cross sectional view illustrating a
semiconductor chip including semiconductor devices with first dummy
patterns which are disposed outside the scribed area; and
[0027] FIG. 12B is a cross sectional view illustrating a
semiconductor chip including semiconductor devices with first and
second dummy patterns which are disposed outside the scribed
area.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0028] In one embodiment, a method of layout of pattern may
include, but is not limited to, the following processes. A graphic
data of a first wiring in a first area of a semiconductor wafer is
extracted. The first area is a semiconductor chip forming area. The
first area is surrounded by a scribed area of the semiconductor
wafer. The first area includes a second area. The second area is
bounded with the scribed area. The second area has a second
distance from a boundary between the semiconductor chip forming
area and the scribed area to an boundary between the first area and
the second area. A first dummy pattern in the first area is laid
out. The first dummy pattern has at least a first distance from the
first wiring. A second dummy pattern in the second area is laid
out. The second dummy pattern has at least the first distance from
the first wiring. The second dummy pattern has at least a third
distance from the first dummy pattern.
[0029] In some cases, laying out the first dummy pattern may
include following processes. A third area that encompasses the
first wiring is set. The third area is included in the first area.
The first dummy pattern not to overlap the third area is laid
out.
[0030] In some cases, the third area may be set such that a
boundary between the first area and the third area has the first
distance from a pattern edge of the first wiring.
[0031] In some cases, laying out the first dummy pattern may
include following processes. A third area that encompasses the
first wiring is set. A third dummy pattern in the first area is
laid out. An overlapping portion of the third dummy pattern which
is disposed over the third area to decide a layout of the first
dummy pattern is removed.
[0032] In some cases, the third area may be set such that a
boundary between the first area and the third area has the first
distance from a pattern edge of the first wiring.
[0033] In some cases, laying out the second dummy pattern may be
performed after laying out the first dummy pattern.
[0034] In some cases, laying out the second dummy pattern may
include following processes. A fourth area encompassing the first
wiring is set. A fifth area encompassing the first dummy pattern is
set. A sixth area covering the first area without the second area
is set. The second dummy pattern in the first area not to overlap
the fourth, fifth and sixth areas is laid out.
[0035] In some cases, the fourth area may be set such that a
boundary between the first area and the fourth area has the first
distance from a pattern edge of the first wiring. The fifth area
may be set such that a boundary between the first area and the
fifth area has the third distance from a pattern edge of the first
dummy pattern.
[0036] In some cases, laying out the second pattern may include
following processes. A fourth area encompassing the first wiring is
set. A fifth area encompassing the first dummy pattern is set. A
sixth area covering the first area without the second area is set.
A fourth dummy pattern in the first area is laid out. An
overlapping portion of the fourth dummy pattern which is disposed
over the fourth, fifth and sixth areas to decide a layout of the
second dummy pattern is removed.
[0037] In some cases, the fourth area may be set such that a
boundary between the first area and the fourth area has the first
distance from a pattern edge of the first wiring. The fifth area
may be set such that a boundary between the first area and the
fifth area has the third distance from a pattern edge of the first
dummy pattern.
[0038] In some cases, the method may further include following
processes. A width of the second dummy pattern after deciding the
layout of the second dummy pattern is checked. A part of the second
dummy pattern is removed. The width of the removed part of the
second dummy pattern is smaller than a predetermined value.
[0039] In some cases, the method may further include following
processes. An area dimension of the second dummy pattern after
deciding the layout of the second dummy pattern is checked. A part
of the second dummy pattern into a plurality of divided patterns is
divided. The area dimensions of the part of the second dummy
pattern is larger than a predetermined value before dividing. Each
of the divided pattern has a smaller area dimension than the
predetermined value.
[0040] In some cases, the first dummy pattern may include a
plurality of fifth dummy patterns, each of the fifth dummy pattern
having a predetermined shape.
[0041] In some cases, the fifth dummy pattern may include a
plurality kind of sub-patterns, each kind of sub-patterns having a
predetermined shape.
[0042] In some cases, the second dummy pattern may include a
plurality of sixth dummy patterns. At least two of the sixth dummy
pattern have different shapes from each other.
[0043] In some cases, the predetermined shape may be a square shape
or a rectangular shape.
[0044] In some cases, the predetermined shape may be a square
shape, and each kind of sub-patterns having a different length at
one side of the square shape.
[0045] According to the aforementioned configurations, it is
possible to increase the density of wiring in the area adjacent to
the scribed area without performing complex logical operations.
Therefore, it is possible to prevent the interlayer insulating film
from being thin in the semiconductor chip formation area adjacent
to the scribed area.
[0046] In addition, it is possible to avoid the problem with
forming a short circuit between wiring layers due to increase of
parasitic capacitance or due to attachment of inclusions during
manufacturing processes, by laying out a second dummy pattern only
in a predetermined area adjacent to the scribed area.
[0047] The invention will be now described herein with reference to
illustrative embodiments. Those skilled in the art will recognize
that many alternative embodiments can be accomplished using the
teachings of the present invention and that the invention is not
limited to the embodiments illustrated for explanatory
purposes.
[0048] FIG. 1 is a plan view illustrating layout of dummy patterns
on a part of a semiconductor wafer. FIG. 1 illustrates an area
which is a part of a semiconductor wafer. Wiring layers 1 are
provided in a semiconductor chip forming area. The wiring layers 1
contribute to circuit operations. A scribed area 2 is laid out at
the periphery of the semiconductor chip forming area. The scribed
area 2 has a predetermined width. The width may be in the range of,
but not limited to, approximately 50 .mu.m to approximately 100
.mu.m. The semiconductor chip forming area is surrounded by the
scribed area 2. First dummy patterns 3 have a predetermined shape,
for example, but not limited to, a rectangular shape. A second
dummy pattern 4 is laid out within an area having a predetermined
distance 6 from the boundary between the scribed area 2 and the
semiconductor chip forming area.
[0049] The first dummy patterns 3, the second dummy pattern 4 and
the wirings 1 are formed by the same patterning process for
patterning the same wiring layer. The wiring layer may be made of,
but not limited to, metals such as tungsten, or polysilicon. The
wiring may have, but not limited to, a multi-layered structure that
includes a plurality of conductive layers. The wiring may be formed
by patterning a multi-layered structure that includes an insulating
layer such as silicon nitride and a metal layer underlying the
insulating layer.
[0050] FIG. 2 is a flowchart illustrating layout processes for
laying out dummy patterns.
[0051] In Step S1, graphic data is extracted. The graphic data
defines shape and position of the wiring 1 (FIG. 4) which has
previously been laid out in the semiconductor chip forming
area.
[0052] In Step S2, as shown in FIG. 4, first dummy pattern layout
prohibition areas 5 are set such that the first dummy pattern
layout prohibition areas 5 encompass the wirings 1. The first dummy
pattern layout prohibition areas 5 and the wirings 1 are separated
from each other by a predetermined distance. It is preferable to
prevent increase in parasitic capacitance of the wiring 1 due to
layout of dummy patterns adjacent to the wirings 1. It is
preferable that the wirings 1 which contribute circuit operations
are separated from dummy patterns by a predetermined distance. The
predetermined distance is adequate to cause no affection to circuit
operations of a semiconductor chip. Previously, it is determined
how much the dummy patterns are distant from the wirings 1. Then,
the first dummy pattern layout prohibition areas 5 are positioned
based on the previously determined distance.
[0053] In Step S3, as shown in FIG. 5, the first dummy patterns 3
which have a rectangular shape are laid out on the semiconductor
chip forming area. The first dummy patterns 3 are laid out at a
pitch which corresponds to a previously predetermined distance "a".
For laying out the first dummy patterns 3, logical operations are
performed to determine whether the first dummy pattern layout
prohibition area 5 which has been set in Step S2 overlaps the first
dummy pattern 3. If at least a part of the dummy pattern 3 overlaps
the first dummy pattern layout prohibition area 5, then the first
dummy pattern 3 is not laid out.
[0054] As another way, the first dummy patterns may be laid out by
two steps as described below.
[0055] In Step S3-1 in FIG. 3 and as shown in FIG. 6, the first
dummy patterns 3 are laid out at the pitch "a" entirely on the
semiconductor chip forming area. In this step, is not necessary to
consider positional relationship between the first dummy patterns 3
and the first dummy pattern layout prohibition area 5. As Step S3-2
in FIG. 3, the logical operations are performed based on the
positions of the first dummy patterns 3 and the first dummy pattern
layout prohibition areas 5. The first dummy pattern 3 if
overlapping at least a part of the first dummy pattern layout
prohibition area 5 is removed. As shown in FIG. 5, the first dummy
patterns 3 is permitted to be laid out as long as the first dummy
patterns 3 do not overlap the first dummy pattern layout
prohibition area 5.
[0056] In FIGS. 5 and 6, the first dummy patterns 3 have a
square-shape. In other cases, the first dummy patterns 3 may have a
rectangular-shape.
[0057] The size or the length of each side of the first dummy
pattern 3 is not limited. To work as dummy patterns, and to prevent
stripping of patterns during manufacturing processes, the size of
the first dummy pattern 3 is preferably in the range of 1.2 times
to 2 times of the minimum line width or design rule value of the
wiring 1.
[0058] Layout of the first dummy patterns 3 is not limited. It is
not essential that the first dummy patterns 3 are disposed along X
and Y directions to form square-matrix as shown in FIG. 10A. In
some cases, the first dummy patterns 3 may be laid out with a
predetermined angle to X and Y directions as shown in FIG. 10B.
[0059] The first dummy patterns 3 may have other shapes than the
rectangular-shape. For example, the first dummy patterns 3 may
have, but not limited to, a polygon-shape or a cross-shape.
[0060] The first dummy patterns 3 may include different patterns.
In some cases, the first dummy patterns 3 may include, but is not
limited to, a first square pattern and a second square pattern. The
first square pattern has a first length of one side. The second
square pattern has a second length of one side. The second length
is different from the first length. In other cases, the first dummy
patterns 3 may include, but is not limited to, one or more square
patterns and one or more rectangular patterns. In other cases, the
first dummy patterns 3 may include, but is not limited to, more
than two different shape patterns. As shown in FIGS. 10A and 10B,
the first dummy patterns 3 may include, but is not limited to,
patterns having different layout angles. In some cases, a plurality
of predetermined shape patterns may be used as the first dummy
patterns 3. The distance between each predetermined shape pattern
and the wiring 1 is optimized. The distance between the
predetermined shape patterns is optimized. Both the optimizations
are carried out independently from each other. After optimization,
the first dummy patterns 3 may be laid out.
[0061] In Step S4, as shown in FIG. 7, the second dummy pattern
layout prohibition areas 5a are laid out such that the second dummy
pattern layout prohibition areas 5a have a predetermined distance
from the outer peripheries of the wirings 1 and that the second
dummy pattern layout prohibition areas 5a encompass the wirings 1.
In some cases, the second dummy pattern layout prohibition areas 5a
may be, but is not limited to, the same as the first dummy pattern
layout prohibition areas 5 which have been previously set.
[0062] The second dummy pattern layout prohibition areas 5b are set
such that the second dummy pattern layout prohibition areas 5b
encompass the first dummy patterns 3, the second dummy pattern
layout prohibition areas 5b are separated by a predetermined
distance from the outer peripheries of the first dummy patterns 3.
In FIG. 7, the second dummy pattern layout prohibition areas 5b
encompass each group of the first dummy patterns 3, wherein the
second dummy pattern layout prohibition areas 5b are presented by
broken lines. In other cases, the second dummy pattern layout
prohibition areas 5b may encompass each of the first dummy patterns
3. In this case, one second dummy pattern layout prohibition area
5b may overlap part of another second pattern layout prohibition
area 5b. If a plurality of predetermined shape patterns are laid
out as the first dummy patterns 3, the second dummy pattern layout
prohibition areas 5b may be set such that the second dummy pattern
layout prohibition areas 5b encompasses each of the predetermined
shape patterns with different distances. The second dummy pattern
layout prohibition areas 5a and 5b may be set to have the same
distances from the wirings 1 and from the first dummy pattern
3.
[0063] The area which has a predetermined distance from the
boundary between the scribed area 2 and the semiconductor chip
forming area is set as the second dummy pattern disposition
permission areas 6. The second dummy pattern layout prohibition
area 7 is set inside the second dummy pattern disposition
permission area 6. As shown in FIG. 11, if the four semiconductor
chips 11 and the scribed area 2 are laid out, the second dummy
pattern layout permission areas 6 (diagonal line areas in FIG. 10)
are placed at the peripheral areas adjacent to the scribed area of
each semiconductor chips 11. The second dummy pattern layout
permission area 6 has a predetermined width. The second dummy
pattern layout prohibition areas 7 are the area inside the second
dummy pattern disposition permission areas 6.
[0064] In Step S5, as shown in FIG. 8, the second dummy pattern 4a
is laid out such that the second dummy pattern 4a covers entirely
the semiconductor chip forming area. The second dummy pattern 4a is
laid out to cover entirely the semiconductor chip forming area
without being divided into rectangular shape patterns.
[0065] In Step S6, as shown in FIG. 9, logical operations are
performed based on the positions of the previously set second dummy
pattern layout prohibition areas 5a, 5b and 7, so as to remove the
data of the second dummy pattern 4a which is included in the second
dummy layout area, while leaving the data of the second dummy
pattern 4 which is not included in the second dummy layout
area.
[0066] Layout of the second dummy pattern may be performed by
laying out the second dummy patterns entirely except for the second
dummy pattern layout prohibition areas 5a, 5b and 7.
[0067] Remaining second dummy pattern 4 may include pattern 9 in
FIG. 9 which is narrower than minimum line width of the wiring 1.
In Step S7, the second dummy pattern 4 which does not satisfy the
requirements for dimensions is extracted and removed.
[0068] In Step S7, the area of the second dummy pattern 4 which is
a continuing pattern may be calculated, and the second dummy
pattern 4 may be divided into patterns with smaller size if the
area of the second dummy pattern 4 is greater than the previously
set predetermined standard area.
[0069] According to the aforementioned Steps S1 to S7, as shown in
FIG. 1, the first dummy patterns 3 and the second dummy patterns 4
have been laid out.
[0070] The effects of laying out the dummy patterns described above
will be described below.
[0071] FIG. 12A is a cross sectional view illustrating a
semiconductor chip including semiconductor devices with first dummy
patterns which are laid out opposite sides with reference to the
scribed area 2.
[0072] The wirings 1 which contribute circuit operations and an
interlayer insulating film 52 are provided over a semiconductor
substrate 51. The first dummy patterns 3 with a rectangular shape
are provided.
[0073] As shown in FIG. 12A, if no wirings are provided at the
scribed area 2 or if the density of wirings is very low, a concave
portion is formed on the interlayer insulating film 52 by excesses
polishing by CMP. The concave portion will provide affection to
adjacent semiconductor chip forming area. The affection reduces the
film thickness of the interlayer insulating film which is disposed
over the wiring layer 1 adjacent to the scribed area 2.
[0074] FIG. 12B is a cross sectional view illustrating first and
second rectangular dummy patterns 3 and 4. The first and second
dummy patterns 3 and 4 are laid out using the aforementioned
methods.
[0075] The wiring density in the area adjacent to the scribed area
is increased by laying out the second dummy patterns 4. The
increased wiring density will prevent excess polishing by CMP.
Increasing the wiring density will shift the position S toward the
inside area of the scribed area 2, wherein is the edge of the
concave portion is positioned at the position S. Therefore, it is
possible to prevent thickness reduction of the interlayer
insulating film over the wiring layer 1 which is adjacent to the
scribed area 2.
[0076] In the present embodiment, in Steps S1 to S7, it is not
necessary to perform any complicated calculations. Therefore, it is
possible to easily lay out the first and second dummy patterns 3
and 4.
[0077] It is possible to prevent a short circuit formation between
wiring layers. The short circuit formation is due to increase of
parasitic capacitance or due to attachment of inclusions during
manufacturing processes. The short circuit formation can be
prevented by laying out the second dummy pattern only in the area
(6) with a predetermined width adjacent to the scribed area.
[0078] The second dummy pattern layout permission area 6 with a
predetermined width is set to be adjacent to the scribed area 2.
The width of the second dummy pattern layout permission area 6 is
not limited. It is preferable that the width of the second dummy
pattern layout permission area 6 is about one to two times of the
width of the scribed area 2.
[0079] The semiconductor device according to the embodiment of the
invention includes dummy patterns which are the same layer as the
wiring layer 1. The semiconductor device includes the first dummy
patterns 3 having a predetermined distance from the wiring 1.
Within the area 6 having a predetermined width adjacent to the
scribed area 2, the second dummy pattern 4 is laid out. The second
dummy pattern 4 is separated by a predetermined distance from the
wiring 1. The second dummy pattern 4 is separated by another
predetermined distance from the first dummy patterns 3.
[0080] The manufacture method of the semiconductor device having
the dummy patterns may include the following steps. The wiring
layer is formed in the semiconductor chip forming area of the
semiconductor wafer. Then, first dummy patterns are formed, which
have a predetermined distance from the wiring layer. Then, within
the area with a predetermined width adjacent to the scribed area
which encompasses the semiconductor chip forming area, the second
dummy patterns are formed. The second dummy pattern has a
predetermined distance from the wiring layer. The second dummy
pattern has a predetermined distance from the first dummy patterns.
Therefore, the wiring layer, the first and second dummy patterns
are formed. Then, each of the semiconductor chip forming areas is
divided into the semiconductor chips, wherein the semiconductor
chip forming area is divided along the scribed area. Therefore, the
semiconductor device is manufactured.
[0081] It is apparent that the present invention is not limited to
the above embodiments, but may be modified and changed without
departing from the scope and spirit of the invention.
* * * * *