U.S. patent application number 12/844037 was filed with the patent office on 2010-11-18 for memory arrays including memory levels that share conductors, and methods of forming such memory arrays.
Invention is credited to S. Brad Herner.
Application Number | 20100288996 12/844037 |
Document ID | / |
Family ID | 46327597 |
Filed Date | 2010-11-18 |
United States Patent
Application |
20100288996 |
Kind Code |
A1 |
Herner; S. Brad |
November 18, 2010 |
MEMORY ARRAYS INCLUDING MEMORY LEVELS THAT SHARE CONDUCTORS, AND
METHODS OF FORMING SUCH MEMORY ARRAYS
Abstract
A memory array is provided that includes a first memory level, a
second memory level and a conductor shared between the first and
second memory levels. The first memory level includes a first diode
and a first resistivity-switching material layer coupled in series
with the first diode. The second memory level includes a second
diode and a second resistivity-switching material layer coupled in
series with the second diode. The first and second
resistivity-switching material layers each comprise one or more of
Ni.sub.XO.sub.y, Nb.sub.xO.sub.y, Ti.sub.xO.sub.y, Hf.sub.xO.sub.y,
Al.sub.xO.sub.y, Mg.sub.xO.sub.y, Co.sub.xO.sub.y, Cr.sub.xO.sub.y,
V.sub.xO.sub.y, Zn.sub.xO.sub.y, Zr.sub.xO.sub.y, B.sub.xN.sub.y,
and Al.sub.xN.sub.y. Numerous other aspects are provided.
Inventors: |
Herner; S. Brad; (San Jose,
CA) |
Correspondence
Address: |
DUGAN & DUGAN, PC
245 Saw Mill River Road, Suite 309
Hawthorne
NY
10532
US
|
Family ID: |
46327597 |
Appl. No.: |
12/844037 |
Filed: |
July 27, 2010 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
11692151 |
Mar 27, 2007 |
7767499 |
|
|
12844037 |
|
|
|
|
10955549 |
Sep 29, 2004 |
|
|
|
11692151 |
|
|
|
|
10855784 |
May 26, 2004 |
6952030 |
|
|
10955549 |
|
|
|
|
10326470 |
Dec 19, 2002 |
|
|
|
10855784 |
|
|
|
|
Current U.S.
Class: |
257/5 ;
257/E21.078; 257/E45.001; 438/104 |
Current CPC
Class: |
H01L 29/0657 20130101;
H01L 29/868 20130101; G11C 17/16 20130101; G11C 11/39 20130101;
G11C 29/00 20130101; H01L 45/04 20130101; H01L 27/1021 20130101;
H01L 45/146 20130101; H01L 45/1233 20130101; G11C 7/00 20130101;
G11C 2213/71 20130101; G11C 5/02 20130101; H01L 27/2481 20130101;
H01L 27/2409 20130101; G11C 2213/77 20130101; H01L 29/0676
20130101; G11C 17/06 20130101; H01L 45/149 20130101 |
Class at
Publication: |
257/5 ; 438/104;
257/E45.001; 257/E21.078 |
International
Class: |
H01L 45/00 20060101
H01L045/00; H01L 21/16 20060101 H01L021/16 |
Claims
1. A memory array comprising: a first memory level comprising: a
first diode; and a first resistivity-switching material layer
coupled in series with the first diode; a second memory level above
the first memory level, the second memory level comprising: a
second diode; and a second resistivity-switching material layer
coupled in series with the second diode; and a conductor shared
between the first and second memory levels, wherein the first and
second resistivity-switching material layers each comprise one or
more of Ni.sub.xO.sub.y, Nb.sub.xO.sub.y, Ti.sub.xO.sub.y,
Hf.sub.xO.sub.y, Al.sub.xO.sub.y, Mg.sub.xO.sub.y, Co.sub.xO.sub.y,
Cr.sub.xO.sub.y, V.sub.xO.sub.y, Zn.sub.xO.sub.y, Zr.sub.xO.sub.y,
B.sub.xN.sub.y, and Al.sub.xN.sub.y.
2. The memory array of claim 1, wherein the first and second
resistivity-switching material layers each have a thickness between
about 5 angstroms and about 100 angstroms.
3. The memory array of claim 1, wherein the first and second
resistivity-switching material layers each comprise HfO.sub.2 or
Al.sub.2O.sub.3.
4. The memory array of claim 1, wherein the first and second
resistivity-switching material layers are formed by a deposition
process.
5. The memory array of claim 1, wherein the first and second
resistivity-switching material layers are formed by atomic layer
deposition.
6. The memory array of claim 1, wherein the first and second diodes
comprise p-i-n diodes.
7. The memory array of claim 1, wherein the first diode comprises a
bottom heavily doped p-type region, a middle intrinsic or lightly
doped region, and a top heavily doped n-type region.
8. The memory array of claim 1, wherein the second diode comprises
a bottom heavily doped n-type region, a middle intrinsic or lightly
doped region, and a top heavily doped p-type region
9. The memory array of claim 1, wherein the first and second diodes
comprise vertical polysilicon diodes.
10. A memory array comprising: a first memory level comprising: a
first conductor; a first diode formed above the first conductor; a
first resistivity-switching material layer formed above the first
conductor; and a second conductor formed above the first diode and
the first resistivity-switching material; and a second memory level
comprising: a second diode formed above the second conductor; a
second resistivity-switching material layer formed above the second
conductor; and a third conductor formed above the second diode and
the second resistivity-switching material, wherein the first memory
level and the second memory level share the second conductor, and
wherein the first and second resistivity-switching material layers
each comprise one or more of Ni.sub.xO.sub.y, Nb.sub.xO.sub.y,
Ti.sub.xO.sub.y, Hf.sub.xO.sub.y, Al.sub.xO.sub.y, Al.sub.xO.sub.y,
Mg.sub.xO.sub.y, Co.sub.xO.sub.y, Cr.sub.xO.sub.y, V.sub.xO.sub.y,
Zn.sub.xO.sub.y, Zr.sub.xO.sub.y, B.sub.xN.sub.y, and
Al.sub.xN.sub.y.
11. The memory array of claim 10, wherein the first and second
resistivity-switching material layers each have a thickness between
about 5 angstroms and about 100 angstroms.
12. The memory array of claim 10, wherein the first and second
resistivity-switching material layers each comprise HfO.sub.2 or
Al.sub.2O.sub.3.
13. The memory array of claim 10, wherein the first and second
resistivity-switching material layers are formed by a deposition
process.
14. The memory array of claim 10, wherein the first and second
resistivity-switching material layers are formed by atomic layer
deposition.
15. The memory array of claim 10, wherein the first and second
diodes comprise p-i-n diodes.
16. The memory array of claim 10, wherein the first diode comprises
a bottom heavily doped p-type region, a middle intrinsic or lightly
doped region, and a top heavily doped n-type region.
17. The memory array of claim 10, wherein the second diode
comprises a bottom heavily doped n-type region, a middle intrinsic
or lightly doped region, and a top heavily doped p-type region
18. The memory array of claim 10, wherein the first and second
diodes comprise vertical polysilicon diodes.
19. A method of forming a memory array, the method comprising:
forming a first memory level by: forming a first diode; and forming
a first resistivity-switching material layer coupled in series with
the first diode; forming a second memory level above the first
memory level by: forming a second diode; and forming a second
resistivity-switching material layer coupled in series with the
second diode; and forming a conductor shared between the first and
second memory levels, wherein the first and second
resistivity-switching material layers each comprise one or more of
Ni.sub.xO.sub.y, Nb.sub.xO.sub.y, Ti.sub.xO.sub.y, Hf.sub.xO.sub.y,
Al.sub.xO.sub.y, Mg.sub.xO.sub.y, Co.sub.xO.sub.y, Cr.sub.xO.sub.y,
V.sub.xO.sub.y, Zn.sub.xO.sub.y, Zr.sub.xO.sub.y, B.sub.xN.sub.y,
and Al.sub.xN.sub.y.
20. The method of claim 19, wherein the first and second
resistivity-switching material layers each have a thickness between
about 5 angstroms and about 100 angstroms.
21. The method of claim 19, wherein the first and second
resistivity-switching material layers each comprise HfO.sub.2 or
Al.sub.2O.sub.3.
22. The method of claim 19, wherein forming the first and second
resistance switching material layers comprises forming the
resistivity-switching material layer by a deposition process.
23. The method of claim 22, wherein the deposition process
comprises an atomic layer deposition process.
24. The method of claim 19, wherein the first and second diodes
comprise p-i-n diodes.
25. The method of claim 19, wherein the first diode comprises a
bottom heavily doped p-type region, a middle intrinsic or lightly
doped region, and a top heavily doped n-type region.
26. The method of claim 19, wherein the second diode comprises a
bottom heavily doped n-type region, a middle intrinsic or lightly
doped region, and a top heavily doped p-type region
27. The method of claim 12, wherein the first and second diodes
comprise vertical polysilicon diodes.
Description
REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent
application Ser. No. 11/692,151, "Method To Form Upward Pointing
P-I-N Diodes Having Large And Uniform Current," filed Mar. 27,
2007, now U.S. Pat. No. 7,767,499, which is a continuation-in-part
of U.S. patent application Ser. No. 10/955,549, "Nonvolatile Memory
Cell Without a Dielectric Antifuse Having High- and Low-Impedance
States," filed Sep. 29, 2004, hereinafter the '549 application,
which is a continuation-in-part of U.S. patent application Ser. No.
10/855,784, "An Improved Method for Making High-Density Nonvolatile
Memory," filed May 26, 2004, now U.S. Pat. No. 6,952,030,
hereinafter the '030 patent, which is a continuation of U.S. patent
application Ser. No. 10/326,470, "An Improved Method for Making
High-Density Nonvolatile Memory," filed Dec. 19, 2002 (since
abandoned) and hereinafter the '470 application, all assigned to
the assignee of the present invention and hereby incorporated by
reference in their entirety
[0002] This application is related to Herner U.S. patent
application Ser. No. 11/692,153, "Large Array of Upward-Pointing
P-I-N Diodes Having Large and Uniform Current," now U.S. Pat. No.
7,586,773, Herner et al. U.S. patent application Ser. No.
11/692,144, "Method to Form a Memory Cell Comprising a Carbon
Nanotube Fabric Element and a Steering Element," now U.S. Pat. No.
7,667,999, and Herner et al. U.S. patent application Ser. No.
11/692,148, "Memory Cell Comprising a Carbon Nanotube Fabric
Element and a Steering Element," each filed on Mar. 27, 2007, and
hereby incorporated by reference in their entirety.
BACKGROUND
[0003] A diode has the characteristic of allowing very little
current flow below a certain turn-on voltage, and substantially
more current above the turn-on voltage. It has proven difficult to
form a large population of vertically oriented p-i-n diodes having
a bottom heavily doped p-type region, a middle intrinsic region,
and a top heavily doped n-type region with good uniformity of
current among the diodes when a voltage above the turn-on voltage
is applied.
[0004] It would be advantageous to form a large population of such
upward-pointing diodes having good uniformity, specifically for use
in a memory array.
SUMMARY
[0005] In a first aspect of the invention, a memory array is
provided that includes a first memory level, a second memory level
above the first memory level and a conductor shared between the
first and second memory levels. The first memory level includes a
first diode and a first resistivity-switching material layer
coupled in series with the first diode. The second memory level
includes a second diode and a second resistivity-switching material
layer coupled in series with the second diode. The first and second
resistivity-switching material layers each comprise one or more of
Ni.sub.xO.sub.y, Nb.sub.xO.sub.y, Ti.sub.xO.sub.y, Hf.sub.xO.sub.y,
Al.sub.xO.sub.y, Mg.sub.xO.sub.y, Co.sub.xO.sub.y, Cr.sub.xO.sub.y,
V.sub.xO.sub.y, Zn.sub.xO.sub.y, Zr.sub.xO.sub.y, B.sub.xN.sub.y,
and Al.sub.xN.sub.y.
[0006] In a second aspect of the invention, a memory array is
provided that includes a first memory level and a second memory
level. The first memory level includes a first conductor, a first
diode formed above the first conductor, a first
resistivity-switching material layer formed above the first
conductor, and a second conductor formed above the first diode and
the first resistivity-switching material. The second memory level
includes a second diode formed above the second conductor, a second
resistivity-switching material layer formed above the second
conductor, and a third conductor formed above the second diode and
the second resistivity-switching material. The first memory level
and the second memory level share the second conductor. The first
and second resistivity-switching material layers each comprise one
or more of Ni.sub.xO.sub.y, Nb.sub.xO.sub.y, Ti.sub.xO.sub.y,
Hf.sub.xO.sub.y, Al.sub.xO.sub.y, Mg.sub.xO.sub.y, Co.sub.xO.sub.y,
Cr.sub.xO.sub.y, V.sub.xO.sub.y, Zn.sub.xO.sub.y, Zr.sub.xO.sub.y,
B.sub.xN.sub.y, and Al.sub.xN.sub.y.
[0007] In a third aspect of the invention, a method of forming a
memory array is provided. The method includes forming a first
memory level, forming a second memory level above the first memory
level, and forming a conductor shared between the first and second
memory levels. Forming the first memory level includes forming a
first diode and forming a first resistivity-switching material
layer coupled in series with the first diode. Forming the second
memory level includes forming a second diode and forming a second
resistivity-switching material layer coupled in series with the
second diode. The first and second resistivity-switching material
layers each comprise one or more of Ni.sub.xO.sub.y,
Nb.sub.xO.sub.y, Ti.sub.xO.sub.y, Hf.sub.xO.sub.y, Al.sub.xO.sub.y,
Mg.sub.xO.sub.y, Co.sub.xO.sub.y, Cr.sub.xO.sub.y, V.sub.xO.sub.y,
Zn.sub.xO.sub.y, Zr.sub.xO.sub.y, B.sub.xN.sub.y, and
Al.sub.xN.sub.y.
[0008] Numerous other aspects are provided. Each aspect and
embodiment of the invention described herein can be used alone or
in combination with one another.
[0009] The preferred aspects and embodiments will now be described
with reference to the attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 is a perspective view of an embodiment of a memory
cell described in the '030 patent.
[0011] FIG. 2 is a perspective view of a portion of a first memory
level comprising memory cells like the cell of FIG. 1.
[0012] FIG. 3A is a perspective view showing two stacked memory
levels sharing conductors.
[0013] FIG. 3B is a cross-sectional view of the same structure.
[0014] FIG. 3C is a cross-sectional view showing two stacked memory
levels not sharing conductors.
[0015] FIG. 4A is a probability plot of current at applied voltage
of 2 volts for a population of downward-pointing diodes formed
according to an embodiment of the '030 patent.
[0016] FIG. 4B is a probability plot of current at applied voltage
of 2 volts for a population of upward-pointing diodes formed
according to an embodiment of the '030 patent.
[0017] FIG. 5 is perspective view of an embodiment of the present
invention.
[0018] FIG. 6 is a probability plot of current at applied voltage
of 2 volts for a population of upward-pointing diodes formed
according to the present invention.
[0019] FIGS. 7A-7D are cross-sectional views illustrating stages in
formation of two memory levels, the first memory level including
upward-pointing diodes formed according to an embodiment of the
present invention.
DETAILED DESCRIPTION
[0020] In the '470 application, the '030 patent, and the '549
application, all owned by the assignee of the present invention,
memory cells are described, each including a vertically oriented
p-i-n diode in the form of a pillar. Such a diode is formed of a
semiconductor material such as silicon, germanium, or a
silicon-germanium alloy, and has a bottom heavily doped region of a
first semiconductor type, a middle intrinsic or lightly doped
region, and a top heavily doped region of a second semiconductor
type opposite the first. It has been described to form this diode
in both orientations, either having a bottom heavily doped p-type
region and a top heavily doped n-type region, or the reverse, with
a bottom heavily doped n-type region and the top heavily doped
p-type region.
[0021] FIG. 1 illustrates a memory cell formed according to an
embodiment of the '030 patent. Such a memory cell includes a bottom
conductor 200 and a top conductor 400, with a vertically oriented
p-i-n diode 302 and a dielectric rupture antifuse 118 arranged
electrically in series between them. In its initial, unprogrammed
state, when a read voltage, for example of 2 volts, is applied
between bottom conductor 200 and top conductor 400, very little
current flows between them. Application of a relatively large
programming voltage alters the memory cell, and, after programming,
significantly more current flows between bottom conductor 200 and
top conductor 400 at the same read voltage. This difference in
current between the unprogrammed and programmed states is
measurable, and each can correspond to a distinct data state. For
example an unprogrammed cell can be considered to be a data "0,"
while a programmed cell is a data "1."
[0022] FIG. 2 shows a portion of a first memory level comprising a
plurality of bottom conductors 200, a plurality of pillars 300,
each pillar including a diode and a dielectric rupture antifuse as
in FIG. 1, and a plurality of top conductors 400. Each pillar 300
is disposed between one of bottom conductors 200 and one of top
conductors 400. Such a memory level can be formed above a substrate
such as a conventional monocrystalline silicon wafer. Multiple
memory levels can be formed stacked above the first to form a dense
monolithic three dimensional memory array.
[0023] A diode is a rectifying device, conducting current more
readily in one direction than in the other. A diode can be said to
point in its direction of preferred conduction. A vertically
oriented diode having n-type semiconductor material at the bottom
and p-type semiconductor material at the top can be said to be
downward-pointing, while a vertically oriented diode having p-type
semiconductor material at the bottom and n-type semiconductor
material at the top can be said to be upward-pointing.
[0024] Note that in this application, when terms indicating spatial
relationships, like "upward," "downward," "above," "below," and the
like are used, these terms are relative to the substrate, which is
assumed to be at the bottom of the frame of reference. For example,
if a first element is described to be above a second element, the
first element is farther from the substrate than the second.
[0025] In a vertically stacked memory array, it is preferred for
vertically adjacent memory levels to share conductors, as shown in
perspective view in FIG. 3A, in which conductors 400 serve both as
the top conductors of the first memory level M0 and as the bottom
conductors of the second memory level M1. The same structure is
shown in a cross-sectional view in FIG. 3B. FIG. 3C shows a
cross-sectional view of an array in which conductors are not
shared.
[0026] In FIG. 3C, each memory level has bottom conductors (200,
500), pillars (300, 600), and top conductors (400, 700), with an
interlevel dielectric separating memory levels M0 and M1, with no
conductors shared. The architecture of FIGS. 3A and 3B requires
fewer masking steps and reduces fabrication costs to produce the
same density of memory cells as shown in FIG. 3C.
[0027] Sharing of conductors, as in FIGS. 3A and 3B, is most
readily achieved electrically if diodes on adjacent levels point in
opposite directions, for example if the first memory level M0
diodes are upward-pointing, while the second memory level M1 diodes
are downward-pointing. A stacked array of only upward-pointing or
only downward-pointing diodes will generally be formed with
conductors not shared, as in FIG. 3C.
[0028] A large memory array will typically include millions of
memory cells, each of which must be sensed. There will inevitably
be some variation in characteristics between memory cells in such a
large array. To improve reliability, for a large array of memory
cells, it is advantageous to maximize the difference between the
unprogrammed and the programmed states, making them easier to
distinguish. It is further advantageous to minimize variation
between cells, and for the cells to behave as uniformly as
possible.
[0029] FIG. 4A is a probability plot showing unprogrammed current
and programmed current under the same applied read voltage for a
population of memory cells like those of the '030 patent (shown in
FIG. 1) including a diode and an antifuse in series between
conductors in which the diodes are all downward-pointing. That is,
the diodes have a bottom heavily doped n-type region, a middle
intrinsic region, and a top heavily doped p-type region.
[0030] It will be seen that the unprogrammed current for the
downward-pointing diodes, shown on line A, is tightly grouped close
to 10.sup.-12 amps. Similarly, the programmed current, shown on
line B, with the exception of one outlier, is tightly grouped
between about 10.sup.-5 and 10.sup.-4 amps. The distributions of
unprogrammed current (line A) and programmed current (line B) are
spaced well apart from each other and both are tightly grouped.
[0031] FIG. 4B is a probability plot showing unprogrammed current
and programmed current for a population of upward-pointing diodes
formed as in the '030 patent. The unprogrammed current, shown on
line C, is very similar to the unprogrammed current of the downward
pointing diode, line A of FIG. 4A. The programmed current, however,
shown on line D, shows a much wider distribution than the
programmed current on line B of FIG. 4A.
[0032] Programmed current for this upward-pointing diode ranges
from about 8.times.10.sup.-8 amps to 7.times.10.sup.-5 amps, a
difference approaching three orders of magnitude. A large number of
the population of these diodes have programmed current less than 1
microamp. This nonuniformity and low programmed current make the
upward-pointing diode of the '030 patent a less advantageous diode
for use in a large array than the downward-pointing diode.
[0033] In the present invention, a fabrication technique has been
found that yields a large population of upward-pointing vertically
oriented p-i-n diodes having good uniformity and large programmed
current. FIG. 5 shows an example of a memory cell including an
upward-pointing diode formed according to an embodiment of the
present invention. In this memory cell, the diode is paired with a
dielectric rupture antifuse, but, as will be described, the
pictured memory cell is only one of many possible uses for such a
diode, and is provided for clarity.
[0034] The memory cell includes bottom conductor 200 and top
conductor 400. Disposed between them are dielectric rupture
antifuse 118 (shown sandwiched between conductive barrier layers
110 and 111) and diode 302. Diode 302 includes bottom heavily doped
p-type region 112, middle intrinsic region 114, and top heavily
doped n-type region 116.
[0035] Diode 302 is formed of semiconductor material, for example
silicon, germanium, or a silicon-germanium alloy. For simplicity,
this semiconductor material will be described as silicon. The
silicon is preferably predominantly amorphous as deposited (though
p-type region 112, if doped in situ, will likely be polycrystalline
as deposited.) Top heavily doped n-type region 116 is doped with
arsenic.
[0036] In preferred embodiments, region 116 is formed by forming
middle intrinsic region 114, then doping the top of middle
intrinsic region 114 with arsenic by ion implantation. As will be
seen, this ion implantation step may take place either before or
after the patterning and etching step that forms the pillar. In
alternative embodiments, region 116 may be doped in situ by flowing
an appropriate source gas such as AsH.sub.3 during silicon
deposition at flows sufficient to result in an arsenic
concentration of at least 5.times.10.sup.20 atoms/cm.sup.3.
[0037] The bottom layer of top conductor 400 is a silicide-forming
metal such as titanium, cobalt, chromium, tantalum, platinum,
niobium, or palladium. Titanium and cobalt are preferred, and
titanium is most preferred. During an anneal performed to
crystallize the silicon, the silicide-forming metal reacts with the
silicon of top heavily doped n-type region 116 and forms a silicide
layer, for example titanium silicide.
[0038] FIG. 6 is a probability plot showing current at a read
voltage of about 2 volts for a population of such upward-pointing
diodes. As will be seen, this population has good uniformity, with
very little variation between diodes, and relative large forward
current, with median current of about 35.5 microamps. In
particular, note that programmed current at 2 volts for all diodes
in this population is above about 3 microamps.
[0039] As described, memory cells in the array described are sensed
by applying a read voltage across the memory cell. Ideally the read
voltage applied is the same for every memory cell in the array. In
practice, there will be some variation due to the location of each
memory cell within the array. For example, cells located farther
from sensing circuitry have a longer interconnect than cells
located closer to it. The increased length of the interconnect
results in increased resistance, resulting in smaller voltages
across the diodes of more distant cells as compared to closer
ones.
[0040] Small variations in the read current of the diode due to
variations in the interconnect length, and resistance, are not
inherent properties of the diode of the present invention, however.
The term "device level" will refer to a plurality of substantially
coplanar devices formed at the same level above a substrate, and
generally by the same processing steps. An example of a device
level is a memory level including a plurality of substantially
coplanar memory cells formed above a substrate.
[0041] In one example, in a device level including a population of
upward-pointing p-i-n diodes formed according to the present
invention, the voltage applied across the diode, i.e., between the
bottom p-type region and the top n-type region of the diode, is
between about 1.8 volts and about 2.2 volts for any diode in the
device level, regardless of its location. In addition, current
flowing through 99 percent of the diodes in this device level under
this applied voltage is at least 1.5 microamps.
[0042] In other examples, in the present invention a current of
about 1.5 microamps is achievable for 99 percent of diodes in a
device level when the voltage applied across the diode (between the
bottom p-type region and the top n-type region of the diode) is
between about 1.1 volts and about 3.0 volts, preferably between
about 1.5 volts and about 3.0 volts, most preferably between about
1.8 volts and about 2.2 volts, for example when the semiconductor
material is a silicon-germanium alloy such as Si.sub.0.8Ge.sub.0.2.
This population of p-i-n diodes may be a device level having
100,000 p-i-n diodes or more, for example 1,000,000 p-i-n diodes or
more.
[0043] In preferred embodiments, the device level is a memory level
comprising memory cells of the present invention, wherein the first
memory cells comprise programmed cells and unprogrammed cells. In
such a memory array, during use, some cells will be programmed
while others are unprogrammed.
[0044] In a preferred embodiment, when at least half of the memory
cells are programmed cells, current flowing through the p-i-n
diodes of at least 99 percent of the programmed cells when a
voltage between about 1.5 volts and about 3.0 volts is applied
between the bottom heavily doped p-type region and the top heavily
doped n-type region is at least 1.5 microamps, wherein the first
plurality of memory cells includes every memory cell in the first
memory level.
[0045] In more preferred embodiments, the applied voltage is
between about 1.8 volts and about 2.2 volts. This memory level of
memory cells may include 100,000 cells or more, for example
1,000,000 cells or more, each cell including an upward-pointing
p-i-n diode formed according to the present invention.
[0046] The upward-pointing diode of the present invention can
advantageously be used in an array of stacked memory levels sharing
conductors, most preferably having upward-pointing diodes
alternating with downward-pointing diodes on each memory level.
[0047] As described in Herner et al. U.S. patent application Ser.
No. 11/148,530, "Nonvolatile Memory Cell Operating by Increasing
Order in Polycrystalline Semiconductor Material," filed Jun. 8,
2005, which is hereby incorporated by reference, when deposited
amorphous silicon is crystallized in contact solely with materials
with which it has a high lattice mismatch, such as silicon dioxide
and titanium nitride, the polycrystalline silicon or polysilicon
forms with a high number of crystalline defects, causing it to be
high-resistivity. Application of a programming pulse through this
high-defect polysilicon apparently alters the polysilicon, causing
it to be lower-resistivity.
[0048] As described further in the '549 application, Herner U.S.
Pat. No. 7,176,064, "Memory Cell Comprising a Semiconductor
Junction Diode Crystallized Adjacent to a Silicide," and Herner
U.S. patent application Ser. No. 11/560,283, "Method for Making a
P-I-N Diode Crystallized Adjacent to a Silicide in Series with A
Dielectric Antifuse," now U.S. Pat. No. 7,682,920 (the "'920
patent"), which are hereby incorporated by reference, it has been
found that when deposited amorphous silicon is crystallized in
contact with a layer of an appropriate silicide, for example
titanium silicide, cobalt silicide, or a silicide formed of one of
the other named silicide-forming metals, the resulting crystallized
silicon is much higher quality, with fewer defects, and has much
lower resistivity.
[0049] The lattice spacing of titanium silicide or cobalt silicide
is very close to that of silicon, and it is believed that when
amorphous silicon is crystallized in contact with a layer of an
appropriate silicide at a favorable orientation, the silicide
provides a template for crystal growth of silicon, minimizing
formation of defects. Unlike the high-defect silicon crystallized
adjacent only to materials with which it has a high lattice
mismatch, application of a large electrical pulse does not
appreciably change the resistivity of this low-defect,
low-resistivity silicon crystallized in contact with the silicide
layer.
[0050] In some memory cells using a vertically oriented p-i-n
diode, then, as in the '549 application, the diode is formed of
higher-defect, higher-resistivity polysilicon, and the memory cell
is programmed by changing the resistivity state of the polysilicon.
For these high-defect-diode cells, the data state of the memory
cell is stored predominantly in the resistivity state of the
polysilicon of the diode.
[0051] In other memory cells, as in the '920 patent, the diode is
formed of low-defect, low-resistivity silicon, is paired with a
companion state-change element (in this case a dielectric rupture
antifuse) and the memory cell is programmed by changing the
characteristics of the state-change element (by rupturing the
antifuse, for example.) The term "state-change element" is used to
describe an element that can take two or more stable, mutually
distinguishable states, usually resistivity states, and can either
reversibly or irreversibly be switched between them.
[0052] For these low-defect-diode cells, the data state of the
memory cell is stored predominantly in the state-change element,
not in the state of the diode. (Note that this discussion has
described the use of silicon crystallized adjacent to a silicide.
The same effect can be expected for germanium and silicon-germanium
crystallized adjacent to a germanide or silicide-germanide.)
[0053] The upward-pointing p-i-n diodes of the present invention
are crystallized in contact with a silicide, and are thus of
low-defect, low-resistivity semiconductor material. If the
upward-pointing diodes of the present invention, then, are used in
memory cells, they are advantageously used when paired with a
state-change element, for example an antifuse or a
resistivity-switching element.
[0054] One example of such a resistivity-switching element is a
binary metal oxide, such as Ni.sub.xO.sub.y, Nb.sub.xO.sub.y,
Ti.sub.xO.sub.y, Hf.sub.xO.sub.y, Al.sub.xO.sub.y, Mg.sub.xO.sub.y,
Co.sub.xO.sub.y, Cr.sub.xO.sub.y, V.sub.xO.sub.y, Zn.sub.xO.sub.y,
Zr.sub.xO.sub.y, B.sub.xN.sub.y, or Al.sub.xN.sub.y, as described
in Herner et al. U.S. patent application Ser. No. 11/395,995,
"Nonvolatile Memory Cell Comprising a Diode and a
Resistance-Switching Material," which is hereby incorporated by
reference. Another example of a resistivity-switching element is a
carbon nanotube fabric, as described in Herner et al. U.S. patent
application Ser. No. 11/692,144, "Method To Program A Memory Cell
Comprising A Carbon Nanotube Fabric And A Steering Element," now
U.S. Pat. No. 7,667,999, filed on Mar. 27, 2007.
[0055] Note that the upward-pointing diodes of the present
invention may advantageously be used in many devices, and is not
limited to use in memory cells, or if used in memory cells, is not
limited to use in cells like those specifically described
herein.
[0056] A detailed example will be provided describing fabrication
of a first memory level formed above a substrate, the memory level
comprising memory cells having an upward-pointing diode and high-K
dielectric antifuse arranged in series between a bottom conductor
and a top conductor, as well fabrication of a second memory level
above it comprising downward-pointing diodes, the two memory levels
sharing conductors. Details from the '920 patent, and from the
other incorporated applications, may prove useful in fabrication of
this memory level.
[0057] To avoid obscuring the invention, not all details from these
or other incorporated documents will be included, but it will be
understood that none of their teaching is intended to be excluded.
For completeness, many details, including materials, steps, and
conditions, will be provided, but it will be understood by those
skilled in the art that many of these details can be changed,
augmented or omitted while the results fall within the scope of the
invention.
Example
[0058] Turning to FIG. 7A, formation of the memory begins with a
substrate 100. Substrate 100 can be any semiconducting substrate
known in the art, such as monocrystalline silicon, IV-IV compounds
like silicon-germanium or silicon-germanium-carbon, III-V
compounds, II-VII compounds, epitaxial layers over such substrates,
or any other semiconducting material. The substrate may include
integrated circuits fabricated therein.
[0059] An insulating layer 102 is formed over substrate 100.
Insulating layer 102 can be silicon oxide, silicon nitride,
Si.times.C.times.O.times.H film, or any other suitable insulating
material.
[0060] First conductors 200 are formed over the substrate 100 and
insulator 102. An adhesion layer 104 may be included between
insulating layer 102 and conducting layer 106 to help conducting
layer 106 adhere to insulating layer 102. If the overlying
conducting layer 106 is tungsten, titanium nitride is preferred as
adhesion layer 104. Conducting layer 106 can comprise any
conducting material known in the art, such as tungsten, or other
materials, including tantalum, titanium, or alloys thereof.
[0061] Once all the layers that will form the conductor rails have
been deposited, the layers will be patterned and etched using any
suitable masking and etching process to form substantially
parallel, substantially coplanar conductors 200, shown in FIG. 7A
in cross-section. Conductors 200 extend out of the page. In one
embodiment, photoresist is deposited, patterned by photolithography
and the layers etched, and then the photoresist removed using
standard process techniques.
[0062] Next a dielectric material 108 is deposited over and between
conductor rails 200. Dielectric material 108 can be any known
electrically insulating material, such as silicon oxide, silicon
nitride, or silicon oxynitride. In a preferred embodiment, silicon
dioxide deposited by a high-density plasma method is used as
dielectric material 108.
[0063] Finally, excess dielectric material 108 on top of conductor
rails 200 is removed, exposing the tops of conductor rails 200
separated by dielectric material 108, and leaving a substantially
planar surface. The resulting structure is shown in FIG. 7A. This
removal of dielectric overfill to form the planar surface can be
performed by any process known in the art, such as chemical
mechanical planarization ("CMP") or etchback. In an alternative
embodiment, conductors 200 could be formed by a Damascene method
instead.
[0064] Turning to FIG. 7B, next optional conductive layer 110 is
deposited. Layer 110 is a conductive material, for example titanium
nitride, tantalum nitride, or tungsten. This layer may be any
appropriate thickness, for example about 50 to about 200 angstroms,
preferably about 100 angstroms. In some embodiments barrier layer
110 may be omitted.
[0065] Next, in this example, a thin layer 118 of a dielectric
material or dielectric stack is deposited to form a dielectric
rupture antifuse. In one embodiment, a high-K dielectric, such as
HfO.sub.2, Al.sub.2O.sub.3, ZrO.sub.2, TiO.sub.2,
La.sub.2O.sub.3Ta.sub.2O.sub.5, RuO.sub.2, ZrSiO.sub.x,
AlSiO.sub.x, HfSiO.sub.x, HfAlO.sub.x, HfSiON, ZrSiAlO.sub.x,
HfSiAlO.sub.x, HfSiAlON, or ZrSiAlON, is deposited, for example by
atomic layer deposition. HfO.sub.2 and Al.sub.2O.sub.3 are
preferred.
[0066] If HfO.sub.2 is used, layer 118 preferably has a thickness
between about 5 and about 100 angstroms, preferably about 40
angstroms. If Al.sub.2O.sub.3 is used, layer 118 preferably has a
thickness between about 5 and about 80 angstroms, preferably about
30 angstroms. In alternative embodiments, the dielectric rupture
antifuse may comprise silicon dioxide.
[0067] Conductive layer 111 is deposited on layer 118. It can be
any appropriate conductive material, for example titanium nitride,
with any appropriate thickness, for example about 50 to about 200
angstroms, preferably about 100 angstroms. In some embodiments
conductive layer 111 may be omitted.
[0068] Next semiconductor material that will be patterned into
pillars is deposited. The semiconductor material can be silicon,
germanium, a silicon-germanium alloy, or other suitable
semiconductors, or semiconductor alloys. For simplicity, this
description will refer to the semiconductor material as silicon,
but it will be understood that the skilled practitioner may select
any of these other suitable materials instead.
[0069] Bottom heavily doped region 112 can be formed by any
deposition and doping method known in the art. The silicon can be
deposited and then doped, but is preferably doped in situ by
flowing a donor gas providing a p-type dopant atoms, for example
boron, during deposition of the silicon. In preferred embodiments,
the donor gas is BCl.sub.3, and p-type region 112 is preferably
doped to a concentration of about 1.times.10.sup.21 atoms/cm.sup.3.
Heavily doped region 112 is preferably between about 100 and about
800 angstroms thick, most preferably about 200 angstroms thick.
[0070] Intrinsic or lightly doped region 114 can be formed next by
any method known in the art. Region 114 is preferably silicon and
has a thickness between about 1200 and about 4000 angstroms,
preferably about 3000 angstroms. In general p-type dopants such as
boron tend to promote crystallization. Thus, the silicon of heavily
doped region 112 is like to be polycrystalline as deposited.
Intrinsic region 114, however, is preferably amorphous as
deposited.
[0071] Semiconductor regions 114 and 112 just deposited, along with
underlying conductive layer 111, dielectric rupture antifuse 118,
and conductive layer 110, will be patterned and etched to form
pillars 300. Pillars 300 should have about the same pitch and about
the same width as conductors 200 below, such that each pillar 300
is formed on top of a conductor 200. Some misalignment can be
tolerated.
[0072] Pillars 300 can be formed using any suitable masking and
etching process. For example, photoresist can be deposited,
patterned using standard photolithography techniques, and etched,
then the photoresist removed. Alternatively, a hard mask of some
other material, for example silicon dioxide, can be formed on top
of the semiconductor layer stack, with bottom antireflective
coating ("BARC") on top, then patterned and etched. Similarly,
dielectric antireflective coating ("DARC") can be used as a hard
mask.
[0073] The photolithography techniques described in Chen U.S.
patent application Ser. No. 10/728,436, "Photomask Features with
Interior Nonprinting Window Using Alternating Phase Shifting," now
U.S. Pat. No. 7,172,840, or Chen U.S. patent application Ser. No.
10/815,312, "Photomask Features with Chromeless Nonprinting Phase
Shifting Window," filed Apr. 1, 2004, both owned by the assignee of
the present invention and hereby incorporated by reference, can
advantageously be used to perform any photolithography step used in
formation of a memory array according to the present invention.
[0074] The diameter of the pillars 300 can be as desired, for
example between about 22 nm and about 130 nm, preferably between
about 32 nm and about 80 nm, for example about 45 nm. Gaps between
pillars 300 are preferably about the same as the diameter of the
pillars. Note that when a very small feature is patterned as a
pillar, the photolithography process tends to round corners, such
that the cross-section of the pillar tends to be circular,
regardless of the actual shape of the corresponding feature in the
photomask.
[0075] Dielectric material 108 is deposited over and between the
semiconductor pillars 300, filling the gaps between them.
Dielectric material 108 can be any known electrically insulating
material, such as silicon oxide, silicon nitride, or silicon
oxynitride. In a preferred embodiment, silicon dioxide is used as
the insulating material.
[0076] Next the dielectric material on top of pillars 300 is
removed, exposing the tops of pillars 300 separated by dielectric
material 108, and leaving a substantially planar surface. This
removal of dielectric overfill can be performed by any process
known in the art, such as CMP or etchback.
[0077] After CMP or etchback, ion implantation is performed,
forming heavily doped n-type top regions 116. The n-type dopant is
preferably a shallow implant of arsenic, with implant energy of,
for example, 10 keV, and dose of about 3.times.10.sup.15/cm.sup.2.
This implant step completes formation of diodes 302. Note that some
thickness, for example about 300 to about 800 angstroms of silicon
is lost during CMP. Thus, the finished height of diode 302 may be
between about 800 and about 4000 angstroms, for example about 2500
angstroms for a diode having a feature size of about 45 nm.
[0078] Turning to FIG. 7C, next a layer 120 of a silicide-forming
metal, for example titanium, cobalt, chromium, tantalum, platinum,
niobium, or palladium, is deposited. Layer 120 is preferably
titanium or cobalt. If layer 120 is titanium, its thickness is
preferably between about 10 and about 100 angstroms, most
preferably about 20 angstroms. Layer 120 is followed by titanium
nitride layer 404. Layer 404 is preferably between about 20 and
about 100 angstroms, most preferably about 80 angstroms.
[0079] Next a layer 406 of a conductive material, for example
tungsten, is deposited. For example this layer may be about 1500
angstroms of tungsten formed by chemical vapor deposition ("CVD").
Layers 406, 404, and 120 are patterned and etched into rail-shaped
top conductors 400, which preferably extend in a direction
perpendicular to bottom conductors 200. The pitch and orientation
of top conductors 400 is such that each top conductor 400 is formed
on top of and contacting a row of pillars 300, and top conductors
400 preferably have about the same width as pillars 300. Some
misalignment can be tolerated.
[0080] Next a dielectric material (not shown) is deposited over and
between top conductors 400. The dielectric material can be any
known electrically insulating material, such as silicon oxide,
silicon nitride, or silicon oxynitride. In a preferred embodiment,
silicon oxide is used as this dielectric material.
[0081] Referring to FIG. 7C, note that layer 120 of a
silicide-forming metal is in contact with the silicon of top
heavily doped region 116. During subsequent elevated temperature
steps, the metal of layer 120 will react with some portion of the
silicon of heavily doped region p-type 116 to form a silicide layer
(not shown), which is between the diode and top conductor 400.
Alternatively, this silicide layer can be considered to be part of
top conductor 400.
[0082] This silicide layer forms at a temperature lower than the
temperature required to crystallize silicon, and thus will form
while intrinsic region 114 and heavily doped p-type region 116 are
still largely amorphous. If a silicon-germanium alloy is used for
top heavily doped region 116, a silicide-germanide layer may form,
for example of cobalt silicide-germanide or titanium
silicide-germanide. Similarly, if germanium is used, a germanide
will form.
[0083] In the example just described, diodes 302 of FIG. 7C are
upward-pointing, comprising a bottom heavily doped p-type region, a
middle intrinsic region, and top heavily doped n-type region. In
preferred embodiments, the next memory level to be monolithically
formed above this one shares conductor 400 with the first memory
level just formed. That is, top conductor 400 of the first memory
level serves as the bottom conductor of the second memory level. If
conductors are shared in this way, then the diodes in the second
memory level are preferably downward-pointing, comprising a bottom
heavily doped n-type region, a middle intrinsic region, and a top
heavily doped p-type region.
[0084] Turning to FIG. 7D, next optional conductive layer 210,
high-K dielectric antifuse layer 218, and optional conductive layer
211 are formed, preferably of the same materials, the same
thicknesses, and using the same methods as layers 110, 118, and
111, respectively, of pillars 300 in the first memory level.
[0085] Diodes are formed next. Bottom heavily doped region 212 can
be formed by any deposition and doping method known in the art. The
silicon can be deposited and then doped, but is preferably doped in
situ by flowing a donor gas providing n-type dopant atoms, for
example phosphorus, during deposition of the silicon. Heavily doped
region 212 is preferably between about 100 and about 800 angstroms
thick, most preferably about 100 to about 200 angstroms thick.
[0086] The next semiconductor region to be deposited is preferably
undoped. In deposited silicon, though, n-type dopants such as
phosphorus exhibit strong surfactant behavior, tending to migrate
toward the surface as the silicon is deposited. Deposition of
silicon will continue with no dopant gas provided, but phosphorus
atoms migrating upward, seeking the surface, will unintentionally
dope this region. As described in Herner U.S. patent application
Ser. No. 11/298,331, "Deposited Semiconductor Structure to Minimize
N-Type Dopant Diffusion and Method of Making," now U.S. Pat. No.
7,405,465, which is hereby incorporated by reference, the
surfactant behavior of phosphorus in deposited silicon is inhibited
with the addition of germanium.
[0087] Preferably a layer of a silicon-germanium alloy including at
least 10 atomic percent ("at %") germanium is deposited at this
point, for example about 200 angstroms of Si.sub.0.8Ge.sub.0.2,
which is deposited undoped, with no dopant gas providing
phosphorus. This thin layer is not shown in FIG. 7D.
[0088] Use of this thin silicon-germanium layer minimizes unwanted
diffusion of n-type dopant into the intrinsic region to be formed,
maximizing its thickness. A thicker intrinsic region minimizes
leakage current across the diode when the diode is under reverse
bias, reducing power loss. This method allows the thickness of the
intrinsic region to be increased without increasing the overall
height of the diode. As will be seen, the diodes will be patterned
into pillars. Increasing the height of the diode increases the
aspect ratio of the etch step forming these pillars and the step to
fill gaps between them. Both etch and fill are more difficult as
aspect ratio increases.
[0089] Intrinsic region 214 can be formed next by any method known
in the art. Region 214 is preferably silicon and preferably has a
thickness between about 1100 and about 3300 angstroms, preferably
about 1700 angstroms. The silicon of heavily doped region 212 and
intrinsic region 214 is preferably amorphous as deposited.
[0090] Semiconductor regions 214 and 212 just deposited, along with
underlying conductive layer 211, high-K dielectric layer 218, and
conductive layer 210, will be patterned and etched to form pillars
600. Pillars 600 should have about the same pitch and about the
same width as top conductors 400 below, such that each pillar 600
is formed on top of a top conductor 400. Some misalignment can be
tolerated. Pillars 600 can be patterned and etched using the same
techniques used to form pillars 300 of the first memory level.
[0091] Dielectric material 108 is deposited over and between the
semiconductor pillars 600, filling the gaps between them. As in the
first memory level, the dielectric material 108 on top of pillars
600 is removed, exposing the tops of pillars 600 separated by
dielectric material 108, and leaving a substantially planar
surface. After this planarization step, ion implantation is
performed, forming heavily doped p-type top regions 116. The p-type
dopant is preferably a shallow implant of boron, with an implant
energy of, for example, 2 keV, and dose of about
3.times.10.sup.15/cm.sup.2. This implant step completes formation
of diodes 602. Some thickness of silicon is lost during the CMP
step, so the completed diodes 602 have a height comparable to that
of diodes 302.
[0092] Top conductors 700 are formed in the same manner and of the
same materials as conductors 400, which are shared between the
first and second memory levels. A layer 220 of a silicide-forming
metal is deposited, followed by titanium nitride layer 704 and
layer 706 of a conductive material, for example tungsten. Layers
706, 704, and 220 are patterned and etched into rail-shaped top
conductors 700, which preferably extend in a direction
substantially perpendicular to conductors 400 and substantially
parallel to conductors 200.
[0093] Preferably after all of the memory levels have been formed,
a single crystallizing anneal is performed to crystallize the
semiconductor material of diodes 302, 602, and those diodes formed
on additional levels, for example at 750.degree. C. for about 60
seconds, though each memory level can be annealed as it is formed.
The resulting diodes will generally be polycrystalline. Since the
semiconductor material of these diodes is crystallized in contact
with a silicide or silicide-germanide layer with which it has a
good lattice match, the semiconductor material of diodes 302, 602,
etc. will be low-defect and low-resistivity.
[0094] In the embodiment just described, conductors were shared
between memory levels. That is, top conductor 400 of the first
memory level serves as the bottom conductor of the second memory
level. In other embodiments, an interlevel dielectric can be formed
above the first memory level of FIG. 7C, its surface planarized,
and construction of a second memory level begun on this planarized
interlevel dielectric, with no shared conductors.
[0095] In the example given, the diodes of the first memory level
were upward-pointing, with p-type silicon on the bottom and n-type
on top, while the diodes of the second memory level were reversed,
pointing downward with n-type silicon on the bottom and p-type on
top. In embodiments in which conductors are shared, diode types
preferably alternate, upward on one level and downward on the next.
In embodiments in which conductors are not shared, diodes may be
all one type, either upward- or downward-pointing. The terms upward
and downward refer to the direction of current flow when the diode
is under forward bias.
[0096] In some embodiments, it may be preferred for the programming
pulse to be applied with the diode in reverse bias. This may have
advantages in reducing or eliminating leakage across the unselected
cells in the array, as described in Kumar et al. U.S. patent
application Ser. No. 11/496,986, "Method For Using A Memory Cell
Comprising Switchable Semiconductor Memory Element With Trimmable
Resistance," filed Jul. 28, 2006, owned by the assignee of the
present invention and hereby incorporated by reference.
[0097] Fabrication of two memory levels above a substrate has been
described. Additional memory levels can be formed in the same
manner, forming a monolithic three dimensional memory array.
[0098] A monolithic three dimensional memory array is one in which
multiple memory levels are formed above a single substrate, such as
a wafer, with no intervening substrates. The layers forming one
memory level are deposited or grown directly over the layers of an
existing level or levels. In contrast, stacked memories have been
constructed by forming memory levels on separate substrates and
adhering the memory levels atop each other, as in Leedy U.S. Pat.
No. 5,915,167, "Three dimensional structure memory." The substrates
may be thinned or removed from the memory levels before bonding,
but as the memory levels are initially formed over separate
substrates, such memories are not true monolithic three dimensional
memory arrays.
[0099] A monolithic three dimensional memory array formed above a
substrate comprises at least a first memory level formed at a first
height above the substrate and a second memory level formed at a
second height different from the first height. Three, four, eight,
or indeed any number of memory levels can be formed above the
substrate in such a multilevel array.
[0100] An alternative method for forming a stacked memory array in
which conductors are formed using Damascene construction, rather
than using subtractive techniques as in the examples provided, is
described in Radigan et al., U.S. patent application Ser. No.
11/444,936, "Conductive Hard Mask to Protect Patterned Features
During Trench Etch," now U.S. Pat. No. 7,575,984, assigned to the
assignee of the present invention and hereby incorporated by
reference.
[0101] The methods of Radigan et al. may be used instead to form an
array according to the present invention. In the methods of Radigan
et al., a conductive hard mask is used to etch the diodes beneath
them. In adapting this hard mask to the present invention, in
preferred embodiments the bottom layer of the hard mask, which is
in contact with the silicon of the diode, is preferably titanium,
cobalt, chromium, tantalum, platinum, niobium, or palladium. During
anneal, then, a silicide forms, providing the silicide
crystallization template. In this embodiment, the ion implantation
step to form the top heavily doped p-type region takes place before
the patterning step to form the pillars.
[0102] In the examples provided so far, the silicide is formed at
the top contact of the diode. In alternative embodiments, it may be
formed elsewhere, for example at the bottom contact. For example,
the silicon of the diode can be deposited directly on a
silicide-forming metal, and a state-change element, such as an
antifuse or a resistivity-switching element (carbon nanotube fabric
or a binary metal oxide, for example) formed on top of the
diode.
[0103] The upward-pointing diode of the present invention has been
described as used in a one-time programmable memory cell (when
paired with an antifuse) or in a rewriteable memory cell (when
paired with a resistivity-switching element.) It will be
understood, however, it is impractical to list all possible uses of
the diode of the present invention, and that these examples are not
intended to be limiting.
[0104] Detailed methods of fabrication have been described herein,
but any other methods that form the same structures can be used
while the results fall within the scope of the invention.
[0105] The foregoing detailed description has described only a few
of the many forms that this invention can take. For this reason,
this detailed description is intended by way of illustration, and
not by way of limitation. It is only the following claims,
including all equivalents, which are intended to define the scope
of this invention.
* * * * *