U.S. patent application number 12/832778 was filed with the patent office on 2010-10-28 for code detection.
This patent application is currently assigned to INTERDIGITAL TECHNOLOGY CORPORATION. Invention is credited to Gary Lomp, Fatih Ozluturk, Avi Silverberg.
Application Number | 20100272155 12/832778 |
Document ID | / |
Family ID | 21692981 |
Filed Date | 2010-10-28 |
United States Patent
Application |
20100272155 |
Kind Code |
A1 |
Lomp; Gary ; et al. |
October 28, 2010 |
CODE DETECTION
Abstract
A code transmitted in a wireless format is to be detected. A
power level associated with the code is determined. The determined
power level is compared with a plurality of thresholds. A test
statistic is increased or decreased based on which of the
thresholds that the determined power level falls within. If the
test statistic exceeds an acceptance threshold, the code is deemed
acquired. If the test statistic is below a dismissal threshold, the
code is deemed not present. If the test statistic does not exceed
the acceptance threshold and the test statistic is not below the
dismissal threshold, the testing for the code is repeated.
Inventors: |
Lomp; Gary; (Centerport,
NY) ; Ozluturk; Fatih; (Port Washington, NY) ;
Silverberg; Avi; (Commack, NY) |
Correspondence
Address: |
VOLPE AND KOENIG, P.C.;DEPT. ICC
UNITED PLAZA, 30 SOUTH 17TH STREET
PHILADELPHIA
PA
19103
US
|
Assignee: |
INTERDIGITAL TECHNOLOGY
CORPORATION
Wilmington
DE
|
Family ID: |
21692981 |
Appl. No.: |
12/832778 |
Filed: |
July 8, 2010 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10680943 |
Oct 8, 2003 |
7756190 |
|
|
12832778 |
|
|
|
|
09840769 |
Apr 24, 2001 |
6633600 |
|
|
10680943 |
|
|
|
|
09444079 |
Nov 22, 1999 |
6229843 |
|
|
09840769 |
|
|
|
|
09024473 |
Feb 17, 1998 |
5991332 |
|
|
09444079 |
|
|
|
|
08669769 |
Jun 27, 1996 |
5796776 |
|
|
09024473 |
|
|
|
|
60000775 |
Jun 30, 1995 |
|
|
|
Current U.S.
Class: |
375/141 ;
375/219; 375/E1.002 |
Current CPC
Class: |
H04L 1/0047 20130101;
H04B 1/7085 20130101; H04W 52/247 20130101; H04B 2201/70707
20130101; H04J 13/004 20130101; H04J 13/0077 20130101; H04J 13/10
20130101; H04B 1/707 20130101; H04J 13/12 20130101; H04W 52/325
20130101; H04W 52/52 20130101; H04W 52/262 20130101; H04B 1/7075
20130101; H04W 52/04 20130101; H04B 1/7077 20130101; H04B 7/2637
20130101; H04B 2201/70701 20130101; H04W 52/08 20130101; H04W 52/50
20130101; H04B 1/70753 20130101; H04W 52/343 20130101; Y02D 10/00
20180101; H04B 1/7093 20130101; H04J 2013/0037 20130101; H04L 1/004
20130101; H04B 1/70754 20130101; H04W 52/241 20130101; H04J 13/00
20130101; H04W 52/245 20130101; H04B 1/70755 20130101; H04B 1/70758
20130101; H04B 1/708 20130101; H04L 1/0001 20130101; H04B 7/264
20130101; H04L 25/0212 20130101; H04L 2027/003 20130101; H04B 1/711
20130101; H04B 1/7115 20130101; H04W 52/367 20130101; H04L 27/206
20130101; H04L 27/2332 20130101; H04W 52/54 20130101; H04W 52/44
20130101; H04B 1/712 20130101; H04L 1/0042 20130101; H04W 52/60
20130101; H04J 13/0048 20130101; H04W 52/24 20130101; H04B 7/2628
20130101; H04N 1/3333 20130101; H04W 52/143 20130101; G06F 13/374
20130101; H03H 17/06 20130101; H04L 1/0059 20130101; H04L 2027/0053
20130101; H04W 52/322 20130101; H04W 52/36 20130101; H04W 52/26
20130101; H03H 17/0226 20130101; H04B 2201/70702 20130101; H04J
13/16 20130101; H04L 1/0054 20130101; H04W 52/346 20130101; H04B
1/709 20130101; H04B 2201/70703 20130101; H04B 2201/7071 20130101;
H04J 13/107 20130101; H04N 1/00912 20130101; H04N 2201/3335
20130101; H04L 5/1446 20130101; H04W 52/146 20130101 |
Class at
Publication: |
375/141 ;
375/219; 375/E01.002 |
International
Class: |
H04B 1/38 20060101
H04B001/38; H04B 1/707 20060101 H04B001/707 |
Claims
1. A subscriber unit comprising: circuitry configured to receive at
least one first bit and second bits on a channel; wherein the at
least one first bit is a flag and the second bits indicates an
amount of data; wherein the flag has a first value indicating that
the subscriber unit is allowed to transmit data or at least one
second value indicating that the subscriber unit is not allowed to
transmit data; and the circuitry further configured on a condition
that the flag has the first value to transmit data on a reverse
link based on the amount of data indicated by the second bits.
2. The subscriber unit of claim 1 wherein the second bits indicate
an increment of data.
3. The subscriber unit of claim 1 wherein the flag and the
indicated amount of data are updated dynamically.
4. The subscriber unit of claim 1 wherein the flag is further
configured to indicate an availability of an access channel.
5. The subscriber unit of claim 1 wherein the reverse link is a
code division multiple access reverse link.
6. The subscriber unit of claim 1 wherein the channel is a control
channel.
7. The subscriber unit of claim 6 wherein the control channel is a
broadcast channel.
8. A method comprising: receiving, by a subscriber unit, at least
one first bit and second bits on a channel; wherein the at least
one first bit is a flag and the second bits indicates an amount of
data; wherein the flag has a first value indicating that the
subscriber unit is allowed to transmit data or at least one second
value indicating that the subscriber unit is not allowed to
transmit data; and transmitting data on a reverse link based on the
amount of data indicated by the second bits, by the subscriber
unit, on a condition that the flag has the first value.
9. The method of claim 8 wherein the second bits indicate an
increment of data.
10. The method of claim 8 wherein the flag and the indicated amount
of data are updated dynamically.
11. The method of claim 8 wherein the flag is further configured to
indicate an availability of an access channel.
12. The method of claim 8 wherein the reverse link is a code
division multiple access reverse link.
13. The method of claim 8 wherein the channel is a control
channel.
14. The method of claim 13 wherein the control channel is a
broadcast channel.
15. A base station comprising: circuitry configured to transmit at
least one first bit and second bits on a channel; wherein the at
least one first bit is a flag and the second bits indicates an
amount of data; wherein the flag has a first value indicating that
a subscriber unit is allowed to transmit data or at least one
second value indicating that the subscriber unit is not allowed to
transmit data; and the circuitry further configured on a condition
that the flag has the first value to receive data on a reverse link
based on the amount of data indicated by the second bits.
16. The base station of claim 15 wherein the second bits indicate
an increment of data.
17. The base station of claim 15 wherein the flag and the indicated
amount of data are updated dynamically.
18. The base station of claim 15 wherein the flag is further
configured to indicate an availability of an access channel.
19. The base station of claim 15 wherein the reverse link is a code
division multiple access reverse link.
20. The base station of claim 15 wherein the channel is a control
channel.
21. The base station of claim 20 wherein the control channel is a
broadcast channel.
Description
[0001] This application is a continuation of U.S. patent
application Ser. No. 10/680,943, filed Oct. 8, 2003, which is a
continuation of U.S. patent application Ser. No. 09/840,769, filed
Apr. 24, 2001, which issued as U.S. Pat. No. 6,633,600 on Oct. 14,
2003, which is a continuation of U.S. patent application Ser. No.
09/444,079, filed Nov. 22, 1999, which issued as U.S. Pat. No.
6,229,843 on May 8, 2001, which is a continuation of U.S. patent
application Ser. No. 09/024,473, filed Feb. 17, 1998, which issued
as U.S. Pat. No. 5,991,332 on Nov. 23, 1999, which is a divisional
of U.S. patent application Ser. No. 08/669,769, filed Jun. 27,
1996, which issued as U.S. Pat. No. 5,796,776 on Aug. 18, 1998,
which claims priority from U.S. Provisional Application Number
60/000,775 filed Jun. 30, 1995.
BACKGROUND
[0002] Providing quality telecommunication services to user groups
which are classified as remote, such as rural telephone systems and
telephone systems in underdeveloped countries, has proved to be a
challenge over recent years. The past needs created by these
services have been partially satisfied by wireless radio services,
such as fixed or mobile frequency division multiplex (FDM),
frequency division multiple access (FDMA), time division multiplex
(TDM), time division multiple access (TDMA) systems, combination
frequency and time division systems (FD/TDMA), and other land
mobile radio systems. Often, these remote services are faced with
more potential users than can be supported simultaneously by their
frequency or spectral bandwidth capacity.
[0003] Recognizing these limitations, recent advances in wireless
communications have used spread spectrum modulation techniques to
provide simultaneous communication by multiple users. Spread
spectrum modulation refers to modulating a information signal with
a spreading code signal; the spreading code signal being generated
by a code generator where the period Tc of the spreading code is
substantially less than the period of the information data bit or
symbol signal. The code may modulate the carrier frequency upon
which the information has been sent, called frequency-hopped
spreading, or may directly modulate the signal by multiplying the
spreading code with the information data signal, called
direct-sequence spreading (DS). Spread-spectrum modulation produces
a signal with bandwidth substantially greater than that required to
transmit the information signal, and synchronous reception and
despreading of the signal at the receiver demodulator recovers the
original information. The synchronous demodulator uses a reference
signal to synchronize the despreading circuits to the input
spread-spectrum modulated signal in order to recover the carrier
and information signals. The reference signal can be a spreading
code which is not modulated by an information signal. Such use of a
synchronous spread-spectrum modulation and demodulation for
wireless communication is described in U.S. Pat. No. 5,228,056
entitled SYNCHRONOUS SPREAD-SPECTRUM COMMUNICATIONS SYSTEM AND
METHOD by Donald L. Schilling, which is incorporated herein by
reference.
[0004] Spread-spectrum modulation in wireless networks offers many
advantages because multiple users may use the same frequency band
with minimal interference to each user's receiver. Spread-spectrum
modulation also reduces effects from other sources of interference.
In addition, synchronous spread-spectrum modulation and
demodulation techniques may be expanded by providing multiple
message channels for a user, each spread with a different spreading
code, while still transmitting only a single reference signal to
the user. Such use of multiple message channels modulated by a
family of spreading codes synchronized to a pilot spreading codes
for wireless communication is described in U.S. Pat. No. 5,166,951
entitled HIGH CAPACITY SPREAD-SPECTRUM CHANNEL by Donald L.
Schilling, which is incorporated herein by reference.
[0005] One area in which spread-spectrum techniques are used is in
the field of mobile cellular communications to provide personal
communication services (PCS). Such systems desirably support large
numbers of users, control Doppler shift and fade, and provide high
speed digital data signals with low bit error rates. These systems
employ a family or orthogonal or quasi-orthogonal spreading codes,
with a pilot spreading code sequence synchronized to the family of
codes. Each user is assigned one of the spreading codes as a
spreading function. Related problems of such a system are:
supporting a large number of users with the orthogonal codes,
handling reduced power available to remote units, and handling
multipath fading effects. Solutions to such problems include using
phased-array antennas to generate multiple steerable beams, using
very long orthogonal or quasi-orthogonal code sequences which are
reused by cyclic shifting of the code synchronized to a central
reference, and diversity combining of multipath signals. Such
problems associated with spread spectrum communications, and
methods to increase capacity of a multiple access, spread-spectrum
system are described in U.S. Pat. No. 4,901,307 entitled SPREAD
SPECTRUM MULTIPLE ACCESS COMMUNICATION SYSTEM USING SATELLITE OR
TERRESTRIAL REPEATERS by Gilhousen et al. which is incorporated
herein by reference.
SUMMARY
[0006] A code transmitted in a wireless format is to be detected. A
power level associated with the code is determined. The determined
power level is compared with a plurality of thresholds. A test
statistic is increased or decreased based on which of the
thresholds that the determined power level falls within. If the
test statistic exceeds an acceptance threshold, the code is deemed
acquired. If the test statistic is below a dismissal threshold, the
code is deemed not present. If the test statistic does not exceed
the acceptance threshold and the test statistic is not below the
dismissal threshold, the testing for the code is repeated.
BRIEF DESCRIPTION OF THE DRAWING(S)
[0007] FIG. 1 is a block diagram of a code division multiple access
communication system according to the present invention.
[0008] FIG. 2a is a block diagram of a 36 stage linear shift
register suitable for use with long spreading-code of the code
generator of the present invention.
[0009] FIG. 2b is a block diagram of circuitry which illustrates
the feed-forward operation of the code generator.
[0010] FIG. 2c is a block diagram of an exemplary code generator of
the present invention including the circuit for generating
spreading-code sequences from the long spreading-code and the short
spreading-codes.
[0011] FIG. 2d is an alternate embodiment of the code generator
circuit including delays to compensate for electrical circuit
delays.
[0012] FIG. 3a is a graph of the constellation points of the pilot
spreading-code QPSK signal.
[0013] FIG. 3b is a graph of the constellation points of the
message channel QPSK signal.
[0014] FIG. 3c is a block diagram of exemplary circuitry which
implements the method of tracking the received spreading-code phase
of the present invention.
[0015] FIG. 4 is a block diagram of the tracking circuit that
tracks the median of the received multipath signal components.
[0016] FIG. 5a is a block diagram of the tracking circuit that
tracks the centroid of the received multipath signal
components.
[0017] FIG. 5b is a block diagram of the Adaptive Vector
Correlator.
[0018] FIG. 6 is a block diagram of exemplary circuitry which
implements the acquisition decision method of the correct
spreading-code phase of the received pilot code of the present
invention.
[0019] FIG. 7 is a block diagram of an exemplary pilot rake filter
which includes the tracking circuit and digital phase locked loop
for despreading the pilot spreading-code, and generator of the
derotation factors of the present invention.
[0020] FIG. 8a is a block diagram of an exemplary adaptive vector
correlator and matched filter for despreading and combining the
multipath components of the present invention.
[0021] FIG. 8b is a block diagram of an alternative implementation
of the adaptive vector correlator and adaptive matched filter for
despreading and combining the multipath components of the present
invention.
[0022] FIG. 8c is a block diagram of an alternative embodiment of
the adaptive vector correlator and adaptive matched filter for
despreading and combining the multipath components of the present
invention.
[0023] FIG. 8d is a block diagram of the Adaptive Matched Filter of
one embodiment of the present invention.
[0024] FIG. 9 is a block diagram of the elements of an exemplary
radio carrier station (RCS) of the present invention.
[0025] FIG. 10 is a block diagram of the elements of an exemplary
modem interface unit (MIU) of the RCS shown in FIG. 9.
[0026] FIG. 11 is a high level block diagram showing the transmit,
receive, control, and code generation circuitry of the CDMA
modem.
[0027] FIG. 12 is a block diagram of the transmit section of the
CDMA modem.
[0028] FIG. 13 is a block diagram of an exemplary modem input
signal receiver.
[0029] FIG. 14 is a block diagram of an exemplary convolutional
encoder as used in the present invention.
[0030] FIG. 15 is a block diagram of the receive section of the
CDMA modem.
[0031] FIG. 16 is a block diagram of an exemplary adaptive matched
filter as used in the CDMA modem receive section.
[0032] FIG. 17 is a block diagram of an exemplary pilot rake as
used in the CDMA modem receive section.
[0033] FIG. 18 is a block diagram of an exemplary auxiliary pilot
rake as used in the CDMA modem receive section.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
[0034] Referring to FIG. 1, the radio links 161 to 165 incorporate
Broadband Code Division Multiple Access (B-CDMA.TM.) as the mode of
transmission in both the Uplink and Downlink directions. CDMA (also
known as Spread Spectrum) communication techniques used in multiple
access systems are well-known, and are described in U.S. Pat. No.
5,228,056 entitled SYNCHRONOUS SPREAD-SPECTRUM COMMUNICATION SYSTEM
AND METHOD by Donald T. Schilling which is incorporated herein by
reference. The described exemplary system uses the Direct Sequence
(DS) spreading technique. In each modem, one or more CDMA
modulators performs the spread-spectrum spreading code sequence
generation. In addition, the modems generate, for example, a
pseudonoise (PN) spreading sequence; and perform complex DS
modulation to produce quadrature phase shift keying (QPSK) signals
for the In-phase (I) and Quadrature (Q) channels. Pilot signals are
generated and transmitted with the modulated signals. The pilot
signals of the present embodiment are spreading codes which are not
modulated by data. The pilot signals are used for system
synchronization, carrier phase recovery, and for estimating the
impulse response of the radio channel. Each SU includes a single
pilot generator and at least one CDMA modulator and demodulator,
called a CDMA modem. Each RCS 104, 105, 110 has a single pilot
generator plus sufficient CDMA modulators and demodulators for all
the logical channels in use by all SUs.
[0035] The CDMA demodulator despreads the signal, with appropriate
processing to combat or exploit multipath propagation effects.
Parameters concerning the received power level are used to generate
the Automatic Power Control (APC) information which, in turn, is
transmitted to the other end (i.e. from the SU to the RCS or from
the RCS to the SU). The APC information is used to control transmit
power of the automatic forward power control (AFPC) and automatic
reverse power control (ARPC) links. In addition, each RCS 104, 105
and 110 may perform Maintenance Power Control (MPC), in a manner
similar to APC, to adjust the initial transmit power of each SU
111, 112, 115, 117 and 118.
[0036] Diversity combining at the radio antennas of the RCS 104,
105 and 110 is not necessary because CDMA has inherent frequency
diversity due to the spread bandwidth. Receivers may include
Adaptive Matched Filters (AMFs) (not shown in FIG. 1), however,
which combine the multipath signals. In the exemplary embodiment,
AMFs perform Maximal Ratio Combining.
[0037] Logical Communication Channels
[0038] A "channel" of the prior art is usually regarded as a
communications path which is part of an interface and which can be
distinguished from other paths of that interface without regard to
its content. In the case of CDMA, however, separate communications
paths are distinguished only by their content. The term "logical
channel" is used to distinguish the separate data streams, which
are logically equivalent to channels in the conventional sense. All
logical channels and sub-channels of the present invention are
mapped to a common 64 kilo-symbols per second (ksym/s) QPSK stream.
Some channels are synchronized to associated pilot codes which are
generated in the same way and perform much the same function as the
system Global Pilot Code. The system pilot signals are not,
however, considered logical channels.
[0039] Several logical communication channels are used over the RF
communication link between the RCS and SU. Each logical
communication channel has either a fixed, pre-determined spreading
code or a dynamically assigned spreading code. For both
pre-determined and assigned codes, the code phase is in synchronism
with the Pilot Code. Logical communication channels are divided
into two groups: the Global Channel (GC) group includes those
channels which are either transmitted from the base station RCS to
all the remote SUs or from any SU to the RCS of the base station
regardless of the SU's identity. These channels contain for all
users and include the channels used by SUs to gain access to
message communication channels. Channels in the Assigned Channels
(AC) group are those channels which are dedicated to communication
between the RCS and a particular SU.
[0040] The Global Channels (GC) group provides for 1) Broadcast
logical channels, which provide point to multipoint services for
broadcasting messages to all SUs and paging messages to SUs; and 2)
Access Control logical channels which provide point-to-point
services on global channels for SUs to access the system and obtain
assigned channels.
[0041] An Assigned Channel (AC) group contains the logical channels
that control a single telecommunication connection between the RCS
and a SU. The functions developed when an AC group is formed
consists of a pair of power control logical message channels for
each of the Uplink and Downlink connections, and depending on the
type of connection, one or more pairs of traffic channels. The
Bearer Control function performs the required forward error
control, bearer rate modification, and encryption functions. The
logical channels which constitute the BC and AC groups are
summarized below in Table 1.
TABLE-US-00001 TABLE 1 Logical Channels and sub-channels of the
B-CDMA Air Interface Direction (forward Channel Brief or Max Name
Abbr. Description reverse Bit rate BER Power level Pilot Global
Channels Fast FBCH Broadcasts F 16 kbit/s 1e-4 Fixed GLPT Broadcast
fast-changing Channel system information Slow SBCH Broadcasts F 16
kbit/s 1e-7 Fixed GLPT Broadcast paging Channel messages to FSUs
and slow-changing system information Access AXCH(i) For initial R
32 kbit/s 1e-7 Controlled by LAXT(i) Channels access APC attempts
by FSUs Control CTCH(i) For granting F 32 kbit/s 1e-7 Fixed GLPT
Channels access Assigned Channels 16 kbit/s TRCH/16 General POTS
F/R 16 kbit/s 1e-4 Controlled by F-GLPT POTS use APC R-ASPT 32
kbit/s TRCH/32 General POTS F/R 32 kbit/s 1e-4 Controlled by F-GLPT
POTS use APC R-ASPT 64 kbit/s TRCH/64N POTS use for F/R 64 kbit/s
1e-4 Controlled by F-GLPT POTS in-band APC R-ASPT modems/fax
Traffic TRCH/64L ISDN B F/R 64 kbit/s 1e-7 Controlled by F-GLPT
channel @ channel or LL APC R-ASPT 64 kbit/s- low BER D TRCH/16L
ISDN D F/R 16 kbit/s 1e-7 Controlled by F-GLPT channel channel APC
R-ASPT Order OW assigned F/R 32 kbit/s 1e-7 Controlled by F-GLPT
wire signaling APC R-ASPT channel channel APC APC carries APC F/R
64 kbit/s 2e-1 Controlled by F-GLPT channel commands APC R-ASPT
[0042] The APC data is sent at 64 kbit/sec. The APC logical channel
is not FEC coded to avoid delay and is transmitted at a low power
level to minimize capacity used for APC. Alternatively, the APC and
order wire (OW) data may be separately modulated using complex
spreading code sequences, or they may be time division multiplexed
with a 16 kbit/s traffic channel.
[0043] The Spreading Codes
[0044] The CDMA code generators used to encode the logical channels
of the present invention employ Linear Shift Registers (LSRs) with
feedback logic which is a method well known in the art. The code
generators of the present embodiment of the invention generate 64
synchronous unique sequences. Each RF communication channel uses a
pair of these sequences for complex spreading (in-phase and
quadrature) of the logical channels, so the generator gives 32
complex spreading sequences. The sequences are generated by a
single seed which is initially loaded into a shift register
circuit.
[0045] The Generation of Spreading Code Sequences and Seed
Selection
[0046] The spreading code period of the present invention is
defined as an integer multiple of the symbol duration, and the
beginning of the code period is also the beginning of the symbol.
The relation between bandwidths and the symbol lengths chosen for
the exemplary embodiment of the present invention is:
TABLE-US-00002 BW (MHZ) L (chips/symbol) 7 91 10 130 10.5 133 14
182 15 195
[0047] The spreading code length is also a multiple of 64 and of 96
for ISDN frame support. The spreading code is a sequence of
symbols, called chips or chip values. The general methods of
generating pseudorandom sequences using Galois Field mathematics is
known to those skilled in the art; however, the inventor has
derived a unique set, or family, of code sequences for the present
invention. First, the length of the linear feedback shift register
to generate a code sequence is chosen, and the initial value of the
register is called a "seed". Second, the constraint is imposed that
no code sequence generated by a code seed can be a cyclic shift of
another code sequence generated by the same code seed. Finally, no
code sequence generated from one seed can be a cyclic shift of a
code sequence generated by another seed.
[0048] The inventor has determined that the spreading code length
of chip values of the present invention is:
128.times.233415=29877120 (1)
[0049] The spreading codes are generated by combining a linear
sequence of period 233415 and a nonlinear sequence of period
128.
[0050] The nonlinear sequence of length 128 is implemented as a
fixed sequence loaded into a shift register with a feed-back
connection. The fixed sequence can be generated by an m-sequence of
length 127 padded with an extra logic 0, 1, or random value as is
well known in the art.
[0051] The linear sequence of length L=233415 is generated using a
linear feedback shift register (LFSR) circuit with 36 stages. The
feedback connections correspond to a irreducible polynomial h(n) of
degree 36. The polynomial h(x) chosen by the inventor for the
exemplary embodiment of the present invention is
h(x)=x.sup.36+x.sup.35+x.sup.30+x.sup.28+x.sup.26+x.sup.25+x.sup.22+x.su-
p.20+x.sup.19+x.sup.17+x.sup.16+x.sup.15+x.sup.14+x.sup.12+x.sup.11+x.sup.-
9+x.sup.8+x.sup.4+x.sup.3+x.sup.2+1 (2)
[0052] A group of "seed" values for a LFSR representing the
polynomial h(x) of equation (2) which generates code sequences that
are nearly orthogonal with each other is determined. The first
requirement of the seed values is that the seed values do not
generate two code sequences which are simply cyclic shifts of each
other.
[0053] The present invention includes a method to increase the
number of available seeds for use in a CDMA communication system by
recognizing that certain cyclic shifts of the previously determined
code sequences may be used simultaneously. The round trip delay for
the cell sizes and bandwidths of the present invention are less
than 3000 chips. In one embodiment of the present invention,
sufficiently separated cyclic shifts of a sequence can be used
within the same cell without causing ambiguity for a receiver
attempting to determine the code sequence. This method enlarges the
set of sequences available for use.
[0054] By implementing the tests previously described, a total of
3879 primary seeds were determined by the inventor through
numerical computation. These seeds are given mathematically as
d.sup.nmodulo h(x) (3)
[0055] When all primary seeds are known, all secondary seeds of the
present invention are derived from the primary seeds by shifting
them multiples of 4095 chips modulo h(x). Once a family of seed
values is determined, these values are stored in memory and
assigned to logical channels as necessary. Once assigned, the
initial seed value is simply loaded into LFSR to produce the
required spreading-code sequence associated with the seed
value.
[0056] Epoch and Sub-Epoch Structures
[0057] The long complex spreading codes used for the system of the
current invention have a number of chips after which the code
repeats. The repetition period of the spreading sequence is called
an epoch. To map the logical channels to CDMA spreading codes, the
present invention uses an Epoch and Sub-epoch structure. The code
period for the CDMA spreading code to modulate logical channels is
29877120 chips/code period which is the same number of chips for
all bandwidths. The code period is the epoch of the present
invention, and the Table 2 defines the epoch duration for the
supported chip rates. In addition, two sub-epochs are defined over
the spreading code epoch and are 233415 chips and 128 chips
long.
[0058] The 233415 chip sub-epoch is referred to as a long
sub-epoch, and is used for synchronizing events on the RF
communication interface such as encryption key switching and
changing from global to assigned codes. The 128 chip short epoch is
defined for use as an additional timing reference. The highest
symbol rate used with a single CDMA code is 64 ksym/sec. There is
always an integer number of chips in a symbol duration for the
supported symbol rates 64, 32, 16, and 8 ksym/s.
TABLE-US-00003 233415 number of 128 chip chip sub- Chip Rate, chips
in a sub-epoch epoch Epoch Bandwidth Complex 64 kbit/sec duration*
duration* duration (MHz) (M chip/sec) symbol (.mu.s) (ms) (sec) 7
5.824 91 21.978 40.078 5.130 10 8.320 130 15.385 28.055 3.591 10.5
8.512 133 15.038 27.422 3.510 14 11.648 182 10.989 20.039 2.565 15
12.480 195 10.256 18.703 2.394 *numbers in these columns are
rounded to 5 digits.
[0059] Cyclic sequences of the prior art are generated using linear
feedback shift register (LFSR) circuits. This method, however, does
not generate sequences of even length. One embodiment of the
spreading code sequence generator using the code seeds generated
previously is shown in FIG. 2a, FIG. 2b, and FIG. 2c. The exemplary
system uses a 36 stage LFSR 201 to generate a sequence of period
N'=233415=3.sup.3.times.5.times.7.times.13.times.19, which is
C.sub.o in FIG. 2a. In the FIGS. 2a, 2b, and 2c the symbol .sym.
represents a binary addition (EXCLUSIVE-OR). A sequence generator
designed as above generates the in-phase and quadrature parts of a
set of complex sequences. The tap connections and initial state of
the 36 stage LFSR determine the sequence generated by this circuit.
The tap coefficients of the 36 stage LFSR are determined such that
the resulting sequences have the period 233415. Note that the tap
connections shown in FIG. 2a correspond to the polynomial given in
equation (2). Each resulting sequence is then overlaid by binary
addition with the 128 length sequence C* to obtain the epoch period
29877120.
[0060] FIG. 2b shows a Feed Forward (FF) circuit 202 which is used
in the code generator. The signal X[n-1] is output of the chip
delay 211, and the input of the chip delay 211 is X[n]. The code
chip C[n] is formed by the logical adder 212 for the input X[n] and
X[n-1]. FIG. 2c shows the complete spreading-code generator. From
the LFSR 201, output signals go through a chain of up to 63 single
stage FFs 203 cascaded as shown. The output of each FF is overlaid
with the short, even code sequence C* which has a period of
128=2.sup.7, the short code sequence C* is stored in code memory
222 and exhibits spectral characteristics of a pseudorandom
sequence to obtain the epoch N=29877120 when combined with the
sequences provided by the FFs 203. This sequence of 128 is
determined by using an m-sequence (PN sequence) of length
127=2.sup.7-1 and adding a bit-value, such as logic 0, to the
sequence to increase the length to 128 chips. The even code
sequence C* is input to the even code shift register 221, which is
a cyclic register, that continually outputs the sequence. The short
sequence is then combined with the long sequence using an
EXCLUSIVE-OR operation 213, 214, 220.
[0061] As shown in FIG. 2c, up to 63 spreading-code sequences
C.sub.o through C.sub.63 are generated by tapping the output
signals of FFs 203 and logically adding the short sequence C* in a
binary adders 213, 214, and 220, for example. One skilled in the
art would realize that the implementation of the FF 203 create a
cumulative delay effect for the code sequences produced at each FF
stage in the chain. This delay is due to the nonzero electrical
delay in the electronic components of the implementation. The
timing problems associated with the delay can be mitigated by
inserting additional delay elements into the FF chain. An exemplary
FF chain with additional delay elements is shown in FIG. 2d.
[0062] The code-generators in the exemplary system are configured
to generate either global codes, or assigned codes. Global codes
are CDMA codes that can be received or transmitted by all users of
the system. Assigned codes are CDMA codes that are allocated for a
particular connection. When a family of sequences is generated from
the same generator as described, only the seed of the 36 stage LFSR
is specified. Sequences for all the global codes, are generated
using the same LFSR circuit. Therefore, once an SU has synchronized
to the Global pilot signal from an RCS and knows the seed for the
LFSR circuit for the Global Channel codes, it can generate not only
the pilot sequence but also all other global codes used by the
RCS.
[0063] The signal that is upconverted to RF is generated as
follows. The spreading sequences produced by the above shift
register circuits are converted to an antipodal sequence (0 maps
into +1, 1 maps into -1). The Logical channels are initially
converted to APSK signals, which are mapped as constellation points
as is well known in the art. The In-phase and Quadrature channels
of each QPSK signal form the real and imaginary parts of the
complex data value. Similarly, two spreading codes are used to form
complex spreading chip values. The complex data and complex
spreading code are multiplied to produce a spread-spectrum data
signal. Similarly, for despreading, the received complex data is
correlated with the conjugate of the complex spreading code to
recover the data signal.
[0064] Short Codes
[0065] Short codes are used for the initial ramp-up process when an
SU accesses an RCS. The period of the short codes is equal to the
symbol duration and the start of each period is aligned with a
symbol boundary. Both the SUs and the RCS derive the real and
imaginary parts of the short codes from the last eight feed-forward
sections of the sequence generator to produce the global codes for
that cell. Details on the implementation of the initial ramp-up
process may be found in a U.S. patent application entitled "A
METHOD OF CONTROLLING INITIAL POWER RAMP-UP IN CDMA SYSTEMS BY
USING SHORT CODES", filed on even date herewith which is
incorporated herein by reference.
[0066] The signals represented by these short codes are known as
Short Access Channel pilots (SAXPTs).
[0067] Mapping of Logical Channels to Spreading Codes
[0068] The exact relationship between the spreading-code sequences
and the CDMA logical channels and pilot signals is documented in
Table 3a and Table 3b. Those signal names ending in `- - - CH`
correspond to logical channels. Those signal names ending in `- - -
PT` correspond to pilot signals, which are described in detail
below.
TABLE-US-00004 TABLE 3a Spreading code sequences and global CDMA
codes Logical Channel Sequence Quadrature or Pilot Signal Direction
C.sub.0 I FBCH Forward (F) C.sub.1 Q FBCH F C.sub.2.sym.C* I GLPT F
C.sub.3.sym.C* Q GLPT F C.sub.4.sym.C* I SBCH F C.sub.5.sym.C* Q
SBCH F C.sub.6.sym.C* I CTCH (0) F C.sub.7.sym.C* Q CTCH (0) F
C.sub.8.sym.C* I APCH (1) F C.sub.9.sym.C* Q APCH (1) F
C.sub.10.sym.C* I CTCH (1) F C.sub.11.sym.C* Q CTCH (1) F
C.sub.12.sym.C* I APCH (1) F C.sub.13.sym.C* Q APCH (1) F
C.sub.14.sym.C* I CTCH (2) F C.sub.15.sym.C* Q CTCH (2) F
C.sub.16.sym.C* I APCH (2) F C.sub.17.sym.C* Q APCH (2) F
C.sub.18.sym.C* I CTCH (3) F C.sub.19.sym.C* Q CTCH (3) F
C.sub.20.sym.C* I APCH (3) F C.sub.21.sym.C* Q APCH (3) F
C.sub.22.sym.C* I reserved -- C.sub.23.sym.C* Q reserved -- . . . .
. . . . . . . . . . . . . . . . . . . . C.sub.40.sym.C* I reserved
-- C.sub.41.sym.C* Q reserved -- C.sub.42.sym.C* I AXCH (3) Reverse
(R) C.sub.43.sym.C* Q AXCH (3) R C.sub.44.sym.C* I LAXPT (3) R
SAXPT (3) seed C.sub.45.sym.C* Q LAXPT (3) R SAXPT (3) seed
C.sub.46.sym.C* I AXCH (2) R C.sub.47.sym.C* Q AXCH (2) R
C.sub.48.sym.C* I LAXPT (2) R SAXPT (2) seed C.sub.49.sym.C* Q
LAXPT (2) R SAXPT (2) seed C.sub.50.sym.C* I AXCH (1) R
C.sub.51.sym.C* Q AXCH (1) R C.sub.52.sym.C* I LAXPT (1) R SAXPT
(1) seed C.sub.53.sym.C* Q LAXPT (1) R SAXPT (1) seed
C.sub.54.sym.C* I AXCH (0) R C.sub.55.sym.C* Q AXCH (0) R
C.sub.56.sym.C* I LAXPT (0) R SAXPT (0) seed C.sub.57.sym.C* Q
LAXPT (0) R SAXPT (0) seed C.sub.58.sym.C* I IDLE --
C.sub.59.sym.C* Q IDLE -- C.sub.60.sym.C* I AUX R C.sub.61.sym.C* Q
AUX R C.sub.62.sym.C* I reserved -- C.sub.63.sym.C* Q reserved
--
TABLE-US-00005 TABLE 3b Spreading code sequences and assigned CDMA
codes Logical Channel Sequence Quadrature or Pilot Signal Direction
C.sub.0.sym.C* I ASPT Reverse (R) C.sub.1.sym.C* Q ASPT R
C.sub.2.sym.C* I APCH R C.sub.3.sym.C* Q APCH R C.sub.4.sym.C* I
OWCH R C.sub.5.sym.C* Q OWCH R C.sub.6.sym.C* I TRCH (0) R
C.sub.7.sym.C* Q TRCH (0) R C.sub.8.sym.C* I TRCH (1) R
C.sub.9.sym.C* Q TRCH (1) R C.sub.10.sym.C* I TRCH (2) R
C.sub.11.sym.C* Q TRCH (2) R C.sub.12.sym.C* I TRCH (3) R
C.sub.13.sym.C* Q TRCH (3) R C.sub.14.sym.C* I reserved --
C.sub.15.sym.C* Q reserved -- . . . . . . . . . . . . . . . . . . .
. . . . . C.sub.44.sym.C* I reserved -- C.sub.45.sym.C* Q reserved
-- C.sub.46.sym.C* I TRCH (3) Forward (F) C.sub.47.sym.C* Q TRCH
(3) F C.sub.48.sym.C* I TRCH (2) F C.sub.49.sym.C* Q TRCH (2) F
C.sub.50.sym.C* I TRCH (1) F C.sub.51.sym.C* Q TRCH (1) F
C.sub.52.sym.C* I TRCH (0) F C.sub.53.sym.C* Q TRCH (0) F
C.sub.54.sym.C* I OWCH F C.sub.55.sym.C* Q OWCH F C.sub.56.sym.C* I
APCH F C.sub.57.sym.C* Q APCH F C.sub.58.sym.C* I IDLE --
C.sub.59.sym.C* Q IDLE -- C.sub.60.sym.C* I reserved --
C.sub.61.sym.C* Q reserved -- C.sub.62.sym.C* I reserved --
C.sub.63.sym.C* Q reserved --
[0069] Pilot Signals
[0070] As described above, the pilot signals are used for
synchronization, carrier phase recovery, and for estimating the
impulse response of the radio channel. The RCS 104 transmits a
forward link pilot carrier reference as a complex pilot code
sequence to provide a time and phase reference for all SUs 111,
112, 115, 117 and 118 in its service area. The power level of the
Global Pilot (GLPT) signal is set to provide adequate coverage over
the whole RCS service area, which area depends on the cell size.
With only one pilot signal in the forward link, the reduction in
system capacity due to the pilot energy is negligible.
[0071] Each of the SUs 111, 112, 115, 117 and 118 transmits a pilot
carrier reference as a quadrature modulated (complex-valued) pilot
spreading-code sequence to provide time and phase reference to the
RCS for the reverse link. The pilot signal transmitted by the SU of
one embodiment of the invention is 6 dB lower than the power of the
32 kbit/s POTS (plain old telephone service) traffic channel. The
reverse pilot channel is subject to APC. The reverse link pilot
associated with a particular connection is called the Assigned
Pilot (ASPT). In addition, there are pilot signals associated with
access channels, and these are called the Long Access Channel
Pilots (LAXPTs). Short access channel pilots (SAXPTs) are also
associated with the access channels and used for spreading-code
acquisition and initial power ramp-up.
[0072] All pilot signals are formed from complex codes, as defined
below:
GLPT (forward)={C.sub.2.sym.C*j.(C.sub.3.sym.C*}{(.+-.1)+j.(0)}
{Complex Code}{Carrier}
[0073] The complex pilot signals are de-spread by multiplication
with conjugate spreading codes:
{(C.sub.2.sym.C*)-j.(C.sub.3.sym.C*)}. By contrast, traffic
channels are of the form:
TRCH.sub.n(forward/reverse)={(C.sub.k.sym.C*)+j.(C.sub.1.sym.C*)}{(.+-.1-
)+j(.+-.1)}
{Complex Codes}{Data Symbol}
which thus form a constellation set at .pi./4 radians with respect
to the pilot signal constellations.
[0074] The GLPT constellation is shown in FIG. 3a, and the
TRCH.sub.n traffic channel constellation is shown in FIG. 3b.
[0075] Logical Channel Assignment of the FBCH, SBCH, and Traffic
Channels
[0076] The fast broadcast channel (FBCH) is a global forward link
channel used to broadcast dynamic information about the
availability of services and access channels (AXCHs). The messages
are sent continuously, and each message lasts approximately 1 ms.
The FBCH message is 16 bits long, repeated continuously, and epoch
aligned. The FBCH is formatted as defined in Table 4.
TABLE-US-00006 TABLE 4 FBCH format Bit Definition 0 Traffic Light 0
1 Traffic Light 1 2 Traffic Light 2 3 Traffic Light 3 4-7 service
indicator bits 8 Traffic Light 0 9 Traffic Light 1 10 Traffic Light
2 11 Traffic Light 3 12-15 service indicator bits
[0077] For the FBCH, bit 0 is transmitted first. A traffic light
corresponds to an Access Channel (AXCH) and indicates whether the
particular access channel is currently in use (red) or not in use
(green). A logic "1" indicates that the traffic light is green, and
a logic "0" indicates the traffic light is red. The values of the
traffic light bits may change from octet to octet, and each 16 bit
message contains distinct service indicator bits which describe
which types of service are available for the AXCHs.
[0078] One embodiment of the present invention uses service
indicator bits as follows to indicate the availability of services
or AXCHs. The service indicator bits {4,5,6,7,12,13,14,15} are
interpreted as an unsigned binary number, with bit 4 as the MSB and
bit 15 as the LSB. Each service type increment has an associated
nominal measure of the capacity required, and the FBCH continuously
broadcasts the available capacity. This is scaled to have a maximum
value equivalent to the largest single service increment possible.
When an SU requires a new service or an increase in the number of
bearers), it compares the capacity required to that indicated by
the FBCH, and then considers itself blocked if the capacity is not
available. The FBCH and the traffic channels are aligned to the
epoch.
[0079] Slow Broadcast Information frames contain system or other
general information that is available to all SUs, and Paging
Information frames contain information about call requests for
particular SUs. Slow Broadcast Information frames and Paging
Information frames are multiplexed together on a single logical
channel which forms the Slot Broadcast Channel (SBCH). As
previously defined, the code epoch is a sequence of 29 877 20 chips
having an epoch duration which is a function of the chip rate
defined in Table 5 below. In order to facilitate power saving, the
channel is divided into N "Sleep" Cycles, and each Cycle is
subdivided into M Slots, which are 19 ms long, except for 10.5 Mhz
bandwidth which has slots of 18 ms.
TABLE-US-00007 TABLE 5 SBCH Channel Format Outline Spreading Epoch
Cycle Slots/ Slot Bandwidth Code Rate Length Cycles/ Length Cycle
Length (MHz) (MHz) (ms) Epoch N (ms) M (ms) 7.0 5.824 5130 5 1026
54 19 10.0 8.320 3591 3 1197 63 19 10.5 8.512 3510 3 1170 65 18
14.0 11.648 2565 3 855 45 19 15.0 12.480 2394 2 1197 63 19
[0080] Sleep Cycle Slot #1 is always used for slow broadcast
information. Slots #2 to #M-1 are used for paging groups unless
extended slow broadcast information is inserted. The pattern of
cycles and slots in one embodiment of the present invention run
continuously at 16 kbit/s.
[0081] Within each Sleep Cycle the SU may power-up the receiver and
re-acquire pilot code to achieve carrier lock to a sufficient
precision for satisfactory demodulation and Viterbi decoding. This
settling time may be up to 3 Slots in duration. For example, an SU
assigned to Slot #7 may power up the Receiver at the start of Slot
#4. Having monitored its Slot the SU either recognizes its Paging
Address and initiates an access request, or fails to recognize its
Paging Address in which case it reverts to the Sleep mode.
[0082] Spreading Code Tracking and AMF Detection in Multipath
Channels
[0083] Spreading Code Tracking
[0084] Three CDMA spreading-code tracking methods in multipath
fading environments are described which track the code phase of a
received multipath spread-spectrum signal. The first method uses
the prior art tracking circuit which simply tracks the spreading
code phase of the detector having the highest output signal value,
the second method uses a tracking circuit that tracks the median
value of the code phase of the group of multipath signals, and the
third method of the present invention, is the centroid tracking
circuit which tracks the code-phase of an optimized, least mean
squared weighted average of the multipath signal components. The
following describes the algorithms by which the spreading code
phase of the received CDMA signal is tracked.
[0085] A tracking circuit has operating characteristics that reveal
the relationship between the time error and the control voltage
that drives a Voltage Controlled Oscillator (VCO) of a
spreading-code phase tracking circuit. When there is a positive
timing error, the exemplary tracking circuit generates a negative
control voltage to offset the timing error. When there is a
negative timing error, the exemplary tracking circuit generates a
positive control voltage to offset the timing error. When the
tracking circuit generates a zero value, this value corresponds to
the perfect time alignment called the `lock-point`. FIG. 3c shows
the basic tracking circuit. Received signal r(t) is applied to
matched filter 301, which correlates r(t) with a local
code-sequence c(t) generated by Code Generator 303. The output
signal of the matched filter x(t) is sampled at the sampler 302 to
produce samples x[nT] and x[nT+T/2]. The samples x[nT] and
x[nT+T/2] are used by a tracking circuit 304 to determine if the
phase of the spreading-code c(t) of the code generator 303 is
correct. The tracking circuit 304 produces an error signal e(t) as
an input to the code generator 303. The code generator 303 uses
this signal e(t) as an input signal to adjust the code-phase it
generates.
[0086] In a CDMA system, the signal transmitted by the reference
user is written in the low-pass representation as
s ( t ) = k = - .infin. .infin. c k P Tc ( t - kT c ) ( 4 )
##EQU00001##
where c.sub.k represents the spreading code coefficients,
P.sub.Tc(t) represents the spreading code chip waveform, and
T.sub.c is the chip duration. Assuming that the reference user is
not transmitting data, only the spreading code modulates the
carrier. Referring to FIG. 3, the received signal is
r ( t ) = i = 1 M a i s ( t - .tau. i ) ( 5 ) ##EQU00002##
[0087] Here, a.sub.i is due to fading effect of the multipath
channel on the i-th path and .tau..sub.i is the random time delay
associated with the same path. The receiver passes the received
signal through a matched filter, which is implemented as a
correlation receiver and is described below. This operation is done
in two steps: first the signal is passed through a chip matched
filter and sampled to recover the spreading code chip values, then
this chip sequence is correlated with the locally generated code
sequence.
[0088] FIG. 3c shows the chip matched filter 301, matched to the
chip waveform P.sub.Tc(t), and the sampler 302. The signal x(t) at
the output terminal of the chip matched filter is
x ( t ) = i = k M k = - .infin. .infin. a i c k g ( t - .tau. i -
kT c ) ( 6 ) where g ( t ) = P Tc ( t ) * h R ( t ) ( 7 )
##EQU00003##
[0089] Here, h.sub.R(t) is the impulse response of the chip matched
filter and "*" denotes convolution. The order of the summations,
can be rewritten as:
x ( t ) = k = - .infin. .infin. c k f ( t - kT c ) ( 8 ) where f (
t ) = t = 1 M a 1 g ( t - .tau. 1 ) ( 9 ) ##EQU00004##
[0090] In the multipath channel described above, the sampler
samples the output signal of the matched filter to produce x(nT) at
the maximum power level points of g(t). In practice, however, the
waveform g(t) is often severely distorted because of the effect of
the multipath signal reception, and a perfect time alignment of the
signals is not available.
[0091] When the multipath in the channel is negligible and a
perfect estimate of the timing is available, i.e., a.sub.1=1,
.tau..sub.1=0, and a.sub.1=0,i=2, . . . , M, the received signal is
r(t)=s(t). Then, with this ideal channel model, the output of the
chip matched filter becomes
x ( t ) = k = - .infin. .infin. c k g ( t - kT c ) ( 10 )
##EQU00005##
[0092] When there is multipath fading, however, the received
spreading code chip value waveform is distorted, and a number of
local maxima that can change from one sampling interval to another
depending on the channel characteristics.
[0093] For multipath fading channels with quickly changing channel
characteristics, it is not practical to try to locate the maximum
of the waveform f(t) in every chip period interval. Instead, a time
reference can be obtained from the characteristics of f(t)that may
not change as quickly. Three tracking methods are described based
on different characteristics of f(t).
[0094] Prior Art Spreading-Code Tracking Method:
[0095] Prior art tracking methods include a code tracking circuit
in which the receiver attempts to determine where the maximum
matched filter output value of the chip waveform occurs and sample
the signal at that point. In multipath fading channels, however,
the receiver despreading code waveform can have a number of local
maxima, especially in a mobile environment. If f(t) represents the
received signal waveform of the spreading code chip convolved with
the channel impulse response, the shape of f(t) and where its
maximum occurs can change rather quickly making it impractical to
track the maximum of f(t).
[0096] Define .tau. to be the time estimate that the tracking
circuit calculates during a particular sampling interval. Also,
define the following error function
= { .intg. f ( t ) t , { t : .tau. - .upsilon. 8 } .tau. - t >
.delta. = 0 .tau. - t < .delta. ( 11 ) ##EQU00006##
The tracking circuits of the prior art calculate a value of the
input signal that minimizes the error .epsilon.. One can write
min = 1 - max .tau. .intg. .tau. - .delta. .tau. + .delta. f ( t )
t ( 12 ) ##EQU00007##
[0097] Assuming has a smooth shape in the values given, the value
of .tau. for which f(.tau.) is maximum minimizes the error
.epsilon., so the tracking circuit tracks the maximum point of
f(.tau.).
[0098] Median Weighted Value Tracking Method:
[0099] The Median Weighted Tracking Method of one embodiment of the
present invention, minimizes the absolute weighted error, defined
as
.epsilon.=.intg..sub.-.infin..sup..infin.|t-.tau.|f(t)dt (13)
[0100] This tracking method calculates the `median` signal value of
f(t) by collecting information from all paths, where f(.tau.) is as
in equation (9). In a multipath fading environment, the waveform
f(t) can have multiple local maxima, but only one median.
[0101] To minimize .epsilon., the derivative of equation (13) is
taken with respect to .tau. and equated it to zero, which gives
.intg..sub.-.infin..sup..tau.f(t)dt=.intg..sub..tau..sup..infin.f(t)dt
(14)
[0102] The value of .tau. that satisfies (14) is called the
"median" of f(.tau.). Therefore, the Median Tracking Method of the
present embodiment tracks the median of f(t). FIG. 4 shows an
implementation of the tracking circuit based on minimizing the
absolute weighted error defined above. The signal x(t) and its
one-half chip offset version x(t+T/2) are sampled by the
analog-to-digital A/D converter 401 at a rate 1/T. The following
equation determines the operating characteristic of the circuit in
FIG. 4:
( .tau. ) = n = 1 2 L f ( .tau. - nT / 2 - f ( .tau. + nT / 2 ) (
15 ) ##EQU00008##
[0103] Tracking the median of a group of multipath signals keeps
the received energy of the multipath signal components equal on the
early and late sides of the median point of the correct locally
generated spreading-code phase c.sub.n. The tracking circuit
consists of an A/D converter 401 which samples an input signal x(t)
to form the half chip offset samples. The half chip offset samples
are alternatively grouped into even samples called an early set of
samples x(nT+.tau.) and odd samples called a late set of samples
x(nT+(T/2)+.tau.). The first correlation bank adaptive matched
filter 402 multiples each early sample by the spreading-code phases
c(n+1), c(n+2), . . . , c(n+L), where L is small compared to the
code length and approximately equal to number of chips of delay
between the earliest and latest multipath signal. The output of
each correlator is applied to a respective first sum-and-dump bank
404. The magnitudes of the output values of the L sum-and-dumps are
calculated in the calculator 406 and then summed in a summer 408 to
give an output value proportional to the signal energy in the early
multipath signals. Similarly, a second correlation bank adaptive
matched filter 403 operates on the late samples, using code phases
c(n-1), c(n-2), . . . , c(n-L), and each output signal is applied
to a respective sum-and-dump in an integrator 405. The magnitudes
of the L sum-and-dump outputs are calculated in calculator 407 and
then summed in summer 409 to give a value for the late multipath
signal energy. Finally, the subtractor 410 calculates the
difference and produces error signal .epsilon.(t) of the early and
late signal energy values.
[0104] The tracking circuit adjusts, by means of error signal
.epsilon.(.tau.), the locally generated code phases c(t) to cause
the difference between the early and late values to tend toward
0.
[0105] Centroid Tracking Method
[0106] Another spreading-code tracking circuit of one embodiment of
the present invention is called the squared weighted tracking (or
centroid) circuit. Defining .tau. to denote the time estimate that
the tracking circuit calculates, based on some characteristic of
f(t), the centroid tracking circuit minimizes the squared weighted
error defined as
.epsilon.=.intg..sub.-.infin..sup..infin.|t-.tau.|.sup.2f(t)dt
(16)
[0107] This function inside the integral has a quadratic form,
which has a unique minimum. The value of .tau. that minimizes
epsilon. can be found by taking the derivative of the above
equation with respect to .quadrature. and equating to zero, which
gives
.intg..sub.-.infin..sup..infin.(-2t+2.tau.)f(t)dt=0 (17)
[0108] Therefore, the value of .quadrature. that satisfies
.tau. - 1 .beta. .intg. - .infin. .infin. tf ( t ) t = 0 ( 18 )
##EQU00009##
is the timing estimate that the tracking circuit calculates, and
.quadrature. is a constant value.
[0109] Based on these observations, a realization of the tracking
circuit minimizing the squared weighted error is shown in FIG. 5.
The following equation determines the error signal .epsilon.(.tau.)
of the centroid tracking circuit:
( .tau. ) = n = 1 2 L n [ f ( .tau. - nT / 2 ) - f ( .tau. + nT / 2
) ] = 0 ( 19 ) ##EQU00010##
[0110] The value that satisfies=0 is the optimized estimate of the
timing.
[0111] The early and late multipath signal energy on each side of
the centroid point are equal. The centroid tracking circuit shown
in FIG. 5 consists of an A/D converter 501 which samples an input
signal x(t), as described above with reference to FIG. 4 to form
half chip offset samples. The half chip offset samples are
alternatively grouped as an early set of samples x(nT+.tau.) and a
late set of samples x(nT+(T/2)+.tau.). The first correlation bank
adaptive matched filter 502 multiples each early sample and each
late sample by the positive spreading-code phases c(n-1),
c(n.sub.+2), . . . , c(n.sub.+L), where L is small compared to the
code length and is approximately equal to number of chips of delay
between the earliest and latest multipath signal. The output signal
of each correlator is applied to a respective one of L sum-and-sump
circuits of the first sum and dump bank 504. The magnitude value of
the output signal produced by each sum-and-dump circuit of the sum
and dump bank 504 is calculated by the respective calculator in the
calculator bank 506 and applied to a corresponding weighting
amplifier of the first weighting bank 508. The output signal of
each weighting amplifier represents the weighted signal energy in a
multipath component signal.
[0112] The weighted early multipath signal energy values are summed
in sample adder 510 to give an output value that is proportional to
the signal energy in the group of multipath signals corresponding
to positive code phases which are the early multipath signals.
Similarly, a second correlation bank adaptive matched filter 503
operates on the early and late samples, using the negative
spreading-code phases c(n-1), c(n-2), . . . , c(n-L), each output
signal is provided to a respective sum-and-dump circuit of discrete
integrator 505. The magnitude value of the L sum-and-dump output
signals are calculated by the respective calculator of calculator
bank 507 and then weighted in weighting bank 509. The weighted late
multipath signal energy values are summed in sample adder 511 to
give an energy value for the group of multipath signal
corresponding to the negative code phases which are the late
multipath signals. Finally, the subtractor 512 calculates the
difference of the early and late signal energy values to produce
error sample value. .epsilon.(.tau.)
[0113] The tracking circuit of FIG. 5 produces error signal
.epsilon.(.tau.) which is used to adjust the locally generated code
phase c(nT) to keep the weighted average energy in the early and
late multipath signal groups equal. The embodiment shown uses
weighting values that increase as the distance from the centroid
increases. The signal energy in the earliest and latest multipath
signals is probably less than the multipath signal values near the
centroid. Consequently, the difference calculated by the subtractor
512 is more sensitive to variations in delay of the earliest and
latest multipath signals.
[0114] Quadratic Detector for Tracking
[0115] In another exemplary tracking method, the tracking circuit
adjusts sampling phase to be "optimal" and robust to multipath. If
f(t) represent the received signal waveform as in equation (9)
above. The particular method of optimizing starts with a delay
locked loop with an error signal .epsilon.(.tau.) that drives the
loop. The function .epsilon.(.tau.) desirably has only one zero at
.tau.=.tau..sub.o where .tau..sub.o is optimal. The optimal form
for .epsilon.(.tau.) has the canonical form:
( .tau. ) = .intg. - .infin. .infin. w ( t , .tau. ) f ( t ) 2 t (
20 ) ##EQU00011##
[0116] where w(t,.tau.) is a weighting function relating f(t) to
the error .epsilon.(.tau.), and the following holds
( .tau. + .tau. 0 ) = .intg. - .infin. .infin. w ( t , .tau. +
.tau. 0 ) f ( t ) 2 t ( 21 ) ##EQU00012##
[0117] It follows from equation (21) that w(t, .quadrature.) is
equivalent to w(t-.quadrature.). Considering the slope M of the
error signal in the neighborhood of a lock point:
M = ( .tau. ) .tau. .tau. 0 = - .intg. - .infin. .infin. w ' ( t -
.tau. 0 ) g ( t ) t ( 22 ) ##EQU00013##
[0118] where w' (t, .quadrature.) is the derivative of w(t,
.quadrature.) with respect to .quadrature., and g(t) is the average
of |f(t)|.sup.2.
[0119] The error .epsilon.(.tau.) has a deterministic part and a
noise part. Let z denote the noise component in .epsilon.(.tau.),
then |z|.sup.2 is the average noise power in the error function
.epsilon.(.tau.). Consequently, the optimal tracking circuit
maximizes the ratio:
F = M 2 z 2 ( 23 ) ##EQU00014##
[0120] The implementation of the Quadratic Detector is now
described. The discrete error value e of an error signal
.epsilon.(.tau.)is generated by performing the operation
e=y.sup.TBy (24)
[0121] where the vector y represents the received signal components
yi, i=0, 1, . . . , L-1, as shown in FIG. 5b. The matrix B is an L
by L matrix and the elements are determined by calculating values
such that the ratio F of equation 23 is maximized.
[0122] Determining the Minimum Value of L Needed:
[0123] The value of L in the previous section determines the
minimum number of correlators and sum-and-dump elements. L is
chosen as small as possible without compromising the functionality
of the tracking circuit.
[0124] The multipath characteristic of the channel is such that the
received chip waveform f(t) is spread over QT.sub.c seconds, or the
multipath components occupy a time period of Q chips duration. The
value of L chosen is L=Q. Q is found by measuring the particular RF
channel transmission characteristics to determine the earliest and
latest multipath component signal propagation delay, QT.sub.c is
the difference between the earliest and latest multipath component
arrival time at a receiver.
[0125] The Quadratic Detector described above may be used to
implement the centroid tracking system described above with
reference to FIG. 5a. For this implementation, the vector y is the
output signal of the sum and dump circuits 504:
y={f(.quadrature.-LT), f(.quadrature.-LT+T/2),
f(.quadrature.-(L-1)T), . . . f(.quadrature.), f(.quadrature.+T/2),
f(.quadrature.+T), . . . f(.quadrature.+LT)} and the matrix B is
set forth in table 6.
TABLE-US-00008 TABLE 6 B matrix for quadratic form of Centroid
Tracking System L 0 0 0 0 0 0 0 0 0 0 0 L - 1/2 0 0 0 0 0 0 0 0 0 0
0 L - 1 0 0 0 0 0 0 0 0 0 0 0 0 1/2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 -1/2 0 0 0 0 0 0 0 0 0 0 0 0 -L + 1 0 0 0 0 0 0 0 0 0
0 0 -L + 1/2 0 0 0 0 0 0 0 0 0 0 0 -L
[0126] Adaptive Vector Correlator
[0127] An embodiment of the present invention uses an adaptive
vector correlator (AVC) to estimate the channel impulse response
and to obtain a reference value for coherent combining of received
multipath signal components. The described embodiment employs an
array of correlators to estimate the complex channel response
affecting each multipath component, then the receiver compensates
for the channel response and coherently combines the received
multipath signal components. This approach is referred to as
maximal ratio combining.
[0128] Referring to FIG. 6, The input signal x(t) to the system is
composed of interference noise of other message channels, multipath
signals of message channels, thermal noise, and multipath signals
of the pilot signal. The signal is provided to AVC 601 and which
includes a despreading means 602, channel estimation means for
estimating the channel response 604, correction means for
correcting a signal for effects of the channel response 603, and
adder 605 in the present invention. The AVC despreading means 602
is composed of multiple code correlators, with each correlator
using a different phase of the pilot code c(t) provided by the
pilot code generator 608. The output of this despreading means
corresponding to a noise power level if the phase of the local
pilot code of the despreading means is not in phase with the input
code signal, or it corresponds to a received pilot signal power
level plus noise power level if the input pilot code and locally
generated pilot code phases are the same. The output signals of the
correlators of the despreading means corrected for the channel
response by the correction means 603 and are applied to the adder
605 which collects all multipath pilot signal power. The channel
response estimation means 604 receives the combined pilot signal
and the output signals of the despreading means 602, and provides a
channel response estimate signal, w(t), to the correction means 603
of the AVC, and the estimate signal w(t) is also available to the
adaptive matched filter (AMF) described subsequently. The output
signal of the despreading means 602 is also provided to the
acquisition decision means 606 which decides, based on a particular
algorithm, such as a sequential probability ratio test (SPRT), if
the present output levels of the despreading circuits correspond to
synchronization of the locally generated code to the desired input
code phase. If the detector finds no synchronization, then the
acquisition decision means sends a control signal a(t) to the local
pilot code generator 608 to offset its phase by one or more chip
periods. When synchronization is found, the acquisition decision
means informs the tracking circuit 607, which achieves and
maintains a close synchronization between the received and locally
generated code sequences.
[0129] An exemplary implementation of the Pilot AVC used to
despread the pilot spreading-code is shown in FIG. 7. The described
embodiment assumes that the input signal x(t) has been sampled with
sampling period T to form x(nT+.tau.), and is composed of
interference noise of other message channels, multipath signals of
message channels, thermal noise, and multipath signals of the pilot
code. The signal x(nT+.tau.) is applied to L correlators, where L
is the number of code phases over which the uncertainty within the
multipath signals exists. Each correlator 701, 702, 703 comprises a
respective multiplier 704, 705, 706, which multiplies the input
signal with a particular phase of the Pilot spreading code signal
c((n+i)T), and a sum-and-dump circuit 708, 709, 710. The output
signal of each multiplier 704, 705, 706 is applied to a respective
sum-and-dump circuit 708, 709, 710 to perform discrete integration.
Before summing the signal energy contained in the outputs of the
correlators, the AVC compensates for the channel response the
carrier phase rotation of the different multipath signals. Each
output signal of each sum-and-dump 708, 709, 710 is multiplied by a
derotation phasor [complex conjugate of ep(nT)] obtained from the
digital phase lock loop (DPLL) 721. This phasor is applied to one
input port of a respective multiplier 714, 715, 716 to account for
the phase and frequency offset of the carrier signal. The Pilot
Rake AMF calculates, complex weighting factors, wk, k=1, . . . , L,
for each multipath signal by passing the output of each multiplier
714, 715, 716 through a low pass filter (LPF) 711, 712, 713. Each
despread multipath signal is multiplied by its corresponding
weighting factor in a respective multiplier 717, 718, 719. The
output signals of the multipliers 717, 718, 719 are summed in a
master adder 720, and the output signal p(nT) of the accumulator
720 consists of the combined despread multipath pilot signals in
noise. The output signal p(nT) is also applied to the DPLL 721 to
produce the error signal ep(nT) for tracking of the carrier
phase.
[0130] FIGS. 8a and 8b show alternate embodiments of the AVC which
can be used for detection and multipath signal component combining.
The message signal AVCs of FIGS. 8a and 8b use the weighting
factors produced by the Pilot AVC to correct the message data
multipath signals. The spreading code signal, c(nT) is the
spreading sequence used by a particular message channel and is
synchronous with the pilot spreading code signal. The value L is
the number of correlators in the AVC circuit.
[0131] The circuit of FIG. 8a calculates the decision variable Z
which is given by
Z = w 1 i = 1 N x ( iT + .tau. ) c ( iT ) + w 2 i = 1 N x ( iT +
.tau. ) c ( ( i + 1 ) T ) + + w L i + 1 L x ( iT + .tau. ) + c ( (
i + L ) T ) ( 25 ) ##EQU00015##
[0132] where N is the number of chips in the correlation window.
Equivalently, the decision statistic is given by
Z = x ( T + .tau. ) i = 1 L w 1 c ( iT ) + x ( 2 T + .tau. ) i = 1
L w 2 c ( ( i + 1 ) T ) + + x ( NT + .tau. ) i = 1 L w N c ( ( i +
N ) T ) = k = 1 N x ( kT_.tau. ) i = 1 L w k c ( ( i + k - 1 ) T )
( 26 ) ##EQU00016##
[0133] The alternative implementation that results from equation
(26) is shown in FIG. 8b.
[0134] Referring to FIG. 8a, the input signal x(t) is sampled to
form x(nT+.tau.), and is composed of interference noise of other
message channels, multipath signals of message channels, thermal
noise, and multipath signals of the pilot code. The signal
x(nT+.tau.) is applied to L correlators, where L is the number of
code phases over which the uncertainty within the multipath signals
exists. Each correlator 801, 802, 803 comprises a multiplier 804,
805, 806, which multiplies the input signal by a particular phase
of the message channel spreading code signal, and a respective
sum-and-sump circuit 808, 809, 810. The output of each multiplier
804, 805, 806 is applied to a respective sum-and dump circuit 808,
809, 810 which performs discrete integration. Before summing the
signal energy contained in the output signals of the correlators,
the AVC compensates for the different multipath signals. Each
despread multipath signal and its corresponding weighting factor,
which is obtained from the corresponding multipath weighting factor
of the pilot AVC, are multiplied by multiplier 817, 818, 819. The
output signals of the multiplier 817, 818, 819. The output signals
of the multipliers 817, 818, 819 are summed in a master adder 820,
and the output signal z(nT) of the accumulator 820 consists of
sampled levels of a despread message signal in noise.
[0135] The alternative embodiment of the invention includes a new
implementation of the AVC despreading circuit for the message
channels which performs the sum-and-dump for each multipath signal
component simultaneously. The advantage of this circuit is that
only one sum-and dump circuit and one adder is necessary. Referring
to FIG. 8b, the message code sequence generator 830 provides a
message code sequence to shift register 831 of length L. The output
signal of each register 832, 833, 834, 835 of the shift register
831 corresponds to the message code sequence shifted in phase by
one chip. The output value of each register 832, 833, 834, 835 is
multiplied in multipliers 836, 837, 838, 839 with the corresponding
weighting factor wk, k=1, . . . L obtained from the Pilot AVC. The
output signals of the L multipliers 836, 837, 838, 839 are summed
by the adding circuit 840. The adding circuit output signal and the
receiver input signal x(nT+.tau.) are then multiplied in the
multiplier 841 and integrated by the sum-and-dump circuit 842 to
produce message signal z(nT).
[0136] A third embodiment of the adaptive vector correlator is
shown in FIG. 8c. This embodiment uses the least mean square (LMS)
statistic to implement the vector correlator and determines the
derotation factors for each multipath component from the received
multipath signal. The AVC of FIG. 8c is similar to the exemplary
implementation of the Pilot AVC used to despread the pilot
spreading-code shown in FIG. 7. The digital phase locked loop 721
is replaced by a phase locked loop 850 having a voltage controlled
oscillator 851, loop filter 852, limiter 853, and imaginary
component separator 854. The difference between the corrected
despread output signal dos and an ideal despread output is provided
by adder 855, and the difference signal is a despread error value
ide which is further used by the derotation circuits to compensate
for errors in the derotation factors.
[0137] In a multipath signal environment, the signal energy of a
transmitted symbol is spread out over the multipath signal
components. The advantage of multipath signal addition is that a
substantial portion of signal energy is recovered in an output
signal from the AVC. Consequently, a detection circuit has an input
signal from the AVC with a higher sign-to-noise ratio (SNR), and so
can detect the presence of a symbol with a lower bit-error ration
(BER). In addition, measuring the output of the AVC is a good
indication of the transmit power of the transmitter, and a good
measure of the system's interference noise.
[0138] Adaptive Matched Filter
[0139] One embodiment of the current invention includes an Adaptive
Matched Filter (AMF) to optimally combine the multipath signal
components in a received spread spectrum message signal. The AMF is
a tapped delay line which holds shifted values of the sampled
message signal and combines these after correcting for the channel
response. The correction for the channel response is done using the
channel response estimate calculated in the AVC which operates on
the Pilot sequence signal. The output signal of the AMF is the
combination of the multipath components which are summed to give a
maximum value. This combination corrects for the distortion of
multipath signal reception. The various message despreading
circuits operate on this combined multipath component signal from
the AMF.
[0140] FIG. 8d shows an exemplary embodiment of the AMF. The
sampled signal from the A/D converter 870 is applied to the L-stage
delay line 872. Each stage of this delay line 872 holds the signal
corresponding to a different multipath signal component. Correction
for the channel response is applied to each delayed signal
component by multiplying the component in the respective multiplier
of multiplier bank 874 with the respective weighting factor
w.sub.1, w.sub.2, . . . , w.sub.L, from the AVC corresponding to
the delayed signal component. All weighted signal components are
summed in the adder 876 to give the combined multipath component
signal y(t).
[0141] The combined multipath component signal y(t) does not
include the correction due to phase and frequency offset of the
carrier signal. The correction for the phase and frequency offset
of the carrier signal is made to y(t) by multiplying y(t) with
carrier phase and frequency correction (derotation phasor) in
multiplier 878. The phase and frequency correction is produced by
the AVC as described previously. FIG. 8d shows the correction
before the despreading circuits 880, but alternate embodiments of
the invention can apply the correction after the despreading
circuits.
[0142] The Radio Carrier Station (RCS)
[0143] The Radio Carrier Station (RCS) of the present invention
acts as a central interface between the SU and the remote
processing control network element, such as a Radio Distribution
Unit (RDU). The interface to the RDU of the exemplary system
follows the G.704 standard and an interface according to a modified
version of DECT V5.1, but the present invention may support any
interface that can exchange call control and traffic channels. The
RCS receives information channels from the RDU including call
control data, and traffic channel data such as, but not limited to,
32 kb/s ADPCM, 64 kb/s PCM, and ISDN, as well as system
configuration and maintenance data. The RCS also terminates the
CDMA radio interface bearer channels with SUs, which channels
include both control data, and traffic channel data. In response to
the call control data from either the RDU or a SU, the RCS
allocates traffic channels to bearer channels on the RF
communication link and establishes a communication connection
between the SU and the telephone network through an RDU.
[0144] As shown in FIG. 9, the RCS receives call control and
message information data into the MUXs 905, 906 and 907 through
interface lines 901, 902 and 903. Although E1 format is shown,
other similar telecommunication formats can be supported in the
same manner as described below. Each MUX provides a connection to
the Wireless Access Controller (WAX) 920 through the PCM highway
910. While the exemplary system shown in FIG. 1 uses an E1
Interface, it is contemplated that other types of telephone lines
which convey multiple calls may be used, for example, T1 lines or
lines which interface to a Private Branch Exchange (PBX).
[0145] The Wireless Access Controller (WAC) 920 is the RCS system
controller which manages call control functions and interconnection
of data streams between the MUXs 905, 906, 907 and the Modem
Interface Units (MIUs) 931, 932, 933. The WAC 920 also controls and
monitors other RCS elements such as the VCD 940, RF 950, and Power
Amplifier 960.
[0146] A low speed bus 912 is connected to the WAC 920 for
transferring control and status signals between the RF
Transmitter/Receiver 950, VDC 940, RF 950 and Power Amplifier 960.
The controls signals are sent from the WAC 920 to enable to enable
or disable the RF Transmitters/Receiver 950 or Power amplifier 960,
and the status signals are sent from the RF Transmitters/Receiver
950 or Power amplifier 960 to monitor the presence of a fault
condition.
[0147] The exemplary RCS contains at least one MIU 931, which is
shown in FIG. 10. The MIU of the exemplary embodiment includes six
CDMA modems, but the invention is not limited to this number of
modems. The MIU includes: a System PCM Highway 1201 connected to
each of the CDMA Modems 1210, 1211, 1212, 1215 through a PCM
Interface 1220; a Control Channel Bus 1221 connected to MIU
controller 1230 and each of the CDMA Modems 1210, 1211, 1212, 1213;
an MIU clock signal generator (CLK) 1231; and a modem output
combiner 1232. The MIU provides the RCS with the following
functions: the MIU controller receives CDMA Channel Assignment
Instructions from the WAC and assigns a first modem to a user
information signal which is applied to the line interface of the
MUX and a second modem to receive the CDMA channel from the SU; the
MIU also combines the CDMA Transmit Modem Data for each of the MIU
CDMA modems; multiplexes I and Q transmit message data from the
CDMA modems for transmission to the VDC; receives Analog I and Q
receive message data from the VDC; distributes the I and Q data to
the CDMA modems; transmits and receives digital AGC Data;
distributes the AGC data to the CDMA modems; and sends MIU Board
Status and Maintenance Information to the WAC 920.
[0148] The MIU controller 1230 of the exemplary embodiment of the
present invention contains one communication microprocessor 1240,
such as the MC68360 "QUICC" Processor, and includes a memory 1242
having a Flash Prom memory 1243 and a SRAM memory 1244. Flash Prom
1243 is provided to contain the program code for the
Microprocessors 1240, and the memory 1243 is downloadable and
reprogrammable to support new program versions. SRAM 1244 is
provided to contain the temporary data space needed by the MC68360
Microprocessor 1240 when the MIU controller 1230 reads or writes
data to memory.
[0149] The MIU CLK circuit 1231 provides a timing signal to the MIU
controller 1230, and also provides a timing signal to the COMA
modems. The MIU CLK circuit 1231 receives and is synchronized to
the system clock signal wo(t). The controller clock signal
generator 1213 also receives and synchronizes to the spreading code
clock signal pn(t) which is distributed to the COMA modems 1210,
1211, 1212, 1215 from the MUX.
[0150] The RCS of the present embodiment includes a System Modem
1210 contained on one MIU. The System Modem 1210 includes a
Broadcast spreader (not shown) and a Pilot Generator (not shown).
The Broadcast Modem provides the broadcast information used by the
exemplary system, and the broadcast message data is transferred
from the MIU controller 1230 to the System Modem 1210. The System
Modem also includes four additional modems (not shown) which are
used to transmit the signals CT1 through CT4 and AX1 through AX4.
The System Modem 1210 provides unweighted I and Q Broadcast message
data signals which are applied to the VDC. The VDC adds the
Broadcast message data signal to the MIU CDMA Modem Transmit Data
of all CDMA modems 1210, 1211, 1212, 1215, and the Global Pilot
signal.
[0151] The Pilot Generator (PG) 1250 provides the Global Pilot
signal which is used by the present invention, and the Global Pilot
signal is provided to the CDMA modems 1210, 1211, 1212, 1215 by the
MIU controller 1230. Other embodiments of the present invention,
however, do not require the MIU controller to generate the Global
Pilot signal, but include a Global Pilot signal generated by any
form of CDMA Code Sequence generator. In the described embodiment
of the invention, the unweighted I and Q Global Pilot signal is
also sent to the VDC where it is assigned a weight, and added to
the MIU CDMA Modem transmit data and Broadcast message data
signal.
[0152] System timing in the exemplary RCS is derived from the E1
interface. There are four MUXs in an RCS, three of which (905, 906
and 907) are shown in FIG. 9. Two MUXs are located on each chassis.
One of the two MUXs on each chassis is designated as the master,
and one of the masters is designated as the system master. The MUX
which is the system master derives a 2.048 Mhz PCM clock signal
from the E1 interface using a phase locked loop (not shown). In
turn, the system master MUX divides the 2.048 Mhz PCM clock signal
in frequency by 16 to derive a 128 KHz reference clock signal. The
128 KHz reference clock signal is distributed from the MUX that is
the system master to all the other MUXs. In turn, each MUX
multiplies the 128 KHz reference clock signal in frequency to
synthesize the system clock signal which has a frequency that is
twice the frequency of the PN-clock signal. The MUX also divides
the 128 KHz clock signal in frequency by 16 to generate the 8 KHz
frame synch signal which is distributed to the MIUs. The system
clock signal for the exemplary embodiment has a frequency of 11.648
Mhz for a 7 MHz bandwidth CDMA channel. Each MUX also divides the
system clock signal in frequency by 2 to obtain the PN-clock signal
and further divides the PN-clock signal in frequency by 29 877 120
(the PN sequence length) to generate the PN-synch signal which
indicates the epoch boundaries. The PN-synch signal from the system
master MUX is also distributed to all MUXs to maintain phase
alignment of the internally generated clock signals for each MUX.
The PN-synch signal and the frame synch signal are aligned. The two
MUXs that are designated as the master MUXs for each chassis then
distribute both the system clock signal and the PN-clock signal to
the MIUs and the VDC.
[0153] The PCM Highway Interface 1220 connects the System PCM
Highway 911 to each CDMA Modem 1210, 1211, 1212, 1215. The WAC
controller transmits Modem Control information, including traffic
message control signals for each respective user information
signal, to the MIU controller 1230 through the HSB 970. Each CDMA
Modem 1210, 1211, 1212, 1215 receives a traffic message control
signal, which includes signaling information, from the MIU. Traffic
message control signals also include call control (CC) information
and spreading code and despreading code sequence information.
[0154] The MIU also includes the Transmit Data Combiner 1232 which
adds weighted CDMA modem transmit data including In-phase (I) and
Quadrature (Q) modem transmit data from the CDMA modems 1210, 1211,
1212, 1215 on the MIU. The I modem transmit data is added
separately from the Q modem transmit data. The combined I and Q
modem transmit data output signal of the Transmit Data Combiner
1232 is applied to the I and Q multiplexer 1233 that creates a
single CDMA transmit message channel composed of the I and Q modem
transmit data multiplexed into a digital data stream.
[0155] The Receiver Data Input Circuit (RDI) 1234 receives the
Analog Differential I and Q Data from the Video Distribution
Circuit (VDC) 940 shown in FIG. 9 and distributes Analog
Differential I and Q Data to each of the CDMA Modems 1210, 1211,
1212, 1215 of the MIU. The Automatic Gain Control Distribution
Circuit (AGC) 1235 receives the AGC Data signal from the VDC and
distributes the AGC Data to each of the CDMA Modems of the MIU. The
TRL circuit 1233 receives the Traffic lights information and
similarly distributes the Traffic light data to each of the Modems
1210, 1211, 1212, 1215.
[0156] The CDMA Modem
[0157] The CDMA modem provides for generation of CDMA
spreading-code sequences, synchronization between transmitter and
receiver. It also provides four full duplex channels (TR0, TR1,
TR2, TR3) programmable to 64, 32, 16, and 8 ksym/sec. each,
spreading and transmission at a specific power level. The CDMA
modem measures the received signal strength to allow Automatic
Power Control, it generates and transmits pilot signals, encodes
and decodes using the signal for forward error correction (FEC).
The modem in a subscriber unit (SU) also performs transmitter
spreading-code pulse shaping using an FIR filter. The CDMA modem is
also used by the SU and, in the following discussion, those
features which are used only by the SU are distinctly pointed out.
The operating frequencies of the CDMA modem are given in Table
7.
TABLE-US-00009 TABLE 7 Operating Frequencies Bandwidth Chip Rate
Symbol Rate Gain (MHz) (MHz) (KHz) (Chips/Symbol) 7 5.824 64 91 10
8.320 64 130 10.5 8.512 64 133 14 11.648 64 182 15 12.480 64
195
[0158] Each CDMA modem 1210, 1211, 1212, 1215 of FIG. 10, and as
shown in FIG. 11, is composed of a transmit section 1301 and a
receive section 1302. Also included in the CDMA modem is a control
center 1303 which receives control messages CNTRL from the external
system. These messages are used, for example, to assign particular
spreading codes, to activate the spreading or despreading, or to
assign transmission rates. In addition, the CDMA modem has a code
generator means 1304 used to generate the various spreading and
despreading codes used by the CDMA modem. The transmit section 1301
transmits the input information and control signals m.sub.i (t),
i=1, 2, . . . I as spread-spectrum processed user information
signals sc.sub.j (t), j=1, 2, . . . J. The transmit section 1301
receives the global pilot code from the code generator 1304 which
is controlled by the control means 1303. The spread spectrum
processed user information signals are ultimately added with other
similarly processed signals and transmitted as CDMA channels over
the CDMA RF forward message link, for example to the SUs. The
receive section 1302 receives CDMA channels as r(t) and despreads
and recovers the user information and control signal rc.sub.k (t),
k=1, 2, . . . K transmitted over the CDMA RF reverse message link,
for example to the RCS from the SUs.
[0159] CDMA Modem Transmitter Section
[0160] Referring to FIG. 12, the code generator means 1304 includes
Transmit Timing Control Logic 1401 and spreading-code PN-Generator
1402, and the Transmit Section 1301 includes MODEM Input Signal
Receiver (MISR) 1410, convolution Encoders 1411, 1412, 1413, 1414,
Spreaders 1420, 1421, 1422, 1423, 1424, and Combiner 1430. The
Transmit Section 1301 receives the message data channels MESSAGE,
convolutionally encodes each message data channel in the respective
convolutional encoder 1411, 1412, 1413, 1414, modulates the data
with random spreading-code sequence in the respective spreader
1420, 1421, 1422, 1423, 1424, and combines modulated data from all
channels, including the pilot code received in the described
embodiment from the code generator, in the combiner 1430 to
generate I and Q components for RF transmission. The Transmitter
Section 1301 of the present embodiment supports four (TR0, TR1,
TR2, TR3) 64, 32, 16, 8 Kbps programmable channels. The message
channel data is a time multiplexed signal received from the PCM
highway 1201 through PCM interface 1220 and input to the MISR
1410.
[0161] FIG. 13 illustrates the block diagram of the MISR 1410. For
the exemplary embodiment of the present invention, a counter is set
by the 8 KHz frame synchronization signal MPCMSYNC and is
incremented by 2.048 MHz MPCMCLK from the timing circuit 1401. The
counter output is compared by comparator 1502 against TRCFG values
corresponding to slot time location for TR0, TR1, TR2, TR3 message
channel data; and the TRCFG values are received from the MIU
Controller 1230 in MCTRL. The comparator sends a count signal to
the registers 1505, 1506, 1507, 1508 which clocks message channel
data into buffers 1510, 1511, 1512, 1513 using the TXPCNCLK timing
signal derived from the system clock. The message data is provided
from the signal MSGDAT from the PCM highway signal MESSAGE when
enable signal TR0EN, TR1EN, TR2EN and TR3EN from Timing Control
Logic 1401 are active. In further embodiments, MESSAGE may also
include signals that enable registers depending upon an encryption
rate or data rate. If the counter output is equal to one of the
channel location addresses, the specified transmit message data in
registers 1510, 1511, 1512, 1513 are input to the convolutional
encoders 1411, 1412, 1413, 1414 shown in FIG. 12.
[0162] The convolutional encoder enables the use of Forward error
correction (FEC) techniques, which are well known in the art. FEC
techniques depend on introducing redundancy in generation of data
in encoded form. Encoded data is transmitted and the redundancy in
the data enables the receiver decoder device to detect and correct
errors. One exemplary system which uses a modem according to the
present invention employs convolutional encoding. Additional data
bits are added to the data in the encoding process and are the
coding overhead. The coding overhead is expressed as the ratio of
data bits transmitted to the tool bits (code data+redundant data)
transmitted and is called the rate "R" of the code.
[0163] Convolution codes are codes where each code bit is generated
by the convolution of each new uncoded bit with a number of
previous coded bits. The total number of bits used in the encoding
process is referred to as the constraint length, "K", of the code.
In convolution coding, data is clocked into a shift register of K
bits length so that an incoming bit is clocked into the register,
and it and the existing K-1 bits are convolutionally encoded to
create a new symbol. The convolution process consists of creating a
symbol consisting of a module-2 sum of a certain pattern of
available bits, always including the first bit and the last bit in
at least one of the symbols.
[0164] FIG. 14 shows the block diagram of K=7, R=1/2 convolution
encoder suitable for use as the encoder 1411 shown in FIG. 12. This
circuit encodes the TR0 Channel as used in one embodiment of the
present invention. Seven-bit Register 1601 with stages Q1 through
Q7 uses the signal TXPNCLK to clock in TR0 data when the TR0EN
signal is asserted. The output value of stages Q1, Q2, Q3, Q4, Q6,
and Q7 are each combined using EXCLUSIVE-OR Logic 1602, 1603 to
produce respective I and Q channel FEC data for the TR0 channel
FECTR0DI and FECTR0DQ.
[0165] Two output symbol streams FECTR0DI and FECTR0DQ are
generated. The FECTR0DI symbol stream is generated by EXCLUSIVE OR
Logic 1602 of shift register outputs corresponding to bits 6, 5,
4.3, and 0, (Octal 171) and is designed as In phase component "I"
of the transmit message channel data. The symbol stream FECTR0DQ is
likewise generated by EXCLUSIVE-OR logic 1603 of shift register
outputs from bits 6, 4, 3, 1 and 0, (Octal 133) and is designated
as Quadrature component "Q" of the transmit message channel data.
Two symbols are transmitted to represent a single encoded bit
creating the redundancy necessary to enable error correction to
take place on the receiving end.
[0166] Referring to FIG. 14, the shift enable clock signal for the
transmit message channel data is generated by the Control Timing
Logic 1401. The convolutionally encoded transmit message channel
output data for each channel is applied to the respective spreader
1420, 1421, 1422, 1423, 1424 which multiplies the transmit message
channel data by its preassigned spreading-code sequence from code
generator 1402. This spreading-code sequence is generated by
control 1303 as previously described, and is called a random
pseudonoise signature sequence (PN-code).
[0167] The output signal of each spreader 1420, 1421, 1422, 1423,
1424 is a spread transmit data channel. The operation of the
spreader is as follows: the spreading of channel output (I+jQ)
multiplied by a random sequence (PNI+jPNQ) yields the In-phase
component I of the result being composed of (I xor PNI) and (-Q xor
PNQ). Quadrature component Q of the result is (Q xor PNI) and (I
xor PNQ). Since there is no channel data input to the pilot channel
logic (I=1, Q values are prohibited), the spread output signal for
pilot channels yields the respective sequences PNI for I component
and PNQ for Q component.
[0168] The combiner 1430 receives the I and Q spread transmit data
channels and combines the channels into an I modem transmit data
(TXIDAT) and Q modem transmit data (TXQDAT) signals. The I-spread
transmit data and the Q spread transmit data are added
separately.
[0169] For an SU, the CDMA modem Transmit Section 1301 includes the
FIR filters to receive the I and Q channels from the combiner to
provide pulse shaping, close-in spectral control and x/sin (x)
correction on the transmitted signal. Separate but identical FIR
filters (not shown) receive the I and Q spread transmit data
streams at the chipping rate, and the output signal of each of the
filters is at twice the chipping rate. The FIR filters are 28 tap
even symmetrical filters, which upsample (interpolate) by 2. The
upsampling occurs before the filtering, so that 28 taps refers to
28 taps at twice the chipping rate, and the upsampling is
accomplished by setting every other sample a zero. Exemplary
coefficients are shown in Table 8.
TABLE-US-00010 TABLE 8 Coefficient Values Coeff No. 0 1 2 3 4 5 6 7
8 9 10 11 12 13 Value 3 -11 -34 -22 19 17 32 19 52 24 94 -31 277
468 Coeff No. 14 15 16 17 18 19 20 21 22 24 25 26 27 Value 277 -31
-94 24 52 -19 -32 17 19 -22 -34 -11 3
[0170] CDMA Modem Receiver Section
[0171] Referring to FIGS. 9 and 10, the RF receiver 950 of the
present embodiment accepts analog input I and Q CDMA channels,
which are transmitted to the CDMA modems 1210, 1211, 1212, 1215
through the MIUs 931, 932, 933 from the VDC 940. These I and Q CMDA
channel signals are sampled by the CDMA modem receive section 1302
(shown in FIG. 11) and converted to I and Q digital receive message
signal using an Analog to Digital (A/D) converter 1730 of FIG. 15.
The sampling rate of the A/D converter of the exemplary embodiment
of the present invention is equivalent to the despreading code
rate. The I and Q digital receive message signals are then despread
with correlators using six different complex despreading code
sequences corresponding to the spreading code sequences of the four
channels (TR0, TR1, TR2, TR3), APC information and the pilot
code.
[0172] Time synchronization of the receiver to the received signal
is separated into two phases; there is an initial acquisition phase
and then a tracking phase after the signal timing has been
acquired. The initial acquisition is done by sliding the locally
generated pilot code sequence relative to the received signal and
comparing the output signal of the pilot despreader to a threshold.
The method used is called sequential search. Two thresholds (match
and dismiss) are calculated from the auxiliary despreader. Once the
signal is acquired, the search process is stopped and tracking
begins. The tracking maintains the code generator 1304 (shown in
FIGS. 11 and 15) used by the receiver in synchronization with the
incoming signal. The tracking loop used in the Delay-Locked Loop
(DLL) and is implemented in the acquisition & track 1701 and
the IPM 1702 blocks of FIG. 15.
[0173] In FIG. 11, the modem controller 1303 implements the Phase
Lock Loop (PLL) as a software algorithm in SW PLL logic 1724 of
FIG. 15 that calculates the phase and frequency shift in the
received signal relative to the transmitted signal. The calculated
phase shifts are used to derotate the phase shifts in rotate and
combine blocks 1718, 1719, 1720, 1721 of the multipath data signal
for combining to produce output signals corresponding to receive
channels TR0', TR1', TR2', TR3'. The data is then Viterbi decoded
in Viterbi Decoders 1713, 1714, 1715, 1716 to remove the
convolutional encoding in each of the received message
channels.
[0174] FIG. 15 indicates that the Code Generator 1304 provides the
code sequences Pn.sub.i (t), I=1, 2, . . . I used by the receive
channel despreaders 1703, 1704, 1705, 1706, 1707, 1708, 1709. The
code sequences generated are timed in response to the SYNK signal
of the system clock signal and are determined by the CCNTRL signal
from the modem controller 1303 shown in FIG. 11. Referring to FIG.
15, the CDMA modem receiver section 1302 includes Adaptive Matched
Filter (AMF) 1710, Channel despreaders 1703, 1704, 1705, 1706,
1707, 1708, 1709, Pilot AVC 1711, Auxiliary AVC 1712, Viterbi
decoders 1713, 1714, 1715, 1716, Modem output interface (MOI) 1717,
Rotate and Combine logic 1718, 1719, 1720, 1721, AMF Weight
Generator 1722, and Quantile Estimation logic 1723.
[0175] In another embodiment of the invention, the CDMA modem
receiver may also include a Bit error Integrator to measure the BER
of the channel and idle code insertion logic between the Viterbi
decoders 1713, 1714, 1715, 1716 and the MOI 1717 to insert idle
codes in the event of loss of the message data.
[0176] The Adaptive Matched Filter (AMF) 1710 resolves multipath
interference introduced by the air channel. The exemplary AMF 1717
uses an stage complex FIR filter as shown in FIG. 16. The received
I and Q digital message signals are received at the register 1820
from the A/D converter 1730 of FIG. 15 and are multiplied in
multipliers 1801, 1802, 1803, 1810, 1811 by I and Q channel weights
W1 to W11 received from AMF weight generator 1722 of FIG. 15. In
the exemplary embodiment, the A/D converter 1730 provides the I and
Q digital receive message signal data as 2's complement 6 bits I
and 6 bits Q which are clocked through an 11 stage shift register
1820 responsive to the receive spreading-code clock signal RXPNCLK.
The signal RXPNCLK is generated by the timing section 1401 of code
generation logic 1304. Each stage of the shift register is tapped
and complex multiplied in the multipliers 1801, 1802, 1803, 1810,
1811 by individual (6-bit I and 6-bit Q) weights to provide 11
tap-weighted products which are added in adder 1830, and limited to
7-bit I and 7-bit Q values.
[0177] The CDMA modem receive section 1302 (shown in FIG. 11)
provides independent channel despreaders 1703, 1704, 1705, 1706,
1707, 1708, 1709 (shown in FIG. 15) for despreading the message
channels. The described embodiment despreads 7 message channels,
each despreader accepting a 1-bit I b 1-bit Q spreading-code signal
to perform a complex correlation of this code against a 8-bit I by
8-bit Q data input. The 7 despreaders correspond to the 7 channels;
Traffic Channel 0 (TR0'), TR1', TR2', TR3', AUX (a spare channel),
Automatic Power Control (APC) and pilot (PLT).
[0178] The Pilot AVC 1711 shown in FIG. 17 receives the I and Q
Pilot Spreading-code sequence values PCI and PCQ into shift
register 1920 responsive to the timing signal RXPNCLK, and includes
11 individual despreaders 1901 through 1911 each correlating the I
and Q digital receive message signal data with a one chip delayed
versions of the same pilot code sequence. Signals OE1, OE2, . . .
OE11 are used by the modem control 1303 to enable the despreading
operation. The output signals of the despreaders are combined in
combiner 1920 forming correlation signal DSPRDAT of the Pilot AVC
1711, which is received by the ACQ & Track logic 1701 (shown in
FIG. 15), and ultimately by modem controller 1303 (shown in FIG.
11). The ACQ & Track logic 1701 uses the correlation signal
value to determine if the local receiver is synchronized with its
remote transmitter.
[0179] The Auxiliary AVC 1712 also receives the I and Q digital
receive message signal data and, in the described embodiment,
includes four separate despreaders 2001, 2002, 2003, 2004 as shown
in FIG. 18. Each despreader receives and correlates the I and Q
digital receive message data with delayed versions of the same
despreading-code sequence PARI and PARQ which are provided by code
generator 1304 input to and contained in shift register 2020. The
output signals of the despreaders 2001, 2002, 2003, 2004 are
combined in combiner 2030 which provides noise correlation signal
ARDSPRDAT. The auxiliary AVC despreading code sequence does not
correspond to any transmit spreading-code sequence of the system.
Signals OE1, OE2, . . . OE4 are used by the modem control 1303 to
enable the despreading operation. The Auxiliary AVC 1712 provides a
noise correlation signal ARDSPRDAT from which quantile estimates
are calculated by the Quantile estimator 1733, and provides a noise
level measurement to the ACQ & Track logic 1701 (shown in FIG.
15) and modem controller 1303 (shown in FIG. 11).
[0180] Each despread channel output signal corresponding to the
received message channels TR0', TR1', TR2', and TR3' is input to a
corresponding Viterbi decoder 1713, 1714, 1715, 1716 shown in FIG.
15 which performs forward error correction on convolutionally
encoded data. The Viterbi decoders of the exemplary embodiment have
a constraint length of K=7 and a rate of R=1/2. The decoded
despread message channel signals are transferred from the CDMA
modem to the PCM Highway 1201 through the MOI 1717. The operation
of the MOI is very similar to the operation of the MISR of the
transmit section 1301 (shown in FIG. 11), except in reverse.
[0181] The CDMA modem receiver section 1302 implements several
different algorithms during different phases of the acquisition,
tracking and despreading of the receive CDMA message signal.
[0182] When the received signal is momentarily lost (or severely
degraded) the idle code insertion algorithm inserts idle codes in
place of the lost or degraded receive message data to prevent the
user from hearing loud noise bursts on a voice call. The idle codes
are sent to the MOI 1717 (shown in FIG. 15) in place of the decoded
message channel output signal from the Viterbi decoders 1713, 1714,
1715, 1716. The idle code used for each traffic channel is
programmed by the Modem Controller 1303 by writing the appropriate
pattern IDLE to the MOI, which in the present embodiment is a 8 bit
word for a 64 kbps stream, 4 bit word for a 32 kbps stream.
[0183] Modem Algorithms for Acquisition and Tracking of Received
Pilot Signal
[0184] The acquisition and tracking algorithms are used by the
receiver to determine the approximate code phase of a received
signal, synchronize the local modem receiver despreaders to the
incoming pilot signal, and track the phase of the locally generated
pilot code sequence with the received pilot code sequence.
Referring to FIGS. 11 and 15, the algorithms are performed by the
Modem controller 1303, which provides clock adjust signals to code
generator 1304. These adjust signals cause the code generator for
the despreaders to adjust locally generated code sequences in
response to measured output values of the Pilot Rake 1711 and
Quantile values from quantile estimators 1723B. Quantile values are
noise statistics measured from the In-phase and Quadrature channels
from the output values of the AUX Vector Correlator 1712 (shown in
FIG. 15). Synchronization of the receiver to the received signal is
separated into two phases; an initial acquisition phase and a
tracking phase. The initial acquisition phase is accomplished by
clocking the locally generated pilot spreading-code sequence at a
higher or lower rate than the received signal's spreading code
rate, sliding the locally generated pilot spreading code sequence
and performing sequential probability ratio test (SPRT) on the
output of the Pilot Vector correlator 1711. The tracking phase
maintains the locally generated spreading-code pilot sequence in
synchronization with the incoming pilot signal.
[0185] The SU cold acquisition algorithm is used by the SU CDMA
modem when it is first powered up, and therefore has no knowledge
of the correct pilot spreading code phase, or when an SU attempts
to reacquire synchronization with the incoming pilot signal but has
taken an excessive amount of time. The cold acquisition algorithm
is divided into two subphases. The first subphase consists of a
search over the length 233415 code used by the FBCCH. Once this
sub-code phase is acquired, the pilot's 233415.times.128 length
code is known to within an ambiguity of 128 possible phases. The
second subphase is a search of these remaining 128 possible phases.
In order not to lose synch with the FBCCH, the second phase of the
search it is desirable to switch back and forth between tracking
the FBCCH code and attempting acquisition of the pilot code.
[0186] The RCS acquisition of short access pilot (SAXPT) algorithm
is used by an RCS CDMA modem to acquire the SAXPT pilot signal of
an SU. The algorithm is a fast search algorithm because the SAXPT
is a short code sequence of length N, where N=chips/symbol, and
ranges from 45 to 195, depending on the system's bandwidth. The
search cycles through all possible phases until acquisition is
complete.
[0187] The RCS acquisition of the long access pilot (LAXPT)
algorithm begins immediately after acquisition of SAXPT. The SU's
code phase is known within a multiple of a symbol duration, so in
the exemplary embodiment of the invention, there may be 7 to 66
phases to search within the round trip delay from the RCS. This
bound is a result of the SU pilot signal being synchronized to the
RCS Global pilot signal.
[0188] The re-acquisition algorithm begins when loss of code lock
(LOL) occurs. A Z-search algorithm is used to speed the process on
the assumption that the code phase has not drifted far from where
it was the last time the system was locked. The RCS uses a maximum
width of the Z-search windows bounded by the maximum round trip
propagation delay.
[0189] The Pre-Track algorithm immediately follows the acquisition
or re-acquisition algorithms and immediately precedes the tracking
algorithm. Pre-track is a fixed duration period during which the
receive data provided by the modem is not considered valid. The
Pre-Track period allows other modem algorithms, such as those used
by the ISW PLL 1724, ACQ & Tracking, AMF Weight GEN 1722, to
prepare and adapt to the current channel. The Pre-track algorithm
is two parts. The first part is the delay while the code tracking
loop pulls in. The second part is the delay while the AMF tap
weight calculations are performed by the AMF Weight Gen 1722 to
produce settled weighting coefficients. Also in the second part of
the Pre-Track period, the carrier tracking loop is allowed to pull
in by the SE PLL 1724, and the scalar quantile estimates are
performed in the Quantile estimator 1723A.
[0190] The Tracking process is entered after the Pre-Track period
ends. This process is actually a repetitive cycle and is the only
process phase during which receive data provided by the modem may
be considered valid. The following operations are performed during
this phase: AMF Tap Weight Update, Carrier Tracking, Code Tracking,
Vector Quantile Update, Scalar Quantile Update, Code Lock Check.
Derotation and Symbol Summing, and Power Control (forward and
reverse).
[0191] If loss of lock (LOL) is detected, the modem receiver
terminates the Track algorithm and automatically enters the
reacquisition algorithm. In the SU, a LOL causes the transmitter to
be shut down. In the RCS, LOL causes forward power control to
disabled with the transmit power held constant at the level
immediately prior to loss of lock. It also causes the return power
control information being transmitted to assume a 010101 . . .
pattern, causing the SU to hold its transmit power constant. This
can be performed using the signal lock check function which
generates the reset signal to the acquisition and tracking circuit
1701.
[0192] Two sets of quantile statistics are maintained, one by
Quantile estimator 1723B and the other by the scalar Quantile
Estimator 1723A. Both are used by the modem controller 1303. The
first set is the "vector" quantile information, so named because it
is calculated from the vector of four complex values generated by
the AUX AVC receiver 1712. The second set is the scalar quantile
information, which is calculated from the signal complex value AUX
signal that is output from the AUX Despreader 1707. The two sets of
information represent different sets of noise statistics used to
maintain a pre-determined Probability of False Alarm (P.sub.fa).
The vector quantile data is used by the acquisition and
reacquisition algorithms implemented by the modem controller 1303
to determine the presence of a received signal in noise, and the
scalar quantile information is used by the code lock check
algorithm.
[0193] For both the vector and scalar cases, quantile information
consists of calculated values of lambda0 through lambda2, which are
boundary values used to estimate the probability distribution
function (p.d.f.) of the despread received signal and determine
whether the modem is locked to the PN code. The Aux_Power value
used in the following C-subroutine is the magnitude squared of the
AUX signal output of the scalar correlator array for the scalar
quantiles, and the sum of the magnitudes squared for the vector
case. In both cases the quantiles are then calculated using the
following C-subroutine:
TABLE-US-00011 for (n = 0; n<3; n++) { lambda [n]+ = (lambda
[n]<Aux_Power)?CG[n]:GM[n]; }
[0194] where CG[n] are positive constants and GM[n] are negative
constants (different values are used for scalar and vector
quantiles).
[0195] During the acquisition phase, the search of the incoming
pilot signal with the locally generally pilot code sequence employs
a series of sequential tests to determine if the locally generated
pilot code has the correct code phase relative to the received
signal. The search algorithms use the Sequential Probability Ratio
Test (SPRT) to determine whether the received and locally generated
code sequences are in phase. The speed of acquisition is increased
by the parallelism resulting from having a multi-fingered receiver.
For example, in the described embodiment of the invention the main
Pilot Rake 1711 has a total of 11 fingers representing a total
phase period of 11 chip periods. For acquisition 8 separate
sequential probability ratio test (SPRTs) are implemented, with
each SPRT observing a 4 chip window. Each window is offset from the
previous window by one chip period, and in a search sequence any
given code phase is covered by 4 windows. If all 8 of the SPRT
tests are rejected, then the set of windows is moved by 8 chips. If
any of the SPRT's is accepted, then the code phase of the locally
generated pilot code sequence is adjusted to attempt to center the
accepted SPRT's phase within the Pilot AVC. It is likely that more
than one SPRT reaches the acceptance threshold at the same time. A
table lookup is used cover all 256 possible combinations of
accept/reject and the modem controller uses the information to
estimate the correct center code phase within the Pilot Rake 1711.
Each SPRT is implemented as follows (all operations occur at 64 k
symbol rate): Denote the fingers' output level values as
I_Finger[n] and Q_Finger[n], where n=0 . . . 10 (inclusive, 0 is
earliest (most advanced) finger), then the power of each window
is:
Power Window [ i ] = n ( I_Finger 2 [ n ] + Q_Finger 2 [ n ]
##EQU00017##
[0196] To implement the SPRT's the modem controller then performs
for each of the windows the following calculations which are
expressed as a pseudo-code subroutine:
TABLE-US-00012 /*find bin for Power*/ tmp = SIGMA[0]; for (k = 0;
k<3; k + + ) { if (Power>lambda [k]) tmp = SIGMA[k + 1]; }
test_statistic + = tmp; /*update statistic*/ if
(test_statistic>ACCEPTANCE_THRESHOLD) you've got ACQ; else if
(test_statistic<DISMISSAL_THRESHOLD) { forget this code phase; }
else keep trying--get more statistics;
[0197] where lambda[k] are as defined in the above section on
quantile estimation, and SIGMA[k], ACCEPTANCE_THRESHOLD and
DISMISSAL_THRESHOLD are predetermined constants. Note that SIGMA[k]
is negative for values for low values of k, and positive for right
values of k, such that the acceptance and dismissal thresholds can
be constants rather than a function of how many symbols worth of
data have been accumulated in the statistic.
[0198] The modem controller determines which bin, delimited by the
values of lambda [k], the Power level falls into which allows the
modem controller to develop an approximate statistic.
[0199] For the present algorithm, the control voltage is formed as
.epsilon.=y.sup.TBY where y is a vector formed from the complex
valued output values of the Pilot Vector correlator 1711, and B is
a matrix consisting of the constant values pre-determined to
maximize the operating characteristics while minimizing the noise
as described above with reference to the Quadratic Detector.
[0200] To understand the operation of the Quadratic Detector, it is
useful to consider the following. A spread spectrum (CDMA) signal,
s(t) is passed through a multipath channel with an impulse response
h.sub.c (t). The baseband spread signal is described by equation
(27).
s ( t ) = i C i p ( t - iT c ) ( 27 ) ##EQU00018##
[0201] where C.sub.i is a complex spreading code symbol, p(t) is a
predefined chip pulse and T.sub.c is the chip time spacing, where
T.sub.c=1/R.sub.c and R.sub.c is the chip rate.
[0202] The received baseband signal is represented by equation
(28)
r ( t ) = i C i q ( t - iT c - .tau. ) + n ( t ) ( 28 )
##EQU00019##
[0203] where q(t)=p(t)*h.sub.c(t), .tau. is an unknown delay and
n(t) is additive noise. The received signal is processed by a
filter, h.sub.R (t), so the waveform, x(t), to be processed is
given by equation (29).
x ( t ) = i C i f ( t - iT c ) - .tau. + z ( t ) ( 29 )
##EQU00020##
[0204] where f(t)=q(t)*h.sub.R(t) and z(t)=n(t)*h.sub.R(t).
[0205] In the exemplary receiver, samples of the received signal
are taken at the chip rate, that is to say, 1/T.sub.c. These
samples, x(mT.sub.c+.tau.'), are processed by an array of
correlators that compute, during the r.sup.th correlation period,
the quantities given by equation (30)
v k ( r ) = m = rL rL - L - 1 x ( mT c + .tau. ' ) C m - k * ( 30 )
##EQU00021##
[0206] These quantities are composed of a noise component
w.sub.k(r) and a deterministic component y.sub.k(r) given by
equation (31).
y.sub.k.sup.(r)=E[v.sub.k.sup.(r)]=Lf(kT.sub.c+.tau.'-.tau.)
(31)
[0207] In the sequel, the time index r may be suppressed for ease
of writing, although it is to be noted that the function f(t)
changes slowly with time.
[0208] The samples are processed to adjust the sampling phase,
.tau.', in an optimum fashion for further processing by the
receiver, such as matched filtering. This adjustment is described
below. To simplify the representation of the process, it is helpful
to describe it in terms of the function f(t+.tau.), where the time
shift, .tau., is to be adjusted. It is noted that the function
f(t+.tau.) is measured in the presence of noise. Thus, it may be
problematical to adjust the phase .tau.' based on measurements of
the signal f(t+.tau.). To account for the noise, the function v(t):
v(t)=f(t)+m(t) is introduced, where the term m(t) represents a
noise process. The system processor may be derived based on
considerations of the function v(t).
[0209] The process is non-coherent and therefore is based on the
envelope power function |v(t+.tau.|.sup.2. The functional
e(.quadrature.') given in equation (32) is helpful for describing
the process.
e(.tau.')=.intg..sub.-.infin..sup.0|v(t+.tau.'-.tau.)|.sup.2dt-.intg..su-
b.0.sup..infin.|v(t+.tau.'-.tau.)|.sup.2dt (32)
[0210] The shift parameter is adjusted for e(.quadrature.')=0,
which occurs when the energy on the interval (-.infin.,
.tau.'-.tau.] equals that on the interval [.tau.'-.tau., .infin.).
The error characteristic is monotonic and therefore has a single
zero crossing point. This is the desirable quality of the
functional. A disadvantage of the functional is that it is
ill-defined because the integrals are unbounded when noise is
present. Nevertheless, the functional e(.quadrature.') may be cast
in the form given by equation (33).
e(.tau.')=.intg..sub.-.infin..sup..infin.w(t)|v(t+.tau.'-.tau.)|.sup.2dt
(33)
[0211] where the characteristic function w(t) is equal to sgn(t),
the signum function.
[0212] To optimize the characteristic function w(t), it is helpful
to define a figure of merit, F, as set forth in equation (34).
F = [ ( .tau. 0 ' + T A ) - ( .tau. 0 ' + T A ) _ ] 2 VAR { ( .tau.
0 ' } ( 34 ) ##EQU00022##
[0213] The numerator of F is the numerical slope of the mean error
characteristic on the interval [-T.sub.A,T.sub.A ] surrounding the
tracked value, .tau.'.sub.0. The statistical mean is taken with
respect to the noise as well as the random channel, h.sub.c (t). It
is desirable to specify a statistical characteristic of the channel
in order to perform this statistical average. For example, the
channel may be modeled as a Wide Sense Stationary Uncorrelated
Scattering (WSSUS) channel with impulse response h.sub.c (t) and a
white noise process U(t) that has an intensity function g(t) as
shown in equation (35).
h.sub.c(t)= {square root over (g(t)U(t))}{square root over
(g(t)U(t))} (35)
[0214] The variance of e(.tau.) is computed as the mean square
value of the fluctuation
e'(.tau.)=e(.tau.)-e(.tau.) (36)
[0215] where <e(.tau.)> is the average of e(.tau.) with
respect to the noise.
[0216] Optimization of the figure of merit F with respect to the
function w(t) may be carried out using well-known Variational
methods of optimization.
[0217] Once the optimal w(t) is determined, the resulting processor
may be approximated accurately by a quadratic sample processor
which is derived as follows.
[0218] By the sampling theorem, the signal v(t), bandlimited to a
bandwidth W may be expressed in terms of its samples as shown in
equation (37).
v(t)=.SIGMA.v(k/W)sin c[(Wt-k).pi.] (37)
[0219] substituting this expansion into equation (z+6) results in
an infinite quadratic form in the samples
v(k/W+.quadrature.'-.quadrature.). Making the assumption that the
signal bandwidth equals the chip rate allows the use of a sampling
scheme that is clocked by the chip clock signal to be used to
obtain the samples. These samples, v.sub.k are represented by
equation (38).
v.sub.k=v(kT.sub.c+.tau.'-.tau.) (38)
[0220] This assumption leads to a simplification of the
implementation. It is valid if the aliasing error is small.
[0221] In practice, the quadratic form that is derived is
truncated. An example normalized B matrix is given below in Table
12. For this example, an exponential delay spread profile
g(t)=exp(-t/.tau.) is assumed with .tau. equal to one chip. An
aperture parameter T.sub.A equal to one and one-half chips has also
been assumed. The underlying chip pulse has a raised cosine
spectrum with a 20% excess bandwidth.
TABLE-US-00013 TABLE 12 Example B matrix 0 0 0 0 0 0 0 0 0 0 0 0 0
-0.1 0 0 0 0 0 0 0 0 0 -0.1 0.22 0.19 -0.19 0 0 0 0 0 0 0 0 0.19 1
0.45 -0.2 0 0 0 0 0 0 0 -0.19 0.45 0.99 0.23 0 0 0 0 0 0 0 0 -0.2
0.23 0 -0.18 0.17 0 0 0 0 0 0 0 0 -0.18 -0.87 -0.42 0.18 0 0 0 0 0
0 0 0.17 -0.42 -0.92 -0.16 0 0 0 0 0 0 0 0 0.18 -0.16 -0.31 0 0 0 0
0 0 0 0 0 0 0 -0.13 0 0 0 0 0 0 0 0 0 0 0 0
[0222] Code tracking is implemented via a loop phase detector that
is implemented as follows. The vector y is defined as a column
vector which represents the 11 complex output level values of the
Pilot AVC 1711, and B denotes an 11.times.11 symmetric real valued
coefficient matrix with pre-determined values to optimize
performance with the non-coherent Pilot AVC output values y. As
described above, the phase detector output is given by equation
(39);
.epsilon.=y.sup.TBy (39)
[0223] The following calculations are then performed to implement a
proportional plus integral loop filter and the VCO:
x[n]=x[n-1]+.beta..epsilon.
z[n]=z[n-1]+x[n]+.alpha..epsilon.
[0224] for .beta. and .quadrature. which are constants chosen from
modeling the system to optimize system performance for the
particular transmission channel and application, and where x[n] is
the loop filter's integrator output value and z[n] is the VCO
output value. The code phase adjustments are made by the modem
controller the following pseudo-code subroutine:
TABLE-US-00014 if (z>zmx) { delay phase 1/16 chip; z- = zmax; }
else if (z<-zmax) { advance phase 1/16 chip; z+ = zmax; }
[0225] A different delay phase could be used in the above
pseudo-code subroutine consistent with the present invention.
[0226] The AMF Tap-Weight Update Algorithm of the AMF Weight Gen
1722 (shown in FIG. 15) occurs periodically to de-rotate and scale
the phase each finger value of the Pilot Rake 1711 by performing a
complex multiplication of the Pilot AVC finger value with the
complex conjugate of the current output value of the carrier
tracking loop and applying the product to a low pass filter to
produce AMF tap-weight values, which are periodically written into
the AMF filters of the CDMA modem.
[0227] The Code lock check algorithm, shown in FIG. 15) is
implemented by the modem controller 1303 performing SPRT operations
on the output signal of the scalar correlator array. The SPRT
technique is the same as that for the acquisition algorithms,
except that the constants are changed to increase the probability
of detection of lock.
[0228] Carrier tracking is accomplished via a second order loop
that operates on the pilot output values of the scalar correlated
array. The phase detector output is the hard limited version of the
quadrature component of the product of the (complex valued) pilot
output signal of the scalar correlated array and the VCO output
signal. The loop filter is a proportional plus integral design. The
VCO is a pure summation, accumulated phase error .phi., which is
converted to the complex phasor cos .phi.+j sin .phi. using a
look-up table in memory.
[0229] The previous description of acquisition and tracking
algorithm focuses on a non-coherent method because the acquisition
and tracking algorithm described uses non-coherent acquisition
following by non-coherent tracking. This is done because, during
acquisition, a coherent reference is not available until the AMF,
Pilot AVC, Aux AVC, and DPLL are in an equilibrium state. It is,
however, known in the art that coherent tracking and combining is
preferred because in non-coherent tracking and combining the output
phase information of each Pilot AVC finger is lost. Consequently,
another embodiment of the invention employs a two step acquisition
and tracking system, in which the previously described non-coherent
acquisition and tracking algorithm is implemented first, and then
the system switches to a coherent tracking method. The coherent
combining and tracking method is similar to that described
previously, except that the error signal tracked is of the
form:
.epsilon.=y.sup.TAy (40)
[0230] where y is defined as a column vector which represents the
11 complex output level values of the Pilot AVC 1711, and A denotes
an 11.times.11 symmetric real valued coefficient matrix with
pre-determined values to optimize performance with the coherent
Pilot AVC outputs y. An exemplary A matrix is shown below.
A = 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 - 1 0 0 0 0 0 0 0 0 0 0 0 - 1 0 0 0 0 0 0 0 0 0 0 0 - 1
0 0 0 0 0 0 0 0 0 0 0 - 1 0 0 0 0 0 0 0 0 0 0 0 - 1 ( 41 )
##EQU00023##
[0231] Although the invention has been described in terms of
multiple exemplary embodiments, it is understood by those skilled
in the art that the invention may be practiced with modifications
to the embodiments which are within the scope of the invention
defined by the following claims.
* * * * *