U.S. patent application number 12/802613 was filed with the patent office on 2010-10-07 for electroplating on ultra-thin seed layers.
Invention is credited to Christian R. Bonhote, Jeffrey S. Lille, Xhavin Sinha.
Application Number | 20100252440 12/802613 |
Document ID | / |
Family ID | 39541304 |
Filed Date | 2010-10-07 |
United States Patent
Application |
20100252440 |
Kind Code |
A1 |
Bonhote; Christian R. ; et
al. |
October 7, 2010 |
Electroplating on ultra-thin seed layers
Abstract
Methods and structures for the electroplating on ultra-thin seed
layers are disclosed. A dual layer structure is utilized,
consisting of a thicker, highly conductive layer surrounding device
structures. Within the device die, an ultra-thin seed layer is
employed, which is electrically coupled to the conduction layer.
Using this technique, electroplating of critical device structures
can be carefully controlled and made uniform across the full
diameter of the wafer. The technique also allow for the deployment
of ultra-thin seed layers of varying thickness and composition in
different locations within the circuit device, or in different die
on the wafer.
Inventors: |
Bonhote; Christian R.; (San
Jose, CA) ; Lille; Jeffrey S.; (Sunnyvale, CA)
; Sinha; Xhavin; (New Westminster, CA) |
Correspondence
Address: |
D'Arcy H. Lorimer
230 Houston Way
Pismo Beach
CA
93449
US
|
Family ID: |
39541304 |
Appl. No.: |
12/802613 |
Filed: |
June 9, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11645397 |
Dec 26, 2006 |
|
|
|
12802613 |
|
|
|
|
Current U.S.
Class: |
205/170 ;
205/80 |
Current CPC
Class: |
H01L 21/76873 20130101;
C25D 5/02 20130101; H01L 2221/1089 20130101; C25D 7/123
20130101 |
Class at
Publication: |
205/170 ;
205/80 |
International
Class: |
C25D 5/10 20060101
C25D005/10; C25D 5/00 20060101 C25D005/00 |
Claims
1. A method for electroplating device structures, comprising: vapor
depositing a first seed layer on a first portion of a wafer
surface; vapor depositing a second seed layer on a second portion
of said wafer surface; vapor depositing a conduction layer on a
third portion of said wafer surface, wherein said conduction layer
is electrically coupled to said first and said second seed layers;
electroplating a first device structure on said first seed layer by
conducting electrical current through said conduction layer to said
first seed layer; and, electroplating a second device structure on
said second seed layer by conducting electrical current through
said conduction layer to said second seed layer.
2. The method as recited in claim 1, wherein said first seed layer
and said second seed layer are less than 25 nm thick.
3. The method as recited in claim 2, wherein said first seed layer
and said second seed layer comprise different materials.
4. The method as recited in claim 2, wherein said first seed layer
and said second seed layer comprise a noble metal.
5. The method as recited in claim 2, wherein said first seed layer
and said second seed layer comprise at least one of Ni, Fe, Co, and
Cr.
6. The method as recited in claim 2, wherein said first seed layer
and said second seed layer comprise Ta.
7. The method as recited in claim 2, wherein said first seed layer
and said second seed layer comprise a plurality of layers.
8. The method as recited in claim 1, wherein said conduction layer
is greater than 20 nm in thickness.
9. The method as recited in claim 8, wherein said conduction layer
comprises a noble metal.
10. The method as recited in claim 8, wherein said conduction layer
comprises at least one of Cu and Al.
11. The method as recited in claim 8, wherein said conduction layer
comprises a plurality of layers.
12. The method as recited in claim 1, wherein vapor deposition of
said conduction layer comprises sputtering said conduction
layer.
13. A method for electroplating device structures, comprising:
vapor depositing a conduction layer on a first portion of a wafer
surface; vapor depositing a seed layer on a second portion of said
wafer surface, and on at least a portion of said conduction layer;
and, electroplating a device structure on said seed layer covering
said second portion of said wafer surface, by conducting electrical
current through said conduction layer to at least a portion of said
seed layer.
14. The method as recited in claim 13, wherein said seed layer is
less than 25 nm thick.
15. The method as recited in claim 14, wherein said seed layer
comprises a noble metal.
16. The method as recited in claim 14, wherein said seed layer
comprises at least one of Ni, Fe, Co, and Cr.
17. The method as recited in claim 14, wherein said seed layer
comprises Ta.
18. The method as recited in claim 14, wherein said seed layer
comprises a plurality of layers.
19. The method as recited in claim 13, wherein said conduction
layer is greater than 20 nm in thickness.
20. The method as recited in claim 19, wherein said conduction
layer comprises a noble metal.
21. The method as recited in claim 19, wherein said conduction
layer comprises at least one of Cu and Al.
22. The method as recited in claim 19, wherein said conduction
layer comprises a plurality of layers.
23. The method as recited in claim 13, wherein vapor deposition of
said conduction layer comprises sputtering said conduction layer.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of co-pending
non-provisional application Ser. No. 11/645,397 filed Dec. 26, 2006
entitled ELECTROPLATING ON ULTRA-THIN SEED LAYERS, and claims
benefit thereof. The aforementioned application is herein
incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] This invention relates to structures and methods for
electroplating on seed layers. More specifically, the invention
relates to structures and methods for electroplating on ultra-thin
seed layers.
[0004] 2. Description of the Related Art
[0005] The use of seed layers to electroplate conductive
interconnect lines and magnetic shield structures is widely
practiced in the art of integrated circuit and micro-circuit
fabrication. Typically, a thin, electrically conductive (seed)
layer is vapor deposited on the circuit structure, which
subsequently acts as a starting cathode for the electrochemical
deposition of a much thicker plated layer. This technique is useful
for depositing thicker metal layers used for interconnect, which
would take very long times if deposited from the vapor by CVD or
sputtering, or for depositing copper which is easily and
economically electroplated.
[0006] A serious problem experienced by practitioners
electroplating on seed layers results from the relatively low
conductivity of thin seed layers as the wafer size increases and
seed layer thickness decreases, resulting in significant voltage
drops across the wafer during the electroplating process.
Typically, electrical contact with the wafer in the plating tools
occurs near the outer edge (or perimeter) of the wafer, and
electrical current needed for the deposition of plated metal in the
center of the wafer must travel across the radius. As wafer sizes
continue to increase, and seed layers continue to decrease in
thickness, this problem is exacerbated to the point where poor
plating uniformity results. In some cases, there may even be a lack
of plated conductor in the center portions of the wafer.
[0007] One solution to this problem is disclosed in FIGS. 1a, 1b,
2a, 2b, and 3a, 3b, of the prior art. FIG. 1a (Prior Art) is a
schematic plan view of a wafer substrate 102 having a plurality of
device die 104a-104f, containing previously fabricated device
structures (not shown). FIG. 1b (Prior Art) is a cross sectional
view through section A-A of FIG. 1a. A single seed layer is then
blanket deposited on the wafer surface in preparation for the
electroplating process. FIG. 2a (Prior Art) is a schematic plan
view of the wafer of FIG. 1a subsequent to the deposition of a seed
layer 202. Subsequent to the seed layer deposition, a conduction
layer, typically copper, is electroplated in the outer perimeter
areas of the wafer and in the "galley" areas between device die.
Generally, no plating is performed within the device areas of the
die, as these areas are masked off. FIG. 3a (Prior Art) is a plan
view of the wafer of FIG. 2a subsequent to the electroplating of a
conductive layer 306. Layer 306 serves as a conductive plating
"buss" for subsequent plating of device structures within the die
(i.e. 104a-104f). In the plating tools, contact with the wafer is
typically made at the outer perimeter areas of the wafer, for
example in area 302. The dark arrows 304 show the current paths
that result during the subsequent plating of structures within the
device die. Although this technique does reduce voltage drops
across the wafer when plating device structures, it has a number of
disadvantages.
[0008] One disadvantage is that the seed layer 202 still must be
reasonably thick, typically 250 to 1000 angstroms or greater.
Otherwise electroplating of the conduction layer 306 will be
non-uniform, with large variations in plated thickness occurring
from center to edge. Voids may also be formed in the galleys,
causing some die areas to be isolated in subsequent device
structure plating processes. The use of ultra-thin seed layers, for
example seed layers under 250 angstroms, may be unsuitable for this
process.
[0009] Another disadvantage is that this prior art process uses a
single seed layer of uniform composition. In current and future
device technology, multiple seed layers of different chemical
compositions, layer structures, and thickness may be required
within the device die at varying locations. This functionality is
required because seed layers have additional functional properties
that are customized to match particular device structures. For
example, seed layers may be required to have anti-reflective
properties to aid in photo resist exposure. They must also have
good adhesion to both underlying materials and photo resists that
will be deposited on their surface, as well as the plated materials
that will be deposited on them. They need to be compatible with the
plating bath chemistry, and not oxidize, corrode, or dissolve in
the bath. They need to be compatible with the plated device design,
if they are part of critically dimensioned structure like a
perpendicular write head, for example. A single seed layer cannot
meet all these requirements. Thicker seed layers suitable for the
prior art process, may not be compatible with device structures
such as perpendicular write heads, where the seed layer is an
integral part of the structure separating the plated shield from
other structures within the head. Furthermore, due to the wide
variety of seed materials needed, some compositions may not be
chemically stable when exposed to copper plating bath chemistries,
particularly at thickness ranges below 250 angstroms.
[0010] What is needed is a better process for electroplating on
ultra-thin seed layers of varying composition and thickness, while
maintaining good device structure plating uniformity across the
full diameter of the wafer.
[0011] A summary of the relevant prior art is provided below.
[0012] An article entitled "Network Plating on Seed Layer to
Improve Plating Uniformity", by Fu et al., published in the IBM
Technical Disclosure Bulletin, May 1992, discloses a method to
improve plating uniformity throughout the' active device area of a
substrate based on pre-plating the inactive area of a substrate to
enhance electrical conductivity and current distribution across the
substrate.
[0013] United States Patent Application Publication 2001/0022704
discloses a method and system for a write head. The method and
system include the steps of providing a first pole and providing a
bottom antireflective coating (BARC) layer. The BARC layer is
conductive, nonmagnetic, and an antireflective coating. A portion
of the BARC layer is disposed above the first pole. The method and
system also include providing a photoresist structure having a
trench therein. The method and system also include providing a
second pole. A portion of the second pole is disposed above the
portion of the BARC layer and within the trench. Thus, the width of
the pole may be better controlled.
[0014] U.S. Pat. No. 5,744,019 discloses multiple-layer thin film
devices deposited by electroplating on an otherwise substantially
clean substrate wafer. The composition of the electroplated alloy
layers is maintained substantially uniform using a cathode assembly
on which the substrate wafer is mounted. The cathode assembly
includes an inner cathode ring electrically connected to the wafer,
a thief ring external to the cathode ring and an insulating ring
connected between and electrically insulating the cathode and thief
rings. The cathode ring and the thief ring are powered by separate
power sources.
[0015] U.S. Pat. No. 5,805,392 discloses pole pieces of a thin film
head formed by two thin film layers of the magnetic metal NiFe,
each NiFe layer being about 20,000 angstroms thick. These two NiFe
layers are separated by an electrically insulating layer of alumina
(Al.sub.2O.sub.3), ceramic or NiFe oxide that is about 100
angstroms thick. In one embodiment, a hard-baked photoresist layer
is formed only around the edges of the first NiFe layer, the
electrically insulating layer is deposited over the top surface of
the first NiFe layer and over the hard-baked photoresist layer, and
the second NiFe layer is then deposited, thus providing a
three-layer metal/insulator/metal pole piece wherein the hard baked
photoresist blocks edge short circuiting between the two thin film
NiFe layers. In another embodiment, edge short circuiting is
minimized by allowing a small filament(s) of a high electrical
resistance plating seed layer of NiFe to extend between the two
NiFe thin film layers, the high resistance of these long and thin
NiFe filaments being much greater than the resistance of the two
NiFe thin film layers.
[0016] U.S. Pat. No. 5,901,432 discloses a method for making a
merged thin film read/write head, where the first pole piece
includes a pedestal or pole tip portion that extends up from the
first pole piece layer, using electroplating to form the gap so
that the gap layer does not have to be removed later. After the
first pole piece is deposited, the coil insulation structure is
built over the first pole piece. Afterwards an electrically
conductive seed layer of the same ferromagnetic material as the
first pole piece is formed over the wafer to provide an
electrically conductive path for subsequent electroplating. After
the seed layer deposition, a photoresist pattern is then formed to
define the shape of the second pole piece. Nonmagnetic
nickel-phosphorous is then electroplated onto the seed layer in the
region not covered by the photoresist pattern to form the gap
layer. The second ferromagnetic layer is then electroplated onto
the gap layer to define the shape of the second pole piece. The
thickness of the second pole piece layer is deliberately made
thicker than the desired final thickness because the second pole
piece layer is used as a mask for subsequent ion beam milling to
form the notched pole tip element of the first pole piece. The
photoresist is removed and ion beam milling performed to remove the
seed layer and a portion of the first pole piece layer to define
the pedestal pole tip element of the first pole piece. The ion beam
milling does not have to remove the gap layer because the
electroplated gap has been defined by the photoresist pattern to
have the desired trackwidth.
[0017] U.S. Pat. No. 6,140,234 discloses selectively plating
recesses in a semiconductor structure, by providing electrical
insulating layer over the semiconductor substrate and in the
recesses, followed by forming a conductive barrier over the
insulating layer; providing a plating seed layer over the barrier
layer; depositing and patterning a photoresist layer over the
plating seed layer; planarizing the insulated horizontal portions
by removing the horizontal portions of the seed layer between the
recesses; removing the photoresist remaining in the recesses; and
then electroplating the patterned seed layer with a conductive
metal using the barrier layer to carry the current during the
electroplating to thereby only plate on the seed layer. In an
alternative process, a barrier film is deposited over recesses in
an insulator. Then, relatively thick resists are lithographically
defined on the field regions, on top of the barrier film over the
recesses. A plating base or seed layer is deposited, so as to be
continuous on the horizontal regions of the recesses in the
insulator, but discontinuous on their surround wall. The recesses
are then plated using the barrier film without seed layers at the
periphery of the substrate wafers for electrical contact. After
electroplating, the resist is removed by lift-off process and
exposed barrier film is etched by RIE method or by CMP. Also
provided is a semiconductor structure obtained by the above
processes.
[0018] U.S. Pat. No. 6,514,393 discloses an electrochemical reactor
used to electrofill damascene architecture for integrated circuits
or for electropolishing magnetic disks. An inflatable bladder is
used to screen the applied field during electroplating operations
to compensate for potential drop along the radius of a wafer. The
bladder establishes an inverse potential drop in the electrolytic
fluid to overcome the resistance of a thin film seed layer of
copper on the wafer.
[0019] U.S. Pat. No. 6,540,928 discloses a method and apparatus for
fabricating an electroplating mask for the formation of a miniature
magnetic pole tip structure. The method incorporates a silylation
process to silylate photo-resist after creating a photo-resist
cavity or to trench in the electroplating mask. The silylation
process is performed after a dry etch of the photo-resist.
Alternatively, silylation is performed after a lithographic
patterning of the trench. As a result of chemical biasing, the
vertical side walls of the photoresist layer shift inward creating
a narrower trench. The resulting structure formed after
electroplating has a width of less than 0.3 micrometers. This
structure can be used as a magnetic pole of a thin film head
("TFH") for a data storage device.
[0020] U.S. Pat. No. 6,589,816 discloses a method of forming metal
connection elements in integrated circuits formed on adjacent areas
of a wafer, including forming a conductive seed layer on a
substrate of the wafer. A first mask covers the integrated circuits
and leaves exposed areas of the seed layer overlying predetermined
scribe lines used for separation of the integrated circuits. Using
the seed layer as a cathode, a metal is deposited by an
electrochemical process on exposed areas of the seed layer. The
first mask is removed and a second mask is formed, leaving
predetermined areas of the seed layer exposed. Using the seed layer
as a cathode a metal is deposited on the exposed predetermined
areas by an electrochemical process. The second mask is then
removed. Connection elements of uniform thickness throughout the
substrate are produced with the use of a very thin seed layer.
[0021] U.S. Pat. No. 6,774,039 discloses copper bus bars formed
between adjacent die on a wafer during the process flow. The bus
bars are between 50 and 100 microns wide and between 2 and 5
microns deep. A barrier layer is formed between the bus bars and
the die to prevent copper diffusion. A dielectric layer is
deposited over the bus bars and die and etched with contacts and
features, such as vias. A seed layer is subsequently deposited over
the wafer, which allows electrical conductance between the bus bars
and the die during a subsequent electroplating process to fill the
features and contacts. The bus bars carry electroplating current
from the die edge to the die center. As a result, current does not
need to be carried by a low sheet resistivity seed layer from the
wafer edge to the center. This allows the seed layer to be thinner
and of materials other than copper. Further, thinner seed layers
allow thicker barrier layer for more reliability.
[0022] U.S. Pat. No. 6,807,027 discloses a perpendicular write head
including a main pole, a return pole, and conductive coils. The
main pole includes a seed layer and a magnetic layer that is plated
upon the seed layer. The seed layer is nonmagnetic, electrically
conductive, and corrosion-resistant. The return pole is separated
from the main pole by a gap at an air bearing surface of the write
head and is coupled to the main pole opposite the air bearing
surface. The conductive coils are positioned at least in part
between the main pole and the return pole.
[0023] U.S. Pat. No. 6,811,670 discloses a method for forming
electroplating cathode contacts around the periphery of a
semiconductor wafer, including forming an insulating layer over a
conductive layer extending at least around the periphery of a
semiconductor wafer substrate; etching a plurality of openings
around a peripheral portion of the semiconductor wafer substrate
through the insulating layer to extend through a thickness of the
insulating layer in closed communication with the conductive layer
said conductive area in electrical communication with a central
portion of the semiconductor wafer substrate; filling the plurality
of openings with metal to form electrically conductive pathways;
planarizing the electrically conductive pathway surfaces; and,
forming a metal layer over the electrically conductive pathway
surfaces to form a plurality of contact pads for contacting a
cathode for carrying out an electroplating process.
[0024] U.S. Pat. No. 6,861,355 discloses a seed film and methods
incorporating the seed film in semiconductor applications. The seed
film includes one or more noble metal layers, where each layer of
the one or more noble metal layers is no greater than a mono-layer.
The seed film also includes either one or more conductive metal
oxide layers or one or more silicon oxide layers, where either
layer is no greater than a mono-layer. The seed film can be used in
plating, including electroplating, conductive layers, over at least
a portion of the seed film. Conductive layers formed with the seed
film can be used in fabricating an integrated circuit, including
fabricating capacitor structures in the integrated circuit.
[0025] U.S. Pat. No. 6,949,833 discloses a structure including a
substrate with a top surface and a bottom surface, an etched
dielectric layer having sidewalls and an upper surface, wherein the
etched dielectric layer with a thickness of v, is positioned upon a
first portion of the top surface of the substrate but not
positioned upon a second portion of the top surface of the
substrate having a width equal to x, an atomic layer deposited
(ALD) film with a thickness of y, positioned upon the upper surface
of the etched dielectric layer, the sidewalls of the etched
dielectric layer, and the second portion of the top surface of the
substrate, and a trench formed by the atomic layer with a width
equal to x-2y. The patent also discloses a method of forming a
structure with a trench that includes the steps of depositing a
dielectric layer on a substrate, forming a patterned photoresist on
the dielectric layer, forming a space having a width x, by etching
the dielectric layer, removing the patterned photoresist to form a
gap having sidewalls and a bottom, and depositing an atomic layer
with a thickness of y on the etched dielectric layer, and the
sidewalls and the bottom of the gap, wherein a trench is formed by
the atomic layer deposited on the sidewalls and bottom of the
gap.
[0026] U.S. Pat. No. 7,037,574 discloses an atomic layer deposition
(ALD) process that deposits thin films for microelectronic
structures, such as advanced gap and tunnel junction applications,
by plasma annealing at varying film thicknesses to obtain desired
intrinsic film stress and breakdown film strength. The primary
advantage of the ALD process is the near 100% step coverage with
properties that are uniform along sidewalls. The process provides
smooth (R.sub.a about 2 angstroms), pure (impurities<1 at. %),
AlO.sub.x films with improved breakdown strength (9-10 MV/cm) with
a commercially feasible throughput.
[0027] U.S. Pat. No. 7,052,922 discloses a method and apparatus for
plating facilitating the plating of a small contact feature of a
wafer die while providing a relatively stable plating bath. The
method utilizes a supplemental plating structure that is larger
than a die contact that is to be plated. The supplemental plating
structure may be located on the wafer, and is conductively
connected to the die contact. Conductive connection between the die
contact and the supplemental plating structure facilitates the
plating of the die contact. The supplemental plating structure also
can be used to probe test the die prior to singulation.
SUMMARY OF THE INVENTION
[0028] It is an object of the present invention to provide a method
for electroplating device structures, including vapor depositing a
seed layer on a first portion of a wafer surface; vapor depositing
a conduction layer on a second portion of the wafer surface,
wherein the conduction layer is electrically coupled to the seed
layer; and, electroplating a device structure on the seed layer by
conducting electrical current through the conduction layer to the
seed layer.
[0029] It is another object of the present invention to provide a
method for electroplating device structures, including vapor
depositing a first seed layer on a first portion of a wafer
surface; vapor depositing a second seed layer on a second portion
of the wafer surface; vapor depositing a conduction layer on a
third portion of the wafer surface, wherein the conduction layer is
electrically coupled to the first and second seed layers;
electroplating a first device structure on the first seed layer by
conducting electrical current through the conduction layer to the
first seed layer; and, electroplating a second device structure on
the second seed layer by conducting electrical current through the
conduction layer to the second seed layer.
[0030] It is another object of the present invention to provide a
method for electroplating device structures, including vapor
depositing a seed layer on a wafer surface, vapor depositing a
conduction layer on a first portion of the seed layer and,
electroplating a device structure on a second portion of the seed
layer by conducting electrical current through the conduction layer
to the second portion of the seed layer.
[0031] It is yet another object of the present invention to provide
a method for electroplating device structures, including vapor
depositing a conduction layer on a first portion of a wafer
surface, vapor depositing a seed layer on a second portion of the
wafer surface, and on at least a portion of said conduction layer;
and, electroplating a device structure on the seed layer covering
the second portion of the wafer surface, by conducting electrical
current through the conduction layer to at least a portion of the
seed layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0032] The present invention will be better understood when
consideration is given to the following detailed description
thereof. Such description makes reference to the annexed drawings,
wherein:
[0033] FIG. 1a (Prior Art) is a schematic plan view of a wafer
having a plurality of device die;
[0034] FIG. 1b (Prior Art) is a cross sectional view through
section A-A of FIG. 1a;
[0035] FIG. 2a (Prior Art) is a schematic plan view of the wafer of
FIG. 1a subsequent to the deposition of seed layer 202;
[0036] FIG. 2b (Prior Art) is a cross section view through section
B-B of FIG. 2a;
[0037] FIG. 3a (Prior Art) is a schematic plan view of the wafer of
FIG. 2a subsequent to the electroplating of a conduction layer
306;
[0038] FIG. 3b (Prior Art) is a cross sectional view through
section C-C of FIG. 3a;
[0039] FIG. 4a is a schematic plan view of a wafer subsequent to
the deposition of ultra-thin seed layer 406, in accordance with an
embodiment of the present invention;
[0040] FIG. 4b is a cross sectional view through section D-D of
FIG. 4a, in accordance with an embodiment of the present
invention;
[0041] FIG. 4c is an expanded schematic plan view of die 404c of
FIG. 4a, in accordance with an embodiment of the present
invention;
[0042] FIG. 5a is a schematic plan view of a wafer subsequent to
the vapor deposition of conduction layer 502, in accordance with an
embodiment of the present invention;
[0043] FIG. 5b is a cross sectional view through section E-E of
FIG. 5a, in accordance with an embodiment of the present
invention;
[0044] FIG. 5c is an expanded schematic plan view of die 404c of
FIG. 5a, in accordance with an embodiment of the present
invention;
[0045] FIG. 6a is a schematic plan view of a wafer subsequent to
the vapor deposition of conduction layer 602, in accordance with an
embodiment of the present invention;
[0046] FIG. 6b is a cross sectional view through section F-F of
FIG. 6a, in accordance with an embodiment of the present
invention;
[0047] FIG. 6c is an expanded schematic plan view of die 404c of
FIG. 6a, in accordance with an embodiment of the present
invention;
[0048] FIG. 7a is a schematic plan view of a wafer subsequent to
the vapor deposition of ultra-thin seed layer 702, in accordance
with an embodiment of the present invention;
[0049] FIG. 7b is a cross sectional view through section G-G of
FIG. 7a, in accordance with an embodiment of the present
invention;
[0050] FIG. 7c is an expanded schematic plan view of die 404c of
FIG. 7a, in accordance with an embodiment of the present
invention;
[0051] FIG. 8a is a schematic plan view of a wafer subsequent to
the vapor deposition of conduction layer 804, and the selective
vapor deposition of a plurality of ultra-thin seed layers, in
accordance with an embodiment of the present invention;
[0052] FIG. 8b is a cross sectional view through section H--H of
FIG. 8a, in accordance with an embodiment of the present
invention;
[0053] FIG. 8c is an expanded schematic plan view of die 404c of
FIG. 8a, in accordance with an embodiment of the present
invention;
[0054] FIG. 9a is a schematic block diagram of a first
electroplating process, in accordance with an embodiment of the
present invention;
[0055] FIG. 9b is a schematic block diagram of a second
electroplating process, in accordance with an embodiment of the
present invention;
[0056] FIG. 9c is a schematic block diagram of process step 902 of
FIGS. 9a and 9b, in accordance with an embodiment of the present
invention; and,
[0057] FIG. 9d is a schematic block diagram of process step 904 of
FIGS. 9a and 9b, in accordance with an embodiment of the present
invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0058] FIGS. 1a-3b have been discussed above in the Background
section.
[0059] FIG. 4a is a schematic plan view 400 of a wafer subsequent
to the deposition of ultra-thin seed layer 406, in accordance with
an embodiment of the present invention. FIG. 4b is a cross
sectional view 401 through section D-D of FIG. 4a. The dashed boxes
in FIG. 4a represent regions of active device areas formed on wafer
402 surface, as, for example, shown in FIG. 1a (Prior Art). For
subsequent discussion, these areas will be referred to as device
die. An exemplary array of device die is represented by items
404a-404f. Within the device die, numerous previously fabricated
devices are present. Further processing steps may require that
various device structures are subsequently electroplated over these
previously fabricated devices, which requires electroplating on
localized areas of the device die. The electroplated device
structures may be, for example, interconnect lines, vias, or
magnetic shield structures. The device die are separated from each
other by thin passages known as galleys. As mentioned previously,
electroplating current must be delivered from the outer perimeter
areas of the wafer, through the galleys, to the localized areas
within the device die themselves. A first step in this process is
represented by FIG. 4a, wherein an ultra-thin seed layer 406 is
deposited throughout the full wafer surface. An ultra-thin seed
layer is typically a seed layer less than about 25 nm (250
Angstroms) in thickness, and may be as thin as 1 nm (10 Angstroms).
The ultra-thin seed layer is generally comprised of a metal or
metal alloy, preferably: a noble metal such as Au, Ag, Pd, Pt, Rh,
Ru, Ir, Os and alloys thereof; alloys of Ni and P; alloys of Ni and
Cr; alloys of Ni, Fe, and Co; W, and Ta. The ultra-thin seed layer
may be comprised of a uniform alloy or composition, or may be
comprised of a plurality of layers. For example, a capping layer
may also be added to improve adhesion to photo resist layers
deposited over the seed layer. Under-layers or base layers may also
be employed to improve adhesion of the seed layer to the material
underneath. Deposition of the ultra-thin seed layer 406 may be a
uniform, blanket deposition, or the deposition may be selectively
limited to specific areas within each device die, and/or to regions
surrounding the plurality of dies on the wafer. This may be done
through additive (mask, deposit, remove mask) or subtractive
(deposit, mask, etch, remove mask) processing. If a uniform,
blanket deposition is used, the specific device structures to be
electroplated within the die can be masked prior to plating, the
additional unwanted ultra-thin seed layer being removed by etching
subsequent to electroplating. One advantage of the present
invention is that the very thin seed layers can be easily removed
without damage to the subsequently plated structures. Although the
ultra-thin seed layer 406 is shown as a continuous layer in FIGS.
4a and 4b for simplicity of illustration, a selective deposition is
also suitable, as is shown, for example, in FIG. 4c.
[0060] FIG. 4c is an expanded schematic plan view of die 404c of
FIG. 4a, in accordance with an embodiment of the present invention.
In this expanded view, selective deposition of ultra-thin seed
layers on previously fabricated active device regions 408a, 408b,
410a, and 410b are illustrated. The specific shapes of the active
device regions are illustrative only, and not meant to limit this
disclosure to or convey any particular type of electronic device.
Regions 408a and 408b represent active devices wherein only a
portion of the device area is to be plated. Regions 410a and 410b
represent regions where the entire device area is to be plated.
Region 412 represents a structure where no electroplating is
desired. Device regions 408a, 408b, 410a, 410b are connected to the
perimeter region surrounding die 404c by conductive pathways of
ultra-thin seed layer 406. The actual deposition process would
involve numerous masking, deposition, and photo resist stripping
steps (not shown), which are well known to those skilled in the
art. As previously mentioned, the case of a blanket deposition of
ultra-thin seed layer 406, wherein all structures within the die
are uniformly covered (not shown in FIG. 4c), is also possible, and
may be preferred to minimize seed layer resistance within the die
404c. Following the deposition of the ultra-thin seed layer, a
thicker, conduction layer is vapor deposited on the wafer to reduce
voltage drops from the outer perimeter of the wafer, where contact
is made with the plating devices and the wafer surface.
[0061] FIG. 5a is a schematic plan view 500 of a wafer subsequent
to the vapor deposition of conduction layer 502, in accordance with
an embodiment of the present invention. FIG. 5b is a cross
sectional view 501 through section E-E of FIG. 5a. Conduction layer
502 is considerably thicker and of lower resistance than ultra-thin
seed layer 406. It need not be optimized with respect to plated
device structures, as its sole purpose is to facilitate plating
current transport to regions surrounding (and in some cases
extending into) the device die. As such, it is primarily deposited
in the outer perimeter regions of the wafer where electrical
contacts with the wafer are made during electroplating, and in the
galleys between the device die. In the perimeter areas surround
each device die, overlap between ultra-thin seed layer 406 and
conductive seed layer 502 must be provided to insure electrical
conductivity between the two layers so that device areas covered by
the ultra-thin seed layer 406 can be electroplated. Encroachment of
conduction layer 502 within the device die area may be permitted if
it does not impede device operation, or create problems requiring
subsequent removal. Deposition of conduction layer 502 may be
carried out by vapor deposition techniques, such as sputtering,
CVD, evaporative deposition, e-beam deposition, and various plasma
assisted deposition techniques. Deposition is limited to the areas
shown by photo resist masking techniques, well known to those of
ordinary skill in the art. Although prior art disclosures recommend
electroplating of this layer, electroplating requires a seed layer
prior to deposition. This seed layer must effectively be much
thicker than ultra-thin seed layer 406, requiring a second seed
layer deposition prior to plating when ultra-thin seed layers are
need to electroplate the device structures. Electroplating the
conduction layer adds additional steps, which are eliminated by the
present invention, using a vapor deposited conduction layer.
[0062] Conduction layer 502 can be composed of any conductive
material, preferably a metal or metal alloy, that can be deposited
by a vapor deposition technique. All the materials and deposition
techniques cited for the ultra-thin seed layer are acceptable, with
the inclusion of low cost base metals such as copper and aluminum.
Conduction layer 502 can comprise a single layer, or have multiple
layers. For example, conduction layer 502 could be composed of a
copper or aluminum base layer, covered with a thin gold protective
layer, to reduce corrosion in the plating bath. Conduction layer
502 must be compatible with ultra-thin seed layer 406 with respect
to adhesion, interfacial resistance, and galvanic corrosion. That
is, the two layers (seed and conduction) must adhere to one
another, there should be an acceptably low resistance at their
interface, and the coupling of the two layers cannot promote
corrosion in the aqueous plating bath when the device structures
are plated. Conduction layer 502 can range from about 20 nm to 100
nm in thickness, depending on its conductivity, with the more
conductive materials, such as copper and Rh, requiring thinner
layers.
[0063] FIG. 5c is an expanded schematic plan view of die 404c of
FIG. 5a, in accordance with an embodiment of the present invention.
In this figure, the conduction layer 502 surrounds device die 404c,
providing conduction to selectively deposited regions on device
structures 408a,b and 410a,b. As disclosed above, a blanket
deposition (not shown in FIG. 5c) of ultra-thin seed layer 406 may
also be utilized.
[0064] FIGS. 6a-7c disclose an alternate embodiments of the present
invention, wherein the deposition order of the conduction layer and
the ultra-thin seed layer(s) are reversed. FIG. 6a is a schematic
plan view 600 of a wafer subsequent to the vapor deposition of
conduction layer 602. FIG. 6b is a cross sectional view 601 through
section F-F of FIG. 6a. In FIGS. 6a and 6b, conduction layer 602 is
deposited on the wafer surface, primarily in the outer perimeter
regions of the wafer and within the galleys between the device die,
as was described for conduction layer 502 previously. FIG. 6c is an
expanded schematic plan view of die 404c of FIG. 6a. In this
figure, conduction layer 602 is excluded from regions within die
404c, although encroachment of conduction layer 602 within the
device die area may be permitted if it does not impede device
operation, or create problems requiring subsequent removal.
Composition, thickness, and deposition techniques disclosed above
for conduction layer 502 apply equally to conduction layer 602.
[0065] FIG. 7a is a schematic plan view 700 of a wafer subsequent
to the vapor deposition of ultra-thin seed layer 702, in accordance
with an embodiment of the present invention.
[0066] FIG. 7b is a cross sectional view 701 through section G-G of
FIG. 7a. Ultra-thin seed layer 702 is deposited throughout the full
wafer surface, covering layer 602. Deposition of the ultra-thin
seed layer 702 may be a uniform, blanket deposition, or the
deposition may be selectively limited to specific areas within each
device die, and/or to regions surrounding the plurality of dies on
the wafer. This may be done through additive (mask, deposit, remove
mask) or subtractive (deposit, mask, etch, remove mask) processing.
If a uniform, blanket deposition is used, the specific structures
to be electroplated within the die can be masked prior to plating,
the additional unwanted ultra-thin seed layer being removed by
etching subsequent to electroplating. Ultra-thin seed layer 702 is
shown as a continuous layer in FIGS. 7a and 7b for simplicity of
illustration, a selective deposition is also suitable, as is shown,
for example, in FIG. 7c. Composition, thickness, and deposition
techniques disclosed above for ultra-thin seed layer 406 apply
equally to ultra-thin seed layer 702.
[0067] FIG. 7c is an expanded schematic plan view of die 404c of
FIG. 7a. In this expanded view, selective deposition of ultra-thin
seed layers on active device regions 408a, 408b, 410a, and 410b are
illustrated. Regions 408a and 408b represent active devices wherein
only a portion of the device area is to be plated. Regions 410a and
410b represent regions where the entire device area is to be
plated. Region 412 represents a structure where no electroplating
is desired. Device regions 408a, 408b, 410a, 410b are connected to
the perimeter region surrounding die 404c by conductive pathways of
ultra-thin seed layer 702. The actual deposition process would
involve numerous masking, deposition, and photo resist stripping
steps (not shown), which are well known to those skilled in the
art. As previously mentioned, the case of a blanket deposition of
ultra-thin seed layer 702, wherein all structures within the die
are uniformly covered (not shown in FIG. 4c), is also possible, and
may be preferred to minimize seed layer resistance within the die
404c.
[0068] FIG. 8a is a schematic plan view 800 of a wafer subsequent
to the vapor deposition of conduction layer 804, and the selective
vapor deposition of a plurality of ultra-thin seed layers, in
accordance with an embodiment of the present invention. FIG. 8b is
a cross sectional view through section H-H of FIG. 8a. FIGS. 8a and
8b disclose the selective vapor deposition of a plurality of
ultra-thin seed layers 802a-802f following the vapor deposition of
conductive layer 804. Of course, as will be recognized by those
skilled in the art, the deposition order can also be reversed,
wherein the plurality of ultra-thin seed layers is deposited on the
wafer prior to the deposition of conductive layer 804. The
plurality of ultra-thin seed layers can be distinguished from one
another by thickness, composition, or both. Although FIGS. 8a and
8b indicate that the same ultra-thin seed layer is used within a
particular vertical column of die, it will be evident to those
skilled in the art that any combination of ultra-thin seed layer
parameters can be employed in any die, in random fashion.
Deposition of the ultra-thin seed layers 802a-802f may be a uniform
deposition within each die, or the deposition may be selectively
limited to specific areas within each device die. This may be done
through additive (mask, deposit, remove mask) or subtractive
(deposit, mask, etch, remove mask) processing. Composition,
thickness, and deposition techniques disclosed above for ultra-thin
seed layer 406 apply equally to ultra-thin seed layers 802a-802f.
Composition, thickness, and deposition techniques disclosed above
for conduction layer 502 apply equally to conduction layer 802.
[0069] FIG. 8c is an expanded schematic plan view of die 404c of
FIG. 8a. In this figure, for example, various ultra-thin
compositions and/or thicknesses are applied to different device
structures 408a', 408b', 410a', 410b', 410c' within die 404c. Each
may be electroplated with different materials, in separate stages,
if required. Conduction paths are provided from each device area to
the surrounding conduction film 804. The actual deposition process
would involve numerous masking, deposition, and photo resist
stripping steps (not shown), which are well known to those skilled
in the art.
[0070] FIG. 9a is a schematic block diagram of a first
electroplating process 900, in accordance with an embodiment of the
present invention. In step 902, ultra-thin seed layers are vapor
deposited in the wafer surface, in accordance with the processes
and limitations previously disclosed. In step 904, the conduction
layer is deposited, also in accordance with the processes and
limitations previously disclosed. In step 906, a plating mask is
deposited to limit the plating deposition to desired areas and
structures within the device die, using processes well known to
those skilled in the art. In step 908, the device structures are
electroplated. In an optional step (not shown), the ultra-thin seed
layers can be removed by etching without damage to remaining
structures.
[0071] FIG. 9b is a schematic block diagram of a second
electroplating process 901, in accordance with an embodiment of the
present invention. In this process, steps 902 and 904 are
reversed.
[0072] FIG. 9c is a schematic block diagram of process step 902 of
FIGS. 9a and 9b, in accordance with an embodiment of the present
invention. This generalized process illustrates the deposition of
more than one ultra-thin seed layer in electroplating processes 900
and 901. In step 910, a first Mask.sub.1 is deposited. In step 912,
a first ultra-thin seed layer UTSL.sub.1 is selectively vapor
deposited. In step 914, Mask.sub.1 is removed, leaving a portion of
UTSL.sub.1 on the wafer surface. Steps 916-926 are optional,
depending on the number of seed layers to be deposited. In step
916, a second Mask.sub.2 is deposited. In step 918, a first
ultra-thin seed layer UTSL.sub.2 is selectively vapor deposited. In
step 920, Mask.sub.2 is removed, leaving a portion of UTSL.sub.2 on
the wafer surface. The process continues until the last (Mask.sub.n
and UTSL.sub.n) are deposited, in steps 922-926.
[0073] FIG. 9d is a schematic block diagram of process step 904 of
FIGS. 9a and 9b, in accordance with an embodiment of the present
invention. In step 930, a mask for the conduction layer is
deposited, which limits deposition of the conduction layer to the
desired areas on the wafer. In step 932, the conduction layer is
vapor deposited, in accordance with the processes and limitations
previously disclosed. In step 934, the mask is removed.
[0074] The present invention is not limited by the previous
embodiments heretofore described. Rather, the scope of the present
invention is to be defined by these descriptions taken together
with the attached claims and their equivalents.
* * * * *