U.S. patent application number 12/795467 was filed with the patent office on 2010-09-30 for clock recovery from data streams containing embedded reference clock values.
This patent application is currently assigned to STMicroelectronics Pvt.. Ltd.. Invention is credited to Kalyana Chakravarthy.
Application Number | 20100246736 12/795467 |
Document ID | / |
Family ID | 11097128 |
Filed Date | 2010-09-30 |
United States Patent
Application |
20100246736 |
Kind Code |
A1 |
Chakravarthy; Kalyana |
September 30, 2010 |
CLOCK RECOVERY FROM DATA STREAMS CONTAINING EMBEDDED REFERENCE
CLOCK VALUES
Abstract
A method and an improved apparatus for clock recovery from data
streams containing embedded reference clock values controlled clock
source means includes of a controllable digital fractional divider
means receiving a control value from digital comparator means and a
clock input from a digital clock synthesizer means driven by a
fixed oscillator means.
Inventors: |
Chakravarthy; Kalyana;
(Delhi, IN) |
Correspondence
Address: |
GRAYBEAL JACKSON LLP
400 - 108TH AVENUE NE, SUITE 700
BELLEVUE
WA
98004
US
|
Assignee: |
STMicroelectronics Pvt..
Ltd.
Uttar Pradesh
IN
|
Family ID: |
11097128 |
Appl. No.: |
12/795467 |
Filed: |
June 7, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10285329 |
Oct 30, 2002 |
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12795467 |
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Current U.S.
Class: |
375/359 |
Current CPC
Class: |
H03L 7/181 20130101;
H04N 21/4305 20130101; H03L 7/0992 20130101 |
Class at
Publication: |
375/359 |
International
Class: |
H04L 7/02 20060101
H04L007/02 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 30, 2001 |
IN |
1084/DEL/2001 |
Claims
1. (canceled)
2. A digitally implemented clock recovery apparatus for clock
recovery from a data stream containing embedded reference clock
values, the apparatus comprising: a clock reference register
operable to store clock reference values received from the incoming
data stream; a digital comparator operable to compare the stored
clock reference values and a locally generated clock reference
values, and to provide a control value in response; and a
controlled clock source operable to provide a locally generated
clock signal synchronized with the clock reference values in
response to the control value, wherein the controlled clock source
includes a controllable digital fractional divider operable to
receive the control value and a clock input from a digital clock
synthesizer.
3. The apparatus of claim 2, wherein the digital clock synthesizer
is driven by a fixed oscillator.
4. The apparatus of claim 2, further including a local clock
reference register operable to store the locally generated clock
reference values.
5. The apparatus of claim 2, further including a counter operable
to receive the locally generated clock signal and provide the
locally generated clock reference values.
6. The apparatus of claim 2, wherein the gain of the comparator is
adjusted in accordance with changing input conditions.
7. The apparatus of claim 6, wherein the gain of the comparator is
adjusted to a high value prior to obtaining a match between the
controlled clock source and the clock reference and reduced after
obtaining the match.
8. The apparatus of claim 2, wherein the data stream comprises an
MPEG data stream.
9-14. (canceled)
14. An improved apparatus for clock recovery from data streams
containing embedded reference clock values comprising: clock
reference storage means for storing clock reference values received
from the incoming data stream connected to, input of a digital
comparator means, the second input of which is connected to, local
clock (LC) storage means for storing locally generated clock values
provided by a, a counter which receives a clock signal from a
controllable digital fractional divider controlled by the output of
said digital comparator, wherein said controllable digital
fractional divider receives a control value from said digital
comparator and a clock input from a digital clock synthesizer means
driven by a fixed oscillator.
15. An improved apparatus as claimed in claim 14, wherein said
input data stream is an MPEG data stream in which said embedded
clock reference value is either the program clock reference (PCR)
value or elementary stream clock reference (ESCR) value.
16. An improved apparatus as claimed in claim 14, wherein said
digital comparator means is implemented using a
microcontroller.
17.-25. (canceled)
Description
PRIORITY
[0001] This application claims priority from Indian Application for
Patent No. 1084/Del/2001, filed Oct. 30, 2001, and entitled
IMPROVED CLOCK RECOVERY FROM DATA STREAMS CONTAINING EMBEDDED
REFERENCE CLOCK VALUES, which is incorporated herein by
reference.
TECHNICAL FIELD
[0002] This invention relates to a method and an improved apparatus
for clock recovery from data streams containing embedded reference
clock values that uses purely digital techniques and can be
incorporated without major changes in most existing applications
such as MPEG based systems such as set-top boxes or DVD
systems.
BACKGROUND OF THE INVENTION
[0003] Many applications involving streaming data, such as
streaming video containing embedded reference-clock information to
enable clock synchronization at the receiver. An important example
of such data streams are Motion Picture Expert Group (MPEG) data
streams that provide an efficient format for transmitting,
receiving and storing video signals in digital format--the MPEG
data stream format includes a timing reference field called Program
Clock Reference (PCR) or Elementary Stream Clock Reference (ESCR)
that is embedded during the encoding process and serves to provide
a clock synchronizing source. The PCR/ESCR field is extracted
during the receive or playback process and is used to synchronize
the receiving clock with the data stream rate thereby implementing
clock recovery. The synchronizing or clock recovery function is
implemented by a Digital Phase Locked Lop (DPLL).
[0004] FIG. 1 shows a typical DPLL used in an MPEG receiver
application. The MPEG encoding is performed using a reference 27
MHz clock. To facilitate the clock recovery process at the decoder,
the MPEG streams are periodically (typically every 0.1 sec)
embedded with a timing reference field called Program Clock
Reference (PCR). The PCR is generated as follows.
[0005] The 27 MHz system clock is given to a counter. A snapshot of
the counter is taken periodically (rate at which the PCR has to be
sent). The values of the counter thus obtained are stuffed into the
PCR field of the MPEG stream.
[0006] On the decoding side, the clock is recovered using the
values in the PCR field.
[0007] The PCR in the MPEG stream is extracted and is stored in the
received PCR register (1.1). The Local PCR register (1.2) stores
the values of the PCR generated by the VOXO (1.6). The contents of
the counter (1.4) are loaded into local PCR register, and the MPEG
stream with the PCR field updates the contents of received PCR
register (1.1). The comparator (1.3) outputs an error signal
depending on the difference between received PCR (1.1) and the
local PCR (1.2). The error signal is used to drive a controlled
clock source (1.7). Within the controlled clock source (1.7) the
error signal is converted into analog voltage by the D/A converter
(1.5). The analog output voltage from D/A converter (1.5) biases
the VOXO (1.6) to generate the required frequency. The actual
implementation may have some blocks being implemented in software.
For example, the compare function can be easily implemented in the
software. The D/A block may consist of a PWM generator that is
programmed by the software and a low pass filter.
[0008] U.S. Pat. No. 5,473,385 describes a DPLL apparatus in which
a subtractor gives the difference between received and locally
generated PCR values. The output of the subtractor, which is the
error value, is fed to a digital filter connected to the input of
an accumulator. The accumulated error values are processed by an
error signal generator, which produces a frequency adjustment
signal for advancing or retarding the local oscillator frequency
after gating with a selected video synchronization signal so that
the clock frequency correction is performed only during the
vertical synch or blanking interval and the effects of the
synchronization are not visible. This technique does not permit
easy modification of the characteristics of the PLL as there are no
programmable features. Also, the dropping of clocks during the
vertical synch incurs a significant risk in obtaining jitter-free
reading of data. Finally, the implementation of this method
requires major redesign of MPEG decoder circuits used in existing
systems such as set-top boxes.
[0009] U.S. Pat. No. 6,072,369 uses a phase error detector,
interpolator, gain calculator, digital-to-analog converter (DAC),
voltage controlled oscillator (VCO) divider, and local PCR (LPCR)
counter to generate the local clock signal. This scheme is
implemented purely in hardware and uses analog components such as
the DAC and VCO. It is therefore sensitive to noise and its
characteristics are not easily modifiable.
[0010] U.S. Pat. No. 6,175,385 describes three purely digital
schemes that essentially use a fixed frequency oscillator. Clock
synchronization is achieved by counting clock pulses of the fixed
frequency signal and adjusting the unit for incrementing or
decrementing the counted value to a predetermined value in a
predetermined time according to the deviation of the fixed
frequency from the reference frequency. The scheme requires a
redesign of almost all the blocks used to process MPEG information
in the majority of existing applications. Further, this process
needs to be implemented during the video-blanking interval and
hence is limited to applications where such an interval is
available.
SUMMARY
[0011] An embodiment of the invention eliminates or reduces the
severity of some of the above drawbacks by providing a completely
digital implementation of the clock-recovery systems.
[0012] Another embodiment of the invention provides dynamically
configurable loop-filter characteristics.
[0013] A further embodiment of the invention provides such an
implementation where no major re design of the existing video
information processing blocks is required.
[0014] Therefore, one embodiment of invention provides an improved
apparatus for clock recovery from data streams containing embedded
reference clock values comprising: [0015] clock reference storage
means for storing clock reference values received from the incoming
data stream connected to, input of a digital comparator means, the
second input of which is connected to, [0016] local clock (LC)
storage means for storing locally generated clock values provided
by a, [0017] counter means which receives a clock signal from a
controlled clock source means controlled by the output of said
digital comparator means, [0018] characterized in that said
controlled clock source means includes a controllable digital
Fractional Divider means receiving a control value from said
digital comparator means and a clock input from a digital clock
synthesizer means driven by a fixed oscillator means.
[0019] For example:
[0020] The input data stream is an MPEG data stream in which said
embedded clock reference value is either the Program Clock
Reference (PCR) value or Elementary Stream Clock Reference (ESCR)
value.
[0021] The comparator means is implemented using a
microcontroller.
[0022] The Digital Fractional Divider is any known Digital
Fractional Divider.
[0023] The said Digital Fractional Divider is implemented as
claimed in our co-pending application, U.S. application No.
[attorney reference number 2110-17-3], filed Oct. 10, 2002.
[0024] The gain of said comparator means is adjusted in accordance
with changing input conditions.
[0025] The gain of said comparator is adjusted to a high value
prior to obtaining a match between said local clock and said clock
reference and reduced after obtaining said match.
[0026] Another embodiment of the invention is a method for enabling
clock recovery from data streams containing embedded reference
clock values, comprising the steps of: [0027] storing the received
reference clock values, [0028] generating a controlled local clock,
[0029] comparing said received reference clock with said generated
local clock; [0030] adjusting said controlled local clock to match
said received reference clock; [0031] characterized in that said
controlled local clock is generated by performing controlled
fractional division on the output from a fixed clock source.
[0032] The above method may also include adjusting of the loop gain
in accordance with changing input conditions, such as the loop gain
is adjusted to a high value prior to lock-in and to a lower value
after lock-in.
BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Embodiments of the invention will now be described with
reference to the accompanying drawings:
[0034] FIG. 1 shows a DPLL used in MPEG receiver application
according to known art;
[0035] FIG. 2 shows a circuit diagram for a preferred embodiment of
the invention; and
[0036] FIG. 3 shows the fractional divider (2.6) of FIG. 2 and its
functioning, in accordance with an embodiment of the invention.
DETAILED DESCRIPTION
[0037] In the following detailed description of exemplary
embodiments of the invention, reference is made to the accompanying
drawings, which form a part hereof. The detailed description and
the drawings illustrate specific exemplary embodiments by which the
invention may be practiced. These embodiments are described in
sufficient detail to enable those skilled in the art to practice
the invention. It is understood that other embodiments may be
utilized, and other changes may be made, without departing from the
spirit or scope of the present invention. The following detailed
description is therefore not to be taken in a limiting sense, and
the scope of the present invention is defined by the appended
claims. In some instances, well known methods, procedures,
components, and circuits have not been described in detail so as
not to obscure the present invention.
[0038] FIG. 1 is described in the Background.
[0039] FIG. 2 shows a preferred embodiment of the invention. The
PCR/ESCR from the data stream is extracted and stored in the PCR
register (2.1). The LPCR register (2.2) stores the values of the
PCR generated by the controlled clock source (2.5). On receiving a
data stream with PCR/ESCR field, the PCR register (2.1) and LPCR
register (2.2) are updated by loading into them the contents of
PCR/ESCR field and the counter (2.4) respectively. The comparator
(2.3) is a logic circuit, which preferably includes a
microcontroller for programmatically adjusting the loop gain in
accordance with changing input conditions. In one embodiment, the
loop gain is adjusted to a high value prior to obtaining a match
between said local clock and said clock reference, and is reduced
after obtaining said match. In another embodiment, the comparator
(2.3) may be implemented with logic hardware.
[0040] The comparator (2.3) outputs a digital error signal
depending upon the difference between PCR register (2.1) and LPCR
register (2.2), which act as its inputs. The error signal may have
both an integer part and a fractional part. The comparator logic
circuit generates the error signal in a manner so as to minimize
the difference between the received program clock reference (PCR)
and the locally generated PCR (LPCR), thereby providing
synchronization and enabling clock recovery. By doing so, the
circuit as a whole functions as a digital phase locked loop.
[0041] The fractional divider (2.6) is responsible for the clock
recovery scheme. The fractional divider could be any known
fractional divider. A preferred embodiment of the fractional
divider is shown in FIG. 3 and is described in co-pending U.S.
patent application No. [attorney reference number 2110-17-3]
entitled "An Improved Fractional Divider", filed Oct. 10, 2002,
which is incorporated herein by reference. The fractional divider
(2.6) receives the digital error signal comprising an integer part
and a fractional part on its configuration bus from the output of
the comparator (2.3). The fractional divider (2.6) converts the
error signal to the required frequency. The fractional divider
(2.6) is clocked by a synthesizer (2.8), generating a high
frequency clock (typically 600 MHz) with the help of a reference
frequency from a crystal oscillator (2.7).
[0042] FIG. 3 shows the fractional divider (2.6) of FIG. 2, in
accordance with an embodiment of the invention. The output from the
synthesizer (2.8) of FIG. 2 is given to a counter (3.1) of the
fractional divider (2.6), as shown FIG. 3. The counter can be
configured to divide by either n or n+1 depending upon the
logic-state of the carry out.
[0043] The fractional adder (3.2) is a binary adder. The fractional
increment register (3.3) holds the fractional increment value. The
contents of the fractional increment register are added to the
current contents of the fractional adder when the clock enable is
high and there is a rising Synth clock edge.
[0044] By way of example, to get 27 MHz clock, the reference
frequency of 600 MHz from the synthesizer (2.8 of FIG. 2) has to be
divided by 22.222222. To achieve this, the counter (3.1) is
programmed as divide by 22. The fractional increment value register
(3.3) is initialized with the fractional value viz., 0.222222. The
counter (3.1) is arranged such that when it completes one
programmed count, the clock out completes one clock cycle,
simultaneously the contents of the fractional increment register
(3.3) are added to the contents of fractional adder (3.2) once
every clock out cycle. When an overflow in the fractional adder
occurs, the carry out is set to logic `1`. This configures the
counter as divide by 23. Table 1 shows the division factor and the
fractional part in the fractional adder for every 27 MHz clock
cycle generated.
TABLE-US-00001 TABLE 1 Division Fractional S. No Factor Division 1
22 0.2222222 2 22 0.4444444 3 22 0.6666666 4 22 0.8888888 5 23
0.1111111 6 22 0.3333333 7 22 0.5555556 8 22 0.7777778 9 23 0.0
[0045] The ratio of frequencies is 27:600=9:200. That implies the
phases will match after 9 clocks of 27 MHz and 200 clocks of 600
MHz. The first column represents the number of clock cycles of the
27 MHz clock, the contents of the second column when added is 200,
which is equal to the number of 600 MHz clocks. The division by a
factor `n` or `n+1` is implemented by a programmable divider. The
`Fractional Adder is a 24-bit binary adder. The addition operation
in the `Fractional Adder` unit is performed when `Adder Enable` is
high and on a rising Synth clock edge. The `Adder Enable` is high
for only one Synth clock cycle. The `Carry Out` signal is high only
when there is a carry from the addition. The division logic is
configured to divide by `n` when carry out signal is low. It is
configured to divide by `n+1` when carry out signal is high.
[0046] This embodiment also relates to a method for enabling clock
recovery from data streams (2.9) containing embedded reference
clock values wherein a locally generated clock (2.10) is adjusted
to match with the received embedded reference clock value, the
adjustable local clock being generated by controlled fractional
division (2.6) of the output of a fixed clock source.
* * * * *