U.S. patent application number 12/816628 was filed with the patent office on 2010-09-30 for test structure and probe for differential signals.
This patent application is currently assigned to Cascade Microtech, Inc.. Invention is credited to Richard Campbell.
Application Number | 20100244874 12/816628 |
Document ID | / |
Family ID | 38821249 |
Filed Date | 2010-09-30 |
United States Patent
Application |
20100244874 |
Kind Code |
A1 |
Campbell; Richard |
September 30, 2010 |
TEST STRUCTURE AND PROBE FOR DIFFERENTIAL SIGNALS
Abstract
A test structure including a differential gain cell and a
differential signal probe include compensation for the Miller
effect reducing the frequency dependent variability of the input
impedance of the test structure.
Inventors: |
Campbell; Richard;
(Portland, OR) |
Correspondence
Address: |
CHERNOFF, VILHAUER, MCCLUNG & STENZEL, LLP
601 SW Second Avenue, Suite 1600
PORTLAND
OR
97204-3157
US
|
Assignee: |
Cascade Microtech, Inc.
Beaverton
OR
|
Family ID: |
38821249 |
Appl. No.: |
12/816628 |
Filed: |
June 16, 2010 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
12157658 |
Jun 11, 2008 |
7750652 |
|
|
12816628 |
|
|
|
|
11710149 |
Feb 22, 2007 |
7403028 |
|
|
12157658 |
|
|
|
|
60813120 |
Jun 12, 2006 |
|
|
|
Current U.S.
Class: |
324/750.14 |
Current CPC
Class: |
G01R 31/2889
20130101 |
Class at
Publication: |
324/755 |
International
Class: |
G01R 31/02 20060101
G01R031/02 |
Claims
1. A test structure comprising a cell including a first input
signal probe pad capacitively interconnected to a first output
signal probe pad and a second input signal probe pad capacitively
interconnected to a second output signal probe pad, said test
structure comprising: (a) a first capacitor interconnecting said
first input signal probe pad and said second output signal probe
pad; and (b) a second capacitor interconnecting said second input
signal probe pad and said first output signal probe pad, wherein
said first capacitor has a capacitance related to a capacitance of
said interconnection of said first input signal probe pad and said
first output signal probe pad and said second capacitor has a
capacitance related to a capacitance of said interconnection of
said second input signal probe pad and said second output signal
probe pad.
2. The test structure of claim 1 wherein said first capacitor has a
capacitance substantially equal to a capacitance of said
interconnection of said first input signal probe pad and said first
output signal probe pad and said second capacitor has a capacitance
substantially equal to a capacitance of said interconnection of
said second input signal probe pad and said second output signal
probe pad.
3. A probe for probing a cell comprising a first input signal probe
pad capacitively interconnected to a first output signal probe pad
and a second input signal probe pad capacitively interconnect to a
second output signal probe pad, said probe comprising: (a) a first
probe tip connectible to a source of a first input signal and
arranged for contact with said first input signal probe pad of said
cell; (b) a second probe tip connectible to a source of a second
input signal and arranged for contact with said second input signal
probe pad; (c) a third probe tip connectible to a sink of a first
output signal and arranged for contact with said first output
signal probe pad; (d) a fourth probe tip connectible to a sink of a
second output signal and arranged to contact said second output
signal probe pad; (e) a first capacitive structure interconnecting
said first probe tip and said fourth probe tip; and (f) a second
capacitive structure interconnecting said second probe tip and said
third probe tip.
4. The probe of claim 3 wherein said first, said second, said third
and said fourth probe tips are arranged in a linear array.
5. The probe of claim 3 wherein said capacitive structure
interconnecting said first probe tip and said fourth probe tip has
a capacitance substantially equal to a capacitance of said
interconnection of said first input signal probe pad and said first
output signal probe pad and said capacitive structure
interconnecting said second probe tip and said third probe tip has
a capacitance substantially equal to a capacitance of said
interconnection of said second input signal probe pad and said
second output signal probe pad.
6. The probe of claim 5 wherein said first, said second, said third
and said fourth probe tips are arranged in a linear array.
7. A method for probing a cell comprising a first input signal
probe pad capacitively interconnected to a first output signal
probe pad and a second input signal probe pad capacitively
interconnected to a second output signal probe pad, said method
comprising steps of: (a) interconnecting said first input signal
probe pad and said second output signal probe pad with a capacitor
approximately equaling a capacitance of said interconnection of
said first input signal probe pad and said first output signal
probe pad; and (b) interconnecting said second input signal probe
pad and said first output probe pad with a capacitor approximately
equaling a capacitance of said interconnection of said second input
signal probe pad and said second output signal probe pad.
8. A test structure for testing a functionality of a transistor,
said test structure comprising: (a) a first transistor including:
(i) a first terminal connectible through a first resistance to a
source of a first component of a signal; (ii) a second terminal
connectible through a second resistance to a sink for a first
component of an output signal and interconnected to said first
terminal by a parasitic capacitance; and (iii) a third terminal;
(b) a second transistor including: (i) a first terminal connectible
through a third resistance to a source of a second component of a
signal; (ii) a second terminal connectible through a fourth
resistance to a sink for a second component of an output signal and
interconnected to said first terminal by a parasitic capacitance;
and (iii) a third terminal interconnected with said third terminal
of said first transistor and a source of a bias voltage; (c) a
first compensating capacitive structure connecting said first
terminal of said first transistor to said second terminal of said
second transistor; and (d) a second compensating capacitive
structure connecting said first terminal of said second transistor
to said second terminal of said first transistor.
9. The test structure of claim 8 wherein said first compensating
capacitive structure has a capacitance substantially equal to said
parasitic capacitance interconnecting said first terminal of said
first transistor and said second terminal of said first transistor
and said second compensating capacitive structure has a capacitance
substantially equal to said parasitic capacitance interconnecting
said first terminal of said second transistor to said second
terminal of said second transistor.
10. The test structure of claim 8 wherein said first, said second,
said third and said fourth resistances have values selected to
cause said test structure to have a gain approximating unity.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent
application Ser. No. 12/157,658, filed Jun. 11, 2008, which is a
continuation of U.S. patent application Ser. No. 11/710,149, filed
Feb. 22, 2007, which claims the benefit of U.S. Provisional App.
No. 60/813,120, filed Jun. 12, 2006.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to wafer probing and, more
particularly, to probes and test structures for wafer probing with
differential signals.
[0003] Integrated circuits (ICs) are economically attractive
because large numbers of often complex circuits, for example
microprocessors, can be inexpensively fabricated on the surface of
a wafer or substrate. Following fabrication, individual dies,
including one or more circuits, are separated or singulated and
encased in a package that provides for electrical connections
between the exterior of the package and the circuit on the enclosed
die. The separation and packaging of a die comprises a significant
portion of the cost of manufacturing the integrated circuit device
and to monitor and control the IC fabrication process and avoid the
cost of packaging defective dies, manufacturers commonly add
electrical circuits or test structures to the wafer to enable
on-wafer testing or "probing" to verify the characteristics of the
integrated circuits before the dies are singulated.
[0004] A test structure typically includes a device-under-test
(DUT), a plurality of metallic probe or bond pads that are
deposited at the wafer's surface and a plurality of conductive vias
that connect the bond pads to the DUT which is typically fabricated
beneath the surface of the wafer. The DUT typically comprises a
simple circuit that includes a copy of one or more of the basic
elements of the integrated circuit, such as a single line of
conducting material, a chain of vias or a single transistor. The
circuit elements of the DUT are typically produced with the same
process and in the same layers of the die as the corresponding
elements of the integrated circuit. The ICs are typically
characterized "on-wafer" by applying a test instrument generated
signal to the test structure and measuring the response of the test
structure to the signal. Since the circuit elements of the DUT are
fabricated with the same process as the corresponding elements of
the integrated circuit, the electrical properties of the DUT are
expected to be representative of the electrical properties of the
corresponding components of the integrated circuit.
[0005] At higher frequencies, on-wafer characterization is commonly
performed with a network analyzer. The network analyzer comprises a
source of an AC signal, commonly, a radio frequency (RF) signal,
that is used to stimulate the DUT of a test structure. A
forward-reverse switch directs the stimulating signals to one or
more of the bond pads of the test structure. Directional couplers
or bridges pick off the forward or reverse waves traveling to or
from the test structure. These signals are down-converted by
intermediate frequency (IF) sections of the network analyzer where
the signals are filtered, amplified and digitized for further
processing and display. The result is a plurality of s-parameters
(scattering parameters), the ratio of a normalized power wave
comprising the response of the DUT to a normalized power wave
comprising the stimulus supplied by the signal source.
[0006] The preferred interconnection for communicating the signals
between the signal source and the receiver of the network analyzer
and the test structure is coaxial cable. The transition between the
coaxial cable and the bond pads of the test structure is preferably
provided by a movable probe having one or more conductive probe
tips that are arranged to be co-locatable with the bond pads of the
test structure. The network analyzer and the test structure can be
temporarily interconnected by bringing the probe tips into contact
with the bond pads of the test structure.
[0007] Integrated circuits typically comprise a ground plane at the
lower surface of the substrate on which the active and passive
devices of the circuit are fabricated. The terminals of transistors
fabricated on a semi-conductive substrate are typically
capacitively interconnected, through the substrate, to the ground
plane. The impedance of this parasitic capacitive interconnection
is frequency dependent and at higher frequencies the ground
potential and the true nature of ground referenced (single ended)
signals becomes uncertain.
[0008] Balanced devices are more tolerant to poor radio frequency
(RF) grounding than single ended devices making them attractive for
high performance ICs. Referring to FIG. 1, a differential gain cell
20 is a balanced device comprising two nominally identical circuit
halves 20A, 20B. When biased, with a DC current source 22, and
stimulated with a differential mode signal, comprising even and odd
mode components of equal amplitude and opposite phase
(S.sub.i.sup.+1 and S.sub.i.sup.-1) 24, 26, a virtual ground is
established at the symmetrical axis 28 of the two circuit halves.
At the virtual ground, the potential at the operating frequency
does not change with time regardless of the amplitude of the
stimulating signal. The quality of the virtual ground of a balanced
device is independent of the physical ground path and, therefore,
balanced or differential circuits can tolerate poor RF grounding
better than circuits operated with single ended signals. The two
waveforms of the differential output signal (So.sup.+1 and
So.sup.-1) 30, 32 are mutual references providing greater certainty
in determining the transition from one binary value to the other
and permitting a reduction the voltage swing of the signal and
faster transition between binary values. Typically, differential
devices can operate at lower signal power and higher data rates
than single ended devices. In addition, noise from external
sources, such as adjacent conductors, tends to couple, electrically
and electromagnetically, in the common mode and cancel in the
differential mode. As a result, balanced or differential circuits
have good immunity to noise including noise at even-harmonic
frequencies since signals that are of opposite phase at the
fundamental frequency are in phase at the even harmonics. Improved
tolerance to poor RF grounding, increased resistance to noise and
reduced signal power make differential devices attractive for
operation at higher frequencies.
[0009] A DUT comprising a differential gain cell provides a basis
for a test structure enabling high frequency, on-wafer evaluation
of devices included in the marketable integrated circuits
fabricated on the wafer. However, the impedance of the internal
connections of the DUT's components are often frequency dependant
complicating de-embedding of the DUT and affecting the accuracy of
the testing. For example, the input and output of a differential
gain cell, such as the differential gain cell 20, are commonly
capacitively interconnected as a result of parasitic capacitance
connecting the terminals of the cell's transistors. Parasitic
capacitance 42 between the gate 38, 40 and the drain 34, 36, a
result of diffusion of the drain dopant under the oxide of the
gate, is intrinsic and typical of MOS transistors. As a result to
the transistor's gain, a change in the gate voltage produces an
even larger change in the voltage at the transistor's drain. The
application of differing voltages at the terminals of the parasitic
gate-to-drain capacitor (C.sub.gd) causes the capacitor to behave
as a much larger capacitance, a phenomenon known as the Miller
effect. As a result, input impedance of the differential device
varies substantially with frequency, producing instability in the
operation of the differential device.
[0010] What is desired is a method and apparatus for testing a
differential device that minimizes or eliminates the Miller
effect.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is schematic diagram of a balanced device.
[0012] FIG. 2 is a schematic illustration of a probe and a
differential test structure comprising field effect transistors and
a pair of Miller effect neutralizing capacitors.
[0013] FIG. 3 is a schematic illustration of a probe and a
differential test structure comprising bipolar junction (BJT)
transistors and a pair of Miller effect neutralizing
capacitors.
[0014] FIG. 4 is a perspective view of a test structure and a
probe.
[0015] FIG. 5 is a schematic illustration of a differential test
structure for go-no go testing of the functionality of a
transistor.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0016] Referring in detail to the drawings where similar parts are
identified by like reference numerals, and, more particularly to
FIG. 1, a differential gain cell 20 is a balanced device comprising
two nominally identical circuit halves 20A, 20B. When biased, with
a DC current source 22, and stimulated with a differential mode
signal, comprising even and odd mode components of equal amplitude
and opposite phase (S.sub.i.sup.+1 and S.sub.i.sup.-1) 24, 26, a
virtual ground is established at the symmetrical axis 28 of the two
circuit halves. At the virtual ground, the potential at the
operating frequency does not change with time regardless of the
amplitude of the stimulating signal. The quality of the virtual
ground of a balanced device is independent of the physical ground
path and, therefore, balanced or differential circuits can tolerate
poor RF grounding better than circuits operated with single ended
(ground referenced) signals. Differential devices can also
typically operate with lower signal power and at higher data rates
than single ended devices and have good immunity to noise from
external sources, such as adjacent conductors, including noise at
even-harmonic frequencies.
[0017] However, the response of integrated circuits, including test
structures comprising differential gain cells, to high frequency
signals is typically frequency dependent. Integrated circuits are
fabricated by depositing layers of semi-conductive and insulating
materials on a semi-conductive substrate and intrinsic frequency
dependent connections commonly exist between the various elements
of the fabricated devices. One such intrinsic frequency dependent
connection connects the gates and drains of MOS transistors and the
bases and collectors of bipolar junction (BJT) transistors. For
example, an intrinsic parasitic capacitance (C.sub.gd)
interconnects the gate and the drain of a typical MOS transistor
because the drain dopant diffuses under the oxide comprising the
transistor's gate. As the frequency of the stimulating signal
increases, the impedance between gate and drain of the transistor
and, therefore, the input impedance of the differential gain cell
changes. Moreover, due to the gain of the transistor, any change in
voltage at the gate of the transistor is amplified at the drain of
the transistor causing the parasitic capacitance (C.sub.gd) to
appear to be a much larger capacitor; a phenomenon known as the
Miller effect. The inventors realized that the signals conducted by
the respective transistors of the differential gain cell are mirror
images and concluded that the Miller effect could be minimized or
eliminated and the input impedance of a test structure comprising a
differential gain cell stabilized connecting the gate of one
transistor to the drain of the second transistor with a capacitor
having a value equal to the parasitic gate-to-drain capacitance
(C.sub.gd).
[0018] Referring to FIG. 2, a test structure 50 comprises a
differential gain cell 51 including transistors 52A, 52B. The gates
of the respective transistors are connected to probe pads 54, 56
Probe tips 64, 66 arranged to be co-locatable with the probe pads
are connected to a source 74 of a differential input signal
comprising the component signal, S.sub.1.sup.+1' and its
differential complement signal, The source of the differential
signal is typically a radio frequency (RF) source included in a
network analyzer 76. The network analyzer also includes a sink 78
for the output signal of the test structure comprising components
S.sub.o.sup.+1 and S.sub.o.sup.-1. The respective components of the
output signal are transmitted from the drains of the transistors to
probe pads 58, 60 which are connectible to the signal sink through
probe tips 68, 70. The sources of the transistors are
interconnected and connected to a bias probe pad 62 which is
engageable with a probe tip 72. The probe tip is interconnected to
a DC current source 80 that provides the bias for the differential
gain cell.
[0019] Intrinsic in each transistor 52A, 52B is parasitic
capacitance (C.sub.gd) 82A, 82B interconnecting the respective
gates and drains which comprise respectively the input terminals
and the output terminals of the test structure. As a result of the
gain (A) of the transistor, a change in voltage (dV) at the gate of
a transistor is amplified at the drain (A*dV) causing the opposing
sides of the parasitic capacitance to experience differing voltage.
As a result of a phenomenon known as the Miller effect, the
parasitic capacitance (C.sub.gd) has the effect of a larger
capacitor causing the input impedance of the test structure to vary
substantially with frequency. To reduce or eliminate the effect of
the parasitic gate-to-drain capacitance and provide a more constant
input impedance for the test structure, a compensating capacitor
84A, 84B is connected from the gate of each transistor, for example
the gate of transistor 52A, to the drain of the second transistor
of the differential gain cell, for example the drain of transistor
52B. The compensating capacitor has a value equal to the value of
C.sub.gd. Since the transistors of the differential gain cell are
matched and the phase of the differential input signal component
S.sub.i.sup.+1 is 180.degree. from the phase of the differential
output signal component S.sub.o.sup.-1, the change in voltage at
the drain of a transistor due to the gate-to-drain capacitance, for
example, A*dV, is offset by the voltage at the compensating
capacitor #(-A*dV) and the input impedance of the test structure
remains constant.
[0020] Referring to FIG. 3, another exemplary embodiment of a test
structure 100 comprises a differential gain cell 102 comprising
bipolar junction (BJT) transistors 104A, 104B connected in a common
emitter configuration. The bases of the transistors are connected
to probe pads 106, 108 that are engageable by probe tips 106, 108
interconnected to a source 126 of a differential signal comprising
the component input signals (S.sub.i.sup.+1 and S.sub.i.sup.-1).
The collectors of the transistors are connected to probe pads 110,
112 which are engageable by probe tips 120, 122 which are
interconnected to a sink 128 for the output signal of the
differential cell comprising the component signals (S.sub.o.sup.+1
and S.sub.o.sup.-1). The emitters of the matched transistors are
interconnected and connected through a probe tip 124, contactable
with a bias probe pad 114, to a DC current source 130 that biases
the differential gain cell. Each BJT includes parasitic
base-to-collector capacitance (C.sub.bc) 132 that comprises a
frequency dependent interconnection between an input and an output
of the test structure. To counter the Miller effect, a compensating
capacitor 134 having a value equal to C.sub.bc interconnects the
gate of each of the transistors 104A, 104B respectively to the
collector of the other transistor of the differential gain
cell.
[0021] The compensating capacitors may be fabricated on the wafer
as part of the test structure enabling consistent matching to the
parasitic capacitance of the transistors. On the other hand, the
compensating capacitors may be connected across the respective
probe tips arranged to engage the appropriate probe pads.
Typically, differential probing is performed with two probes.
Referring to FIG. 4, the differential test structure 200 comprises
at least four bond or probe pads, including probe pads 202, 204 for
the input signal components and probe pads 206, 208 for the output
signal components that are arranged in a linear array and connected
to the DUT 212, which is fabricated below the surface of a wafer
214, by a plurality of conductive vias 216. The fifth probe pad
210, through which the DUT is biased, is preferably fabricated
within the linear array but could be offset. Arrangement of the
probe pads in a linear array enables fabrication of the test
structure in a saw street 218 (indicated by bracket) between dies
220 permitting a reduction in the area of the wafer that is
occupied by test structures which serve no purpose after the dies
are singulated. The linear arrangement of probe pads also enables
probing with a single probe comprising a linear array of at least
four probe tips 222, 224, 226, 228 which may be fabricated on the
surfaces of a dielectric plate 232 and which are arranged to be
co-locatable with the probe pads for the input and output signals.
The fifth probe tip 230, through which the DUT is biased, is
preferably fabricated in the linear array probe tips but could be
offset or arranged at a different angle to the wafer. The linear
arrangement of probe tips facilitates fabrication of conductors 234
and compensating capacitors 236 interconnecting the probe tips 222,
224 transmitting the input signals and the probe tips 226, 228
transmitting the output signals for the two transistors of the
differential gain cell of the DUT.
[0022] During the fabrication of integrated circuits (ICs) it is
desirable to be able to easily determine if transistors included in
the integrated circuits are functional. Referring to FIG. 4, an
easily tested go-no go test structure 150 comprising a differential
gain cell 152 having circuit elements fabricated with the same
process and in the same layers of the wafer as their counterpart
elements of the marketable integrated circuits. The test structure
comprises compensating capacitors 156 connecting the gate of each
transistor 154A, 1548 to the drain of its counterpart, respectively
1548, 154A, to neutralize the Miller effect originating with the
parasitic gate-to-drain capacitance (C.sub.gd) and stabilize the
input impedance of the test structure. A resistor network
comprising resistors 178 connect the signal input probe tips 168,
170, arranged to engage the input probe pads 158, 160, and the
signal source 74. Likewise, the signal output probe pads 162, 164
are connected to the signal sink 78 through probe tips 172, 174 and
resistors 182, 184. The test structure is biased through the probe
pad 166 and the probe tip 176 which is connected to ground through
the bias resistor 186. The resistors at all terminations stabilize
the DC operation of the amplifier and prevent it from oscillating
by reducing the Q factor of resonances produced by the capacitive
and inductive interconnections of the device parasitics. The values
of the resistors are selected to provide stability and a convenient
level of gain, preferably, approximately unity. Data is collected
by testing a plurality transistor pairs known to be good. Comparing
this data to data obtained by testing on-wafer test structures
provides a go-no go gauge of transistor functionality that can be
easily used during the production process.
[0023] The input impedance of a test structure comprising a
differential gain cell is stabilized by interconnecting the gate of
one transistor and the drain of the second transistor of the
differential pair with a capacitor having a value approximating the
parasitic gate-to-drain (base-to-collector) capacitance of the
device.
[0024] The detailed description, above, sets forth numerous
specific details to provide a thorough understanding of the present
invention. However, those skilled in the art will appreciate that
the present invention may be practiced without these specific
details. In other instances, well known methods, procedures,
components, and circuitry have not been described in detail to
avoid obscuring the present invention.
[0025] All the references cited herein are incorporated by
reference.
[0026] The terms and expressions that have been employed in the
foregoing specification are used as terms of description and not of
limitation, and there is no intention, in the use of such terms and
expressions, of excluding equivalents of the features shown and
described or portions thereof, it being recognized that the scope
of the invention is defined and limited only by the claims that
follow.
* * * * *