U.S. patent application number 12/771386 was filed with the patent office on 2010-08-26 for methods for passivating metallic interconnects.
Invention is credited to Uri Cohen.
Application Number | 20100213614 12/771386 |
Document ID | / |
Family ID | 37393348 |
Filed Date | 2010-08-26 |
United States Patent
Application |
20100213614 |
Kind Code |
A1 |
Cohen; Uri |
August 26, 2010 |
Methods for Passivating Metallic Interconnects
Abstract
One or more embodiments of the present invention relates to a
method for passivating metallic interconnects, said method
including: forming a metallic conductor embedded in at least one
surrounding dielectric layer, said metallic conductor including a
metal or alloy chosen from a group consisting of Cu, Ag, and alloys
including one or more of these metals, said metallic conductor and
said at least one surrounding dielectric layer having top surfaces;
and forming a capping passivation film directly on the top surface
of the metallic conductor, but not over the top surface of the at
least one surrounding dielectric layer, wherein said capping
passivation film including one or more materials selected from the
group consisting of copper sulfide, silver sulfide, copper
selenide, silver selenide, copper telluride, and silver telluride,
wherein the copper sulfide refers to CuS.sub.X or Cu.sub.2S.sub.X,
the silver sulfide refers to AgS.sub.X or Ag.sub.2S.sub.X, the
copper selenide refers to CuSe.sub.Xor Cu.sub.2Se.sub.X, and the
copper telluride refers to CuTe.sub.X or Cu.sub.2Te.sub.X, and
wherein 0.7.ltoreq.X.ltoreq.1.3.
Inventors: |
Cohen; Uri; (Palo Alto,
CA) |
Correspondence
Address: |
Uri Cohen
4147 Dake Avenue
Palo Alto
CA
94306
US
|
Family ID: |
37393348 |
Appl. No.: |
12/771386 |
Filed: |
April 30, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11156122 |
Jun 17, 2005 |
7709958 |
|
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12771386 |
|
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60581285 |
Jun 18, 2004 |
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Current U.S.
Class: |
257/762 ;
257/E21.59; 257/E23.161; 438/642 |
Current CPC
Class: |
H01L 21/76846 20130101;
H01L 2224/11001 20130101; H01L 2221/1089 20130101; H01L 21/76843
20130101; H01L 21/76834 20130101; H01L 21/76873 20130101; H01L
21/76867 20130101; H01L 21/76849 20130101 |
Class at
Publication: |
257/762 ;
438/642; 257/E23.161; 257/E21.59 |
International
Class: |
H01L 23/532 20060101
H01L023/532; H01L 21/768 20060101 H01L021/768 |
Claims
1. A method for passivating metallic interconnects, said method
comprising: forming a metallic conductor embedded in at least one
surrounding dielectric layer, said metallic conductor comprising a
metal or alloy chosen from a group consisting of Cu, Ag, and alloys
comprising one or more of these metals, said metallic conductor and
said at least one surrounding dielectric layer having top surfaces;
and forming a capping passivation film directly on the top surface
of the metallic conductor, but not over the top surface of the at
least one surrounding dielectric layer, wherein said capping
passivation film comprising one or more materials selected from the
group consisting of copper sulfide, silver sulfide, copper
selenide, silver selenide, copper telluride, and silver telluride,
wherein the copper sulfide refers to CuS.sub.X or Cu.sub.2S.sub.X,
the silver sulfide refers to AgS.sub.X or Ag.sub.2S.sub.X, the
copper selenide refers to CuSe.sub.X or Cu.sub.2Se.sub.X, and the
copper telluride refers to CuTe.sub.X or Cu.sub.2Te.sub.X, and
wherein 0.7.ltoreq.X.ltoreq.1.3.
2. The method of claim 1 further comprising depositing a capping
dielectric barrier layer over the capping passivation film.
3. The method of claim 2 wherein the capping passivation film has a
thickness in a range from about 10 .ANG. to about 100 .ANG..
4. The method of claim 2 wherein the capping passivation film has a
thickness in a range from about 30 .ANG. to about 200 .ANG..
5. The method of claim 2 wherein the capping passivation film has a
thickness in a range from about 10 .ANG. to about 50 .ANG..
6. The method of claim 2 wherein the capping dielectric diffusion
barrier layer comprises one or more materials selected from a group
consisting of silicon nitride, silicon carbide, silicon carbide
nitride, silicon carbide nitride oxide, silicon nitride oxide,
SiC.sub.XH.sub.Y, and SiC.sub.XO.sub.YH.sub.Z.
7. The method of claim 2 wherein the capping passivation film is
formed in a plasma enhanced chemical vapor deposition (PECVD)
chamber.
8. The method of claim 7 wherein the PECVD chamber is the same
chamber used for depositing the capping dielectric barrier
layer.
9. The method of claim 2 wherein the capping passivation film
comprises copper sulfide.
10. The method of claim 9 wherein the capping passivation film has
a thickness in a range from about 10 .ANG. to about 100 .ANG..
11. The method of claim 9 wherein the capping passivation film has
a thickness in a range from about 30 .ANG. to about 200 .ANG..
12. The method of claim 9 wherein the capping passivation film has
a thickness in a range from about 10 .ANG. to about 50 .ANG..
13. The method of claim 9 wherein the capping dielectric diffusion
barrier layer comprises one or more materials selected from a group
consisting of silicon nitride, silicon carbide, silicon carbide
nitride, silicon carbide nitride oxide, silicon nitride oxide,
SiC.sub.XH.sub.Y, and SiC.sub.XO.sub.YH.sub.Z.
14. The method of claim 9 wherein the capping passivation film is
formed in a plasma enhanced chemical vapor deposition (PECVD)
chamber.
15. The method of claim 14 wherein the PECVD chamber is the same
chamber used for depositing the capping dielectric barrier
layer.
16. The method of claim 14 wherein a sulfur-bearing reactant is
utilized for sulfidation of the top surface of the metallic
conductor.
17. The method of claim 16 wherein the sulfur-bearing reactant is
selected from a group consisting of H.sub.2S gas, H.sub.2S gas
mixture, and sublimed sulfur vapor.
18. The method of claim 9 wherein the capping passivation film is
formed by reacting the top surface of the metallic conductor with a
wet solution containing one or more sulfur-bearing compounds.
19. The method of claim 18 wherein the wet solution comprises one
or more of dissolved elemental sulfur (S.sub.n), sulfide ions
(S.sup.-2), and dissolved H.sub.2S.
20. The method of claim 2 wherein the capping passivation film is
formed by reacting the top surface of the metallic conductor with a
wet solution containing one or more sulfur-bearing compounds.
21. A semiconductor device comprising a metallic interconnect
passivated by the method of claim 2.
22. A semiconductor device comprising a metallic interconnect
passivated by the method of claim 14.
Description
[0001] This is a Continuation of application Ser. No. 11/156,122,
filed on Jun. 17, 2005, now U.S. Pat. 7,709,958, which claims the
benefit of U.S. Provisional Application No. 60/581,285, filed on
Jun. 18, 2004, which application is incorporated herein by
reference.
Technical Field of the Invention
[0002] One or more embodiments of the present invention relates to
the field of Very Large Scale Integration (VLSI) and Ultra Large
Scale Integration (ULSI) semiconductor devices, Thin Film Head
(TFH) devices, Micro Electronic Machined Systems (MEMS), and high
density electronic device packaging such as, for example and
without limitation, Flip Chip, Chip Scale Packaging (CSP), and
Wafer Scale Packaging (WSP).
BACKGROUND OF THE INVENTION
[0003] In fabricating Damascene and Dual Damascene (DD) copper
interconnects in accordance with prior art techniques, copper is
encased in one or more copper diffusion barrier layers. Typically,
the bilayer Ta/TaN.sub.X is used as a barrier layer for sidewalls
and at the bottom of lines, and a relatively high-k dielectric
layer, typically silicon nitride (or silicon carbide, or silicon
carbide nitride, or silicon oxide carbide nitride), is used as a
top capping barrier layer.
[0004] Sites of poor adhesion between copper and metallic barrier
layers on sidewalls and/or at the bottom of openings may result in
electromigration (EM) and/or Stress Induced Voids (SIV). Copper EM
and SIV are important reasons for poor reliability and low yields
in copper interconnects. Presently used sidewalls and bottom
barrier layers, such as Ta, TaN.sub.X, Ta/TaN.sub.X, Ru,
TaSi.sub.XN.sub.Y, WN.sub.X, Ti/TiN.sub.X, TiSi.sub.XN.sub.Y, or
WSi.sub.XN.sub.Y, are problematic because: (a) their relatively
high resistivity increases the resistance of interconnect lines and
vias--this is particularly problematic at the bottom of vias; (b)
they may have poor adhesion to copper and/or to the dielectric
surrounding the interconnect (inter layer dielectric or ILD),
resulting in high EM and/or SIV; and (c) they are often
discontinuously deposited by a PVD technique over sidewalls of high
aspect ratio (HAR) Damascene and Dual Damascene vias and trenches
(particularly on hard to reach lower sidewalls of HAR openings, and
on negative slope vicinities of undercut crevices, nooks, and
crannies)--which discontinuities provide easy diffusion routes for
copper into surrounding dielectric and/or copper voids.
[0005] In light of the above, there is a need for methods and
materials that solve one or more of the above-identified
problems.
SUMMARY OF THE INVENTION
[0006] One or more embodiments of the present invention solve one
or more of the above-identified problems. In particular, one or
more embodiments of the present invention relate to methods for
passivating metallic interconnects, said method including: forming
a metallic conductor embedded in at least one surrounding
dielectric layer, said metallic conductor including a metal or
alloy chosen from a group consisting of Cu, Ag, and alloys
including one or more of these metals, said metallic conductor and
said at least one surrounding dielectric layer having top surfaces;
and forming a capping passivation film directly on the top surface
of the metallic conductor, but not over the top surface of the at
least one surrounding dielectric layer, wherein said capping
passivation film including one or more materials selected from the
group consisting of copper sulfide, silver sulfide, copper
selenide, silver selenide, copper telluride, and silver telluride,
wherein the copper sulfide refers to CuS.sub.X or Cu.sub.2S.sub.X,
the silver sulfide refers to AgS.sub.X or Ag.sub.2S.sub.X, the
copper selenide refers to CuSe.sub.X or Cu.sub.2Se.sub.X, and the
copper telluride refers to CuTe.sub.X or Cu.sub.2Te.sub.X, and
wherein 0.7.ltoreq.X.ltoreq.1.3.
BRIEF DESCRIPTION OF THE FIGURES
[0007] FIGS. 1(a)-1(b) show a pictorial representation of a
transverse (along the width) cross-section of an interconnect
structure used to fabricate, for example and without limitation, a
semiconductor device that includes a conductor structure fabricated
in accordance with one or more embodiments of the present
invention;
[0008] FIGS. 2(a)-2(b) show a pictorial representation of a
transverse (along the width) cross-section of an opening with its
sidewalls covered with a conformal passivation and/or diffusion
barrier film in accordance with one or more embodiments of the
present invention;
[0009] FIGS. 3(a)-3(b) show a pictorial representation of a
transverse (along the width) cross-section of an embedded (or
filled) conductive interconnect with its sidewalls covered with a
conformal passivation and/or diffusion barrier film, and its top
surface covered with a passivation capping film in accordance with
one or more embodiments of the present invention; and
[0010] FIGS. 4(a)-4(b) show a pictorial representation of a
longitudinal (along the length) cross-section of an embedded (or
filled) Dual Damascene conductive interconnect where the
interconnect is encased by a passivation and/or diffusion barrier
film on its sidewalls and bottom surfaces, and its top surface is
covered with a passivation capping film in accordance with one or
more embodiments of the present invention.
DETAILED DESCRIPTION
Top Capping
[0011] FIG. 1(a) shows a pictorial representation of a transverse
(along the width) cross-section (not to scale for ease of
understanding) of structure 100 used to fabricate, for example and
without limitation, a semiconductor device that includes a
conductor structure comprised of conductive interconnect 18.
Conductive interconnect 18 may comprise a metal or metal alloy such
as, for example and without limitation, Cu, Ag, or alloys
comprising one or more of these metals. Structure 100 may be
fabricated as follows. In accordance with any one of a number of
methods that are well known to those of ordinary skill in the art,
dielectric layer 11 may be deposited over substrate 10, which
substrate 10 may comprise one or more layers such as, for example
and without limitation, a lower metallization level and/or another
dielectric layer. Next, in accordance with any one of a number of
methods that are well known to those of ordinary skill in the art,
an opening having sidewall surfaces 15 and bottom surface 17 may be
pattern-etched in dielectric layer 11, and barrier layer 16 and one
or more seed layers (not shown in FIG. 1) may be deposited over
sidewalls 15 and bottom surface 17 of the opening. Barrier 16 may
comprise, for example and without limitation, a refractory metal or
an alloy comprising a refractory metal, such as Ta, TaN.sub.X,
Ta/TaN.sub.X, Ru, TaSi.sub.XN.sub.Y, WN.sub.X, Ti/TiN.sub.X,
TiSi.sub.XN.sub.Y, or WSi.sub.XN.sub.Y. One or more seed layers
(not shown) are then deposited over the metallic barrier layer 16.
Next, in accordance with any one of a number of methods that are
well known to those of ordinary skill in the art, for example and
without limitation, using electrofilling methods, the opening may
be filled with conductive interconnect 18. Next, in accordance with
any one of a number of methods that are well known to those of
ordinary skill in the art, for example and without limitation,
using one or more planarization and/or removal techniques, such as
chemical mechanical polishing (CMP), polishing,
electro-dissolution, electropolishing, or chemical etching, excess
conductor in conductor 18 and excess conductor over dielectric 11
in field 14, as well as any seed and barrier layers overlying field
14, may be removed to expose a top surface of conductor
interconnect metal 18 and a top surface of field 14. This step is
sometimes referred to in the art as a removal or planarization
step.
[0012] In accordance with one or more embodiments of the present
invention, following the removal or planarization step, the exposed
top surface of conductor interconnect 18 is covered with
passivation film 12. In accordance with one or more embodiments of
the present invention, the step of covering the exposed top surface
of conductor interconnect 18 with passivation film 12 comprises
providing passivation film 12 over the exposed top surface of
conductive metal 18 by, for example and without limitation, an
intermixing growth process or a deposition process.
[0013] The term "intermixing growth" process is defined herein as a
process in which a film grows on a surface of a material, which
film comprises one or more constituents of the material and one or
more constituents of a reactant. One example, without limitation,
of an intermixing growth process involves diffusion across a
growing film of one or more constituents from the material to the
surface of the growing film, and/or diffusion across the growing
film of one or more constituents from the reactant to the interface
between the material and the growing film. For example and without
limitation, silicon dioxide growth by oxidation of a silicon
surface (such as described in a book entitled "VLSI Fabrication
Principles" by S. K. Ghandhi, pp. 377-383, John Wiley & Sons,
Inc. (1983)) is an intermixing growth process. The term
"deposition" is defined herein as any process in which all of the
constituents of a film originate from reagents external to the
surface of a material. Some examples, without limitation, of
deposition processes are electrodeposition, electroless deposition,
chemical bath deposition (CBD), physical vapor deposition (PVD),
chemical vapor deposition (CVD), and atomic layer deposition
(ALD).
[0014] A. Intermixing Growth
[0015] In accordance with one or more embodiments of the present
invention, passivation film 12 may be fabricated by reacting the
exposed top surface of conductor interconnect 18 with one or more
reactants to fabricate one or more materials that adhere strongly
to the exposed conductor 18 surface. In accordance with one or more
such embodiments, it is believed that strong adhesion is provided
because at least one of such materials is chemically bonded to the
material at the exposed top surface of conductor interconnect 18.
Advantageously, in accordance with one or more of such embodiments,
it is believed that passivation film 12 grows selectively, i.e., it
grows only on exposed surface of conductor interconnect 18, and not
on dielectric 11 at the exposed surface of field 14.
[0016] In accordance with one or more embodiments of the present
invention, conductor interconnect 18 comprises copper or a copper
alloy, and passivation film 12 comprises a copper sulfide such as
CuS.sub.X and/or Cu.sub.2S.sub.X (where 0.7.ltoreq.X.ltoreq.1.3;
and X=1.0 for stoichiometric compounds), and/or other materials
comprising one or more of these compounds. Copper sulfide film 12
can be grown by an intermixing growth process, for example and
without limitation, by sulfidation of (or reacting) the exposed top
surface of copper interconnect 18 with a sulfur-bearing reactant
gas (or gas mixture) comprising sulfur atoms, molecules, or ions
such as, for example and without limitation, H.sub.2S or vapors of
elemental sulfur (S.sub.n; where n is an integer). It is believed
that in accordance with such embodiments, copper sulfide film 12 is
grown by an intermixing growth process according to the following
chemical reactions:
XH.sub.2S+CuCuS.sub.X+XH.sub.2; or XS.sub.n+nCunCuS.sub.X
XH.sub.2S+2CuCu.sub.2S.sub.X+XH.sub.2; or
XS.sub.n+2nCunCu.sub.2S.sub.X
[0017] The rate of growth of film 12 can be increased or decreased
by raising or lowering, respectively, the temperature of structure
100 and/or the reactant gas. The growth rate can also be increased
or decreased by increasing or decreasing, respectively, the
concentration (or partial pressure) of the reactant gas.
[0018] For example and without limitation, copper sulfide film 12,
having a thickness of about 10 .ANG. to about 2,000 .ANG., can be
grown by an intermixing sulfidation process on the top surface of
copper conductor 18 by subjecting a wafer with exposed conductor 18
to an H.sub.2S gas (or a gas mixture of H.sub.2S with inert gas,
such as argon or nitrogen), or to a sublimed sulfur vapor, at a
temperature from about 25.degree. C. to about 500.degree. C. The
dry sulfidation can be performed in a furnace, such as a rapid
thermal processing (RTP) furnace, a CVD chamber, or a plasma
enhanced CVD (PECVD) chamber at sulfidation times ranging from a
few seconds to about 10 minutes. The higher the substrate
temperature and/or the longer the exposure time, the thicker the
copper sulfide film 12, and vice versa.
[0019] Copper sulfide film 12 may also be grown by an intermixing
growth process in accordance with one or more further embodiments
of the present invention by reacting the exposed top surface of
copper interconnect 18 with a wet solution which contains one or
more sulfur-bearing compounds comprising sulfur atoms, molecules,
or ions, such as, for example and without limitation, solutions
comprising elemental sulfur (S.sub.n) or sulfide ions (S.sup.-2) of
Na.sub.2S, K.sub.2S, (NH.sub.4).sub.2S, and dissolved H.sub.2S. It
is believed that in accordance with such embodiments, copper
sulfide film 12 is grown by an intermixing growth process according
to the following chemical reactions:
XS.sup.-2+2XH.sub.2O+CuCuS.sub.X+2XOH.sup.-+XH.sub.2;
or XS.sub.n+nCunCuS.sub.X
XS.sup.-2+2XH.sub.2O+2CuCu.sub.2S.sub.X+2XOH.sup.-+XH.sub.2;
or XS.sub.n+2nCunCu.sub.2S.sub.X
[0020] In accordance with one or more of such embodiments, dipping
or spraying the top surface of copper interconnect 18 in the wet
solution is continued until a predetermined thickness of film 12 is
approached or attained (as will be described below, it is believed
that the predetermined thickness may be a self-limited thickness).
The rate of growth of film 12 can be increased or decreased by
raising or lowering, respectively, the temperature of the wet
solution and/or structure 100. The growth rate of film 12 can also
be increased or decreased by increasing or decreasing,
respectively, the concentration of the sulfur-bearing reactant in
the solution.
[0021] It may be advantageous to grow film 12 by an intermixing
self-limiting growth process, to its self-limited thickness at a
temperature higher (for example and without limitation, by at least
50.degree. C., and more specifically, by at least 100.degree. C.)
than the operational temperatures attained during device operation.
It is believed that this will help to reduce copper diffusion
across film 12 during operation of the device, or it might even
substantially prevent such copper diffusion. In such a case,
passivation film 12 can also function (and be used) as a diffusion
barrier layer, in addition to its passivation role (by immobilizing
top surface atoms of conductor 18). However, as is well-known, the
actual growth temperature might be limited by a thermal budget, or
by other processing and/or integration considerations, and a
trade-off might be required. In light of this information,
appropriate values of temperature can be determined for a
particular application by one of ordinary skill in the art
routinely and without undue experimentation. "Self-limited
thickness" is defined herein as the thickness attained after a
certain growth time, .DELTA.t (at a specific growth temperature),
which increases by less than about 25% when the growth time is
extended by another .DELTA.t, or more. For example, if the
thickness of film 12 is about 200 .ANG. after 5 minutes growth at a
given temperature, and it is less than about 250 .ANG. after
additional 5 minutes growth at the same temperature, then the
self-limited thickness of film 12 is about 200 .ANG.. The
self-limited thickness is a strong function of the growth
temperature, increasing with the growth temperature. It is believed
that the thickness of passivation film 12 has to be larger than
about 300 .ANG. and, probably larger than about 500 .ANG., for it
to function as an efficient diffusion barrier. Using film 12 alone
as a diffusion barrier (see FIG. 1(a)), without dielectric barrier
layer 19, would have the distinct advantages of significantly
reducing the effective dielectric constant (k.sub.eff) of the
multilevel interconnect, while improving its reliability,
structural strength, and integrity.
[0022] In General, the Cu.sub.2S.sub.X phases are thermally more
stable than the CuS.sub.X phases. For example, the Cu.sub.2S.sub.X
.delta.-phase has a maximum melting point of 1,131.degree. C.,
whereas the CuS.sub.X .epsilon.-phase is not stable above
507.degree. C., and undergoes phase transformations at 76.degree.
C. and at 115.degree. C. See Metals Handbook, 8.sup.th Edition,
Vol. 8, pages 297, 300, 358, American Society for Metals, 1973. A
reference herein to a Cu.sub.2S.sub.X phase may also include the
case of more than a single phase and, similarly, a reference herein
to a single CuS.sub.X phase may also include the case of more than
a single phase. It is believed that when film 12 comprises the
Cu.sub.2S.sub.X phase, it is more stable and, therefore, may be
more desirable. As a result, if film 12 is formed (by intermixing
growth) by reacting a sulfur-bearing reactant gas or vapor on
copper conductor 18, at temperatures above about 507.degree. C.,
only the Cu.sub.2S.sub.X phase is formed. Similarly, if film 12 is
first formed as the phase CuS.sub.X (alone or in a multiple phase
structure) and, if the film is subsequently heated (or annealed) to
above about 507.degree. C., then film 12 will convert to the
Cu.sub.2S.sub.X phase.
[0023] However, depending on the thickness of film 12 and
subsequent heating (or annealing), film 12 may convert entirely
into the Cu.sub.2S.sub.X phase at even lower temperatures than
about 500.degree. C. For example, it is believed that a relatively
thin (about 30 .ANG. to about 200 .ANG.) copper sulfide(s) film 12
will convert entirely into the Cu.sub.2S.sub.X phase by annealing
it for a relatively short time (about 0.5 minute to about 10
minutes) at a temperature between about 100.degree. C. to about
400.degree. C. and, more specifically, between about 150.degree. C.
to about 300.degree. C. It is believed that film 12 converts to the
Cu.sub.2S.sub.X phase by reacting with excess copper on the
conductor 18 side, while there is no fresh supply of sulfur species
on the other side of film 12. Thicker film 12 may require longer
annealing time and/or higher annealing temperature to fully convert
into the Cu.sub.2S.sub.X phase. Subsequent annealing of film 12 can
be performed as a separate dedicated processing step, or during
another elevated temperature processing step such as, for example
and without limitation, during deposition of dielectric barrier 19
in FIG. 1(b), for example, by a CVD or a PECVD process. For
example, it is believed that when the thickness of film 12 is in a
range of about 30 .ANG. to about 200 .ANG., the processing
temperature during a subsequent CVD or plasma enhanced CVD (PECVD)
deposition step (for example and without limitation, of a silicon
nitride or a silicon carbide barrier layer 19) is sufficiently high
and is present for a long enough time to fully convert any other
phase(s) of film 12 into the Cu.sub.2S.sub.X phase.
[0024] In accordance with one or more still further embodiments of
the present invention, film 12 grown by an intermixing growth
process on copper interconnect 18 comprises one or more of
CuSe.sub.X, Cu.sub.2Se.sub.X, CuTe.sub.X, Cu.sub.2Te.sub.X (where
0.7.ltoreq.X.ltoreq.1.3; and X=1.0 for stoichiometric
compounds)--where copper selenide refers to CuSe.sub.X and/or
Cu.sub.2Se.sub.X and copper telluride refers to CuTe.sub.X and/or
Cu.sub.2Te.sub.X. In still further embodiments, film 12 comprises
one or more of CuS.sub.X, Cu.sub.2S.sub.X, CuSe.sub.X,
Cu.sub.2Se.sub.X, CuTe.sub.X, Cu.sub.2Te.sub.X (where
0.7.ltoreq.X.ltoreq.1.3; and X=1.0 for stoichiometric compounds),
and other materials comprising one or more of these compounds.
[0025] Copper selenide can be grown by an intermixing growth
process by reacting the exposed top surface of copper interconnect
18 with a wet reactant, or a dry reactant gas (or gas mixture) or
vapor of one or more selenium-bearing compounds comprising selenium
atoms, molecules, or ions. Copper telluride can be grown by an
intermixing growth process by reacting the exposed top surface of
copper interconnect 18 with a wet reactant, or a dry reactant gas
(or gas mixture) or vapor of one or more tellurium-bearing
compounds comprising tellurium atoms, molecules, or ions. For
example, in order to grow copper selenide by an intermixing growth
process on the copper surface, the copper surface may be reacted
with (for example and without limitation) H.sub.2Se, Na.sub.2Se,
K.sub.2Se, or (NH.sub.4).sub.2Se. Similarly, in order to grow
copper telluride by an intermixing growth process on the copper
surface, the copper surface may be reacted with (for example and
without limitation) H.sub.2Te, Na.sub.2Te, K.sub.2Te, or
(NH.sub.4).sub.2Te.
[0026] It is believed that one or more of the above-described
embodiments for growing film 12 by an intermixing growth process is
a self-limiting process. In particular, it is believed that the
process is self-limiting by copper and/or sulfur (or sellenium or
tellurium) diffusion through (or across) the film as it grows. In
particular, it is believed that as the thickness of the growing
film increases, the flux of copper species that travel from copper
interconnect 18 through film 12 and/or the flux of sulfur (or
sellenium or tellurium) species that travel from the surface
through film 12 slows down until it or they become substantially
negligible or insignificant. In particular, it is believed that a
self-limited thickness of film 12 depends on temperature, the
density of the film, and its morphology. For example, if the growth
temperature is higher, the limiting thickness will be greater
(assuming sufficient growth time of the film to its self-limited
thickness), and the film will form faster. However, it is also
believed that, if the density of the film is so low that there are
high rates of diffusion, or if the film contains voids and/or many
defects, the process may not be self-limiting. It is further
believed that the process is confined to a self-limiting process by
enabling diffusion to take place fast enough (during film
formation) to growth sites to avoid forming voids. This may be done
by raising the growth temperature to ensure that the diffusing
species can reach their proper growth sites without forming voids.
In light of this information, appropriate values of temperature and
reactant concentration or amounts can be determined for a
particular application by one of ordinary skill in the art
routinely and without undue experimentation.
[0027] It should be understood that in some semiconductor
processes, the use of compounds containing alkali metal ions might
be problematic due to the possibility of contamination. In such
cases, for example and without limitation, ammonium sulfide or
dissolved H.sub.2S may be used to avoid such alkali metal
contamination. Other chemical reagents which comprise sulfur such
as, for example and without limitation, elemental sulfur (S),
SO.sub.2, sulfites, thioacetamide, thiourea, or thiosulfates may
also be used to form film 12. As such, one or more embodiments of
the present invention include the use of any chemical reagent
suitable for reaction with the exposed top surface of conductor 18
to form passivation film 12 comprising a copper sulfide.
[0028] Advantageously, film 12 formed as described above is grown
on top of conductor interconnect 18, and does not grow on top field
14 of the surrounding dielectric layer 11. As such, growth of
passivation film 12 by an intermixing growth process provides a
selective process which advantageously helps avoid current leakage
through dielectric layer 14. It is further believed that the
passivating reactant can advantageously passivate any exposed
copper residue (contamination) left on (or embedded onto) field 14
of surrounding dielectric 11 by a previous CMP step. This is
advantageous because it may further reduce leakage currents between
interconnect lines. In addition, and advantageously in accordance
with one or more embodiments of the present invention related to
copper interconnect, it is believed that passivation film 12 is
chemically bonded to the copper conductor 18 underneath it, thereby
adhering well to the top surface of copper (or copper alloy)
conductor interconnect 18. As such, it is believed that film 12 can
reduce or eliminate copper interfacial surface diffusion and,
thereby, reduce or eliminate electromigration (EM).
[0029] Copper sulfide passivation film 12 described above is
further advantageous because it also adheres well to dielectric
layers such as, for example and without limitation, dielectric
layers that overlay in structures used to fabricate devices such as
semiconductor devices, thereby improving the mechanical strength
and the structural integrity of multi-level metallization devices.
Furthermore, since copper sulfide film 12 is not a dielectric
material (actually it is conductive, having a resistivity .rho.
value in a range of about 10.sup.-4 to about 10.sup.-2 ohm-cm), it
does not increase the effective dielectric constant (k.sub.eff) of
structures 100 or 110. In accordance with one or more embodiments,
the thickness of passivation film (or layer) 12 may be in a range
from about 10 .ANG. to about 500 .ANG. and, more specifically, in a
range from about 50 .ANG. to about 200 .ANG..
[0030] B. Deposition
[0031] In accordance with one or more embodiments of the present
invention, film 12 may be deposited upon the exposed top surface of
conductor interconnect 18. Such a deposition may be carried out by
a: (a) dry deposition process such as, for example and without
limitation, atomic layer deposition (ALD) or chemical vapor
deposition (CVD); (b) physical vapor deposition (PVD) process such
as, for example and without limitation, sputtering or evaporation;
or (c) wet deposition process such as, for example and without
limitation, chemical bath deposition, electrodeposition, or
electroless deposition. Except for electroless deposition and
electrodeposition, the other deposition processes mentioned above
are not selective. For example, using such other deposition
processes, copper sulfide will be deposited over the top surface of
copper interconnect 18 and the top surface of surrounding
dielectric 11 on field 14. As such, the use of non-selective
deposition processes may require additional steps for removing
copper sulfide deposited over the top surface of dielectric 11 in
field 14. In accordance with one or more such embodiments, it is
believed that strong adhesion is provided because at least one of
such materials is chemically bonded to material at the exposed top
surface conductor interconnect 18. In addition, and advantageously
in accordance with one or more embodiments of the present
invention, because film 12 is chemically bonded to copper
underneath it, film 12 adheres well to the top surface of copper
interconnect 18. As such, it is believed that film 12 can reduce or
eliminate copper surface diffusion, and thereby reduce or eliminate
electromigration (EM). It is believed that chemical bonding is
enhanced if the temperature of the substrate is elevated during
deposition and/or during successive processing steps entailed in
fabricating a device.
[0032] In accordance with one or more embodiments of the present
invention, it is believed that copper atoms at the surface of
copper interconnect 18 are chemically bound, for example and
without limitation, in a chalcogenide compound comprised of one or
more constituents that have a high affinity for copper. In
accordance with one or more such embodiments, film 12 may be
utilized to passivate the top surface of conductor interconnect 18.
In accordance with one or more such embodiments, the thickness of
passivation film layer 12 may be in a range from about 10 .ANG. to
about 500 .ANG., and more specifically in a range from about 50
.ANG. to about 200 .ANG.. In addition, film 12 may reduce the
effective dielectric constant k.sub.eff of a multi-level
interconnect structure by reducing the required thickness of (or
entirely eliminating) the relatively high-k silicon nitride (or
other high-k) dielectric capping layer. Although the description
above referred mostly to copper metal (Cu) interconnect and copper
sulfide (CuS.sub.X and/or Cu.sub.2S.sub.X, where
0.7.ltoreq.X.ltoreq.1.3; and X=1.0 for stoichiometric compounds)
films, it should be understood by those skilled in the art that one
or more embodiments of the present invention also may be utilized
with interconnects comprising any highly conductive metal or alloy,
such as, for example and without limitation, silver metal (Ag) or
alloys which comprise one or more of the metals Cu and Ag.
Similarly, it should be understood that one or more embodiments of
the present invention also include films which comprise silver
sulfide (AgS.sub.X and/or Ag.sub.2S.sub.X, where
0.7.ltoreq.X.ltoreq.1.3; and X=1.0 for stoichiometric compounds)
and/or mixtures of other sulfide compounds comprising one or more
atoms selected from the group consisting of Cu and Ag. In addition,
it should be understood that one or more embodiments of the present
invention also include films which comprise copper selenides and/or
tellurides, silver selenides and/or tellurides, and mixtures
thereof (consisting of one or more of copper and/or silver
sulfides, selenides, and tellurides).
[0033] Copper sulfide passivation film 12 described above with
respect to intermixing growth and deposition processes is further
advantageous because it also adheres well to dielectric layers such
as, for example and without limitation, dielectric layers that
overlay in structures used to fabricate devices such as
semiconductor devices, thereby improving the mechanical strength
and the structural integrity of multi-level metallization devices.
Furthermore, since copper sulfide film 12 is not a dielectric
material (actually it is conductive, having a resistivity .rho.
value in a range of about 10.sup.-4 to about 10.sup.-2 ohm-cm), it
does not increase the effective dielectric constant (k.sub.eff) of
structures 100 or 110. In accordance with one or more embodiments,
the thickness of passivation film (or layer) 12 may be in a range
from about 10 .ANG. to about 500 .ANG. and, more specifically, in a
range from about 50 .ANG. to about 200 .ANG..
[0034] C. Capping Passivation Plus Capping Dielectric Barrier
[0035] FIG. 1(b) shows a pictorial representation of a transverse
(along the width) cross-section (not to scale for ease of
understanding) of structure 110 used to fabricate, for example and
without limitation, a semiconductor device that includes structure
100 shown in FIG. 1(a) and a dielectric layer 19 that overlays
structure 100. In accordance with one or more embodiments of the
present invention, dielectric barrier layer 19 may be utilized as
an etch-stop layer (ESL) during etching of successive vias and/or
trenches for a higher metallization level. Dielectric barrier layer
19 may also serve as an additional capping diffusion barrier
against copper outdiffusion. Dielectric barrier layer 19 may
comprise, for example and without limitation, silicon nitride,
silicon carbide, silicon carbide nitride, silicon carbide nitride
oxide, silicon nitride oxide, SiC.sub.XH.sub.Y, or
SiC.sub.XO.sub.YH.sub.Z. Dielectric barrier layer 19 may be
deposited using any one of a number of deposition processes that
are well known to those skilled in the art, for example and without
limitation, by a chemical vapor deposition (CVD) or by a plasma
enhanced CVD (PECVD), at a temperature range of about
400-500.degree. C., or less. As described above, passivation film
12 adheres well to dielectric layers, and as such, film 12 adheres
well to dielectric layer 19. As such, passivation film 12 may
significantly improve the strength and structural integrity of
multi-level metallization devices.
[0036] It is believed that conventional interfaces between copper
lines and the capping dielectric barrier (such as silicon nitride
or silicon carbide) effectively generate micro-crack precursors
which, under thermal and/or mechanical stress, may propagate into
the surrounding (mechanically weak) dielectric, thus adversely
affecting the structural integrity. It is further believed that,
many of the current mechanical strength and structural integration
problems associated with low-k dielectrics in advanced interconnect
structures (such as CMP delamination and packaging problems), are
related to such interfacial micro-cracks precursors. Thus,
interposing a copper chalcogenide film, such as a copper sulfide
film 12, between the copper lines 18 and the capping dielectric
barrier layer 19, with strong adhesion to both, can effectively
mitigate or eliminate the deleterious interfacial micro-crack
precursors, thereby improving the mechanical strength and
structural integrity of the device.
[0037] D. Further Processing
[0038] When higher levels interconnects are used (not shown),
successive vias (not shown) connecting conductor 18 to an upper
level metallization interconnect are formed. In order to minimize
the successive vias resistance, it may be desirable and/or
advantageous to remove passivation film 12 from under the bottom of
the successive vias (not shown), prior to copper or silver filling,
by a short etching step. In accordance with one or more embodiments
of the present invention, passivation film 12 can be selectively
removed from under the bottom of successive vias by an etching step
such as, for example and without limitation, using a directional
dry etching technique such as sputter etching, ion milling, or
reactive ion etching (RIE) through the successive vias. Film 12 may
also be selectively removed from under the bottom of the vias by
wet chemical etching through the successive vias, utilizing, for
example and without limitation, HNO.sub.3 and/or H.sub.2SO.sub.4.
Where dielectric barrier layer 19 is formed over film 12, the
etching of film 12 can be integrated into the removal (etching)
step of layer 19 from the successive vias' bottom, usually by a RIE
technique. The chemistry used for etching the dielectric barrier
layer 19 may also be utilized for the RIE etching of film 12.
Alternatively, film 12 may be removed by a separate subsequent
step, utilizing ion milling, or by a different RIE gas chemistry,
suitable for the removal of film 12.
[0039] Structures comprising successive vias disposed over film 12
and/or dielectric barrier 19, with film 12 and/or dielectric
barrier 19 selectively removed from the successive vias' bottom,
ensure minimal vias resistance by direct metallic contact to the
preceding (i.e., lower) copper metallization level 18.
Sidewalls and Bottom Encasing
[0040] FIG. 2(a) shows a pictorial representation of a transverse
(along the width) cross-section (not to scale for ease of
understanding) of structure 200 used to fabricate, for example and
without limitation, a metallic interconnect in a semiconductor
device, wherein opening 13 has sidewalls surfaces 15 and bottom
surface 17 covered with metallic barrier layer 16. Metallic barrier
layer 16 is covered in turn, with film 22 in accordance with one or
more embodiments of the present invention. Opening 13 of structure
200 may subsequently be filled, for example and without limitation,
using electroplating (or electrofilling) methods. Structure 200 may
be fabricated as follows. In accordance with any one of a number of
methods that are well known to those of ordinary skill in the art,
dielectric layer 11 may be deposited over substrate 10, which
substrate 10 may comprise one or more layers such as, for example
and without limitation, a lower metallization level and/or another
dielectric layer. Next, in accordance with any one of a number of
methods that are well known to those of ordinary skill in the art,
opening 13 having sidewalls surfaces 15 and bottom surface 17 may
be pattern-etched in dielectric layer 11, and barrier layer 16 may
be deposited over sidewalls 15 and bottom surface 17 of opening 13.
Metallic barrier layer 16 may comprise, for example and without
limitation, at least one layer of one or more refractory metals or
alloys comprising refractory metals, such as Ta, TaN.sub.X, binary
Ta/TaN.sub.X, Ru, TaSi.sub.XN.sub.Y, WN.sub.X, binary Ti/TiN.sub.X,
TiSi.sub.XN.sub.Y, or WSi.sub.XN.sub.Y. Next, film 22 is grown by
an intermixing growth process or by a deposition process over
metallic barrier layer 16 in accordance with one or more
embodiments of the present invention. Next, one or more seed layers
24 are deposited over film 22 in accordance with any one of a
number of methods that are well known to those of ordinary skill in
the art. Although FIGS. 2(a) and 2(b) show a single seed layer 24,
it is within the scope of the invention that layer 24 may also
comprise two or more layers, deposited in two or more steps, such
as, for example and without limitation, where one step produces a
relatively thick seed layer which may be non-conformal (or
discontinuous), and another step produces a relatively thin
conformal (i.e., continuous on the bottom 17 and sidewalls 15) seed
layer.
[0041] In accordance with one or more embodiments of the present
invention, a relatively thin conductive continuous (or conformal)
Ru layer (such as deposited by PVD, ALD, or CVD techniques) serves
as a barrier layer and/or as a seed layer, followed by a thicker
PVD seed layer 24 (comprising Cu, Ag, or an alloy comprising one or
more of these metals). The Ru layer can be used as a single barrier
layer 16 or, preferably, in a combination (not shown) with one or
more other metallic barrier layers (such as Ta, TaN.sub.X or
bilayer Ta/TaN.sub.X). While the conformal conductive Ru seed layer
ensures continuous sidewalls and bottom coverage, the thicker PVD
seed layer provides sufficient field surface conduction, required
for void-free electrofilling and for adequate plating uniformity
across a wafer. The interposed Ru layer provides good adhesion to
both the refractory metal barrier 16 on one side and to Cu on the
other side, thus serving as a "glue", enhancing strong adhesion
between the two. When Ru layer is used as a single barrier layer
16, it also provides good adhesion to dielectric 11. In such
embodiments, the Ru layer can be used in combinations with, or
without, film 22.
[0042] As defined herein, "conformal" means "continuous", and
"substantially conformal" means "substantially continuous" coverage
of a layer on at least the sidewalls (preferably also on the
bottom) of the openings.
[0043] In accordance with one or more preferred embodiments of the
present invention, layer or film 22 comprises one or more of
CuS.sub.X, Cu.sub.2S.sub.X, CuSe.sub.X, Cu.sub.2Se.sub.X,
CuTe.sub.X, Cu.sub.2Te.sub.X (where 0.7.ltoreq.X.ltoreq.1.3; and
X=1.0 for stoichiometric compounds), and other materials comprising
one or more of these compounds. In accordance with one or more
further embodiments of the present invention, film 22 may also
comprise silver sulfide (AgS.sub.X and/or Ag.sub.2S.sub.X, where
0.7.ltoreq.X.ltoreq.1.3; and X=1.0 for stoichiometric compounds)
and/or other mixtures of sulfides comprising one or more atoms
selected from the group consisting of Cu and Ag. Advantageously in
accordance with one or more embodiments of the present invention,
it is believed that because film 22 is chemically bonded to barrier
16 and to copper (or silver) seed layer 24, film 22 adheres well to
both. In accordance with one or more further embodiments of the
present invention, a conductive conformal film 22 serves as a first
seed layer, followed by a thicker PVD seed layer 24 (comprising Cu,
Ag, or an alloy comprising one or more of these metals). While the
first seed layer 22 ensures continuous sidewalls and bottom
coverage, the thicker PVD seed layer provides sufficient field
surface conduction, required for void-free electrofilling and for
adequate plating uniformity across a wafer. As such, after
electrofilling to form a copper (or silver) interconnect in opening
13, film 22 may advantageously also function as a passivation layer
on sidewalls and/or on the bottom surfaces of the interconnect to
reduce or eliminate EM and/or SIV, and to enhance adhesion between
the copper (or silver) interconnect and metallic barrier 16. Film
22 may also function as a diffusion barrier to reduce or eliminate
copper (or silver) outdiffusion into surrounding dielectric 11.
[0044] FIG. 2(b) shows a pictorial representation of a transverse
(along the width) cross-section (not to scale for ease of
understanding) of structure 210 used to fabricate, for example and
without limitation, a semiconductor device that is the same as
structure 200 shown in FIG. 2(a), except that barrier layer 16 is
not used. In accordance with one or more such embodiments of the
present invention, film 22 functions as a passivation film and/or
as a diffusion barrier to prevent or reduce copper or silver
outdiffusion, depending on the application, into dielectric 11 from
an interconnect that is subsequently formed in opening 13.
[0045] In accordance with one or more embodiments of the present
invention, film 22 in FIGS. 2(a) and 2(b) is substantially
conformal (i.e., continuous) and may be utilized to passivate the
sidewalls and bottom surfaces of an interconnect conductor that
fills opening 13. In accordance with one or more such embodiments,
the thickness of film layer 22 may be in a range from about 10
.ANG. to about 500 .ANG. and, more specifically in a range from
about 20 .ANG. to about 200 .ANG..
[0046] In accordance with one or more embodiments of the present
invention, it is believed that copper atoms at interfaces with film
22, such as seed layer 24 and/or copper-filled conductor
interconnect 18 (in FIG. 1), are chemically bound, for example and
without limitation, in a chalcogenide compound comprised of one or
more constituents that have a high affinity for copper.
[0047] A. Deposition
[0048] In accordance with one or more embodiments of the present
invention, film 22 may be deposited using a: (a) dry deposition
process such as, for example and without limitation, atomic layer
deposition (ALD) or chemical vapor deposition (CVD); (b) physical
vapor deposition (PVD) process such as, for example and without
limitation, sputtering or evaporation; or (c) wet deposition
process such as, for example and without limitation, chemical bath
deposition, electrodeposition, or electroless deposition. In
accordance with a preferred embodiment, film 22 is deposited by a
conformal deposition process, such as ALD (preferably), CVD,
electroless, or electrodeposition. For example and without
limitation, in accordance with one or more embodiments, an ALD
technique or a CVD technique may be used to deposit a conformal
CuS.sub.X or Cu.sub.2S.sub.X film 22 inside opening 13 of high
aspect ratio (HAR). Such embodiments provide a continuous film 22
over sidewalls 15, which may even comprise negative slopes, nooks,
crevices, or crannies For an example of an ALD of CuS.sub.X, see a
publication entitled "Growth of conductive copper sulfide thin
films by atomic layer deposition" by Johansson et al., in J. Mater.
Chem., Vol. 12, pp. 1022-1026 (2002). For example and without
limitation, organometallic precursors such as Cu(thd).sub.2,
Cu(hfac).sub.2, or (hfac)Cu(tmvs) can be reacted with H.sub.25 gas
in ALD or CVD processes to deposit conformal CuS.sub.X or
Cu.sub.2S.sub.X films. Due to the high affinity of refractory
metals to carbon and oxygen, a metallic barrier layer 16, which is
based on a refractory metal or alloy, tends to form interfacial
oxides and/or carbides by reacting with the organic part of the
copper organometallic precursors. Such interfacial oxides and/or
carbides may impair adhesion (and/or nucleation) of copper sulfide
film 22 to metallic barrier 16. For this reason, other copper
precursors comprising inorganic compounds which do not include
carbon and/or oxygen atoms can be used. For example and without
limitation, precursors comprising copper halides, such as copper
chlorides, copper bromides, or copper iodides may be used instead
of the copper organometallic precursors.
[0049] In accordance with one or more such embodiments, it is
believed that advantageously strong adhesion is provided because at
least one of such materials comprising film 22 (copper or silver
chalcogenide) is chemically bonded to material at the underlying
surfaces of barrier 16 and to overlying seed layer(s) 24. It is
further believed that film 22 is chemically bonded to metallic
barrier 16 underneath it by sharing chalcogenide atoms (S, Se, or
Te) with it, and to seed layer(s) 24 above it by sharing
chalcogenide atoms with film 24, thus providing excellent adhesion
to both. As such, it is believed that film 22 can reduce or
eliminate copper interfacial surface diffusion, and thereby reduce
or eliminate electromigration (EM) and/or stress induced voids
(SIV), while improving structural strength and integrity. It is
also believed that chemical bonding is enhanced if the temperature
of the substrate is elevated during deposition and/or during
successive processing steps entailed in fabricating a device. When
no barrier layer 16 is used, such as structure 210 of FIG. 2(b), it
is similarly believed that adhesion of film 22 to dielectric 11 is
promoted by sharing or substituting chalcogenide atoms or ions of
S, Se, or Te with dielectric 11.
[0050] Film 22 can be grown on barrier layer 16 (FIG. 2(a)), or
directly on dielectric 11 (FIG. 2(b)), by dry or by wet deposition
techniques. The dry deposition techniques may include ALD, CVD, or
PVD. Note that the ALD method may be particularly advantageous due
to its highly conformal nature. As such, it can coat all surfaces
continuously, including hard to reach negative slopes, crevices,
nooks and crannies For an example of a method for ALD deposition of
copper sulfide, see an article by Johansson et al. entitled "Growth
of conductive copper sulfide thin films by atomic layer deposition"
in Journal of Materials Chemistry, 2002, vol. 12, pp. 1022-1026,
incorporated herein by reference. The wet deposition techniques may
include, for example and without limitation, electroless,
electroplating, or chemical bath deposition techniques.
[0051] In one or more other embodiments, sulfur (atoms, molecules,
or ions) are first deposited directly onto, and/or "impregnated"
into, the surface of dielectric 11, and then reacted with a
copper-bearing reactant (such as aqueous solution of cuprous or
cupric ions) to form film 22 by intermixing growth. Such
embodiments might be particularly useful when using porous low-k
dielectric 11, capable of absorbing appreciable amounts of the
sulfur species.
[0052] B. Intermixing Growth
[0053] In accordance with one or more embodiments of the present
invention, layer 22 can be grown by an intermixing growth process
by first depositing a thin layer of copper or silver (such as by
ALD, CVD, electrodeposition, or electroless techniques) over
barrier layer 16, followed by an intermixing growth process like
those described above for growing film 12 of FIG. 1. Accordingly,
film 22 is grown in two steps: (a) a copper (or silver) layer (not
shown) is first deposited (by a dry or by a wet deposition
technique on metallic barrier 16 or directly on dielectric 11 (see
FIG. 2(b)) and, (b) reacting the copper (or silver) layer with a
sulfur (or sellenium or tellurium) bearing reactant to form film 22
by intermixing growth. For example, a copper layer can be deposited
on barrier 16 or directly on dielectric 11 by an ALD, CVD, PVD, or
electroless technique, followed by reacting the copper (or silver)
layer with a (wet or dry) sulfur-bearing reactant, such as H.sub.2S
or elemental sulfur.
[0054] In yet another embodiment (not shown), one or more copper
seed layer(s) 24 is first deposited over metallic barrier layer 16
(see FIG. 2(a)), and the copper seed layer (s) 24 is then reacted
with a dry or wet chalcogenide-bearing reactant to form film 22.
Partially consumed seed layer(s) 24 thus underlay film 22 (not
shown), and electrofilling of opening 13 is performed directly onto
film 22.
[0055] Advantageously, film 22 may provide improved device
integrity and reliabilty because it may act to reduce voids in
subsequently electroplated conductor that fills opening 13, when
seed layer 24 is too thin and/or when seed layer(s) 24 is
discontinuous on sidewalls 15.
[0056] Further Processing
[0057] 1. In order to minimize via resistance, it may be desirable
or advantageous to remove film 22 from bottom 17 of opening 13
(such as via in FIGS. 2(a) and 2(b)) prior to copper or silver
filling. In accordance with one or more embodiments of the present
invention, film 22 can be removed from bottom 17 of vias 13 by an
etching step such as, for example and without limitation, using a
directional dry etching technique such as sputter etching, ion
milling, or reactive ion etching (RIE). Film 22 may also be removed
from bottom 17 of via 13 by wet chemical etching such as, for
example and without limitation, using HNO.sub.3 and/or
H.sub.2SO.sub.4. Structures comprising vias with layer 22 removed
from bottom 17 are shown, for example and without limitation, in
FIG. 4. Such removal (as well as the removal of barrier layer 16
from the via's bottom) ensures minimal via resistance, by providing
copper to copper contact with a preceding (i.e., lower)
metallization level (see 10 in FIG. 4). Removal of metallic barrier
16 from the via's bottom further improves device reliability by
mitigating or eliminating EM and/or SIV problems related to the
vias' bottom.
[0058] As was discussed above in conjunction with FIGS. 2(a) and
2(b), seed layer(s) 24 is deposited over film 22 inside opening 13
and over field 14. In accordance with one or more embodiments of
the present invention, a continuous film 22 on the sidewalls 15
facilitates the use of a relatively thick seed layer 24 (which may
be discontinuous inside the opening), which can be deposited, for
example, by a PVD technique such as sputtering, ion plating, or
evaporation. The main purpose of depositing the relatively thick
seed layer 24 is to provide sufficient seed layer thickness for
adequate surface conduction over field 14. Adequate surface
conduction is required to minimize "terminal effect" (i.e., a
thickness non-uniformity across a wafer due to IR-drop from the
wafer's edge contact to its center). Adequate surface conduction is
required for good uniformity of an electroplated conductor across a
wafer and for void-free electrofilling. The thickness of seed layer
24 can be in a range from about 200 .ANG. to about 2,000 .ANG. over
field 14, and more particularly in a range from about 300 .ANG. to
about 1,000 .ANG. over field 14. As is discussed below, in
accordance with one or more embodiments of the present invention,
seed layer 24 (which may be discontinuous inside the opening) may
also be used as a (sacrificial) mask during removal of film 22
and/or metallic barrier layer 16 from a via's bottom 17.
[0059] 2. In still another embodiment, as shown in FIG. 2(b), film
22 may be formed directly (without barrier layer 16) over
dielectric 11 and over substrate 10 at bottom 17 of opening 13 and,
following its formation, a non-conformal seed layer 24 is deposited
over film 22. Then, if desired, film 22 may be removed from bottom
17 by an etching step, using non-conformal seed layer 24 as a mask
to protect layer 22 over field 14 and sidewalls 15. The etching can
be performed by wet chemical etching (for example, with HNO.sub.3
and/or H.sub.2SO.sub.4) or, more preferably, by directional
(anisotropic) dry etching such as by sputter etching, ion milling,
or reactive ion etching (RIE). Then, in order to improve conduction
of sidewalls 15, a relatively thin conformal seed layer (not shown)
may be deposited over the entire structure. The conformal seed
layer may be deposited following the step of removing film 22 from
bottom 17. The conformal seed layer may preferably be deposited by
an ALD or a CVD technique. However, it may also be deposited by any
other conformal deposition technique, such as electroless or
electrodeposition. In an alternative embodiment, a relatively thin
conformal seed layer can be deposited as part of a combined seed
layers 24 directly over film 22, followed by the deposition of a
thicker seed layer (which can be non-conformal), to form a combined
seed layer 24. This embodiment is particularly advantageous in
embodiments where there is no removal of film 22 from the bottom
17.
[0060] 3. In accordance with one or more further embodiments, film
22 may also serve as a conformal seed layer. In accordance with
further such embodiments, another seed layer, which may be
non-conformal, can be deposited thereon.
Further Structures
[0061] 1. FIG. 3(a) shows a pictorial representation of a
transverse (along the width) cross-section (not to scale for ease
of understanding) of structure 300 used to fabricate, for example
and without limitation, a conductor line in a metallic interconnect
in a semiconductor device. Structure 300 comprises an embedded or
filled conductive interconnect 18 in dielectric 11, with its
sidewalls 15 encased with film 30, and its top surface covered with
capping film 32, in accordance with one or more embodiments of the
present invention. Capping film 32 may be fabricated using any of
the above-described methods relating to film 12 of FIGS. 1(a) and
1(b). FIG. 3(a) also shows metallic barrier layer 16 formed over
sidewalls 15 and bottom 17 of the interconnect line embedded in
dielectric 11. FIG. 3(a) also shows a film or layer 30 disposed
between metallic barrier layer 16 and metallic conductor 18. Film
30 may be fabricated using any of the above-described methods
relating to film 22 of FIGS. 2(a) and 2(b). In accordance with one
or more embodiments of the invention, film (or layer) 30 passivates
the sides of conductor 18 (which conductor may comprise Cu, Ag, or
an alloy comprising one or more of these metals), and capping film
(or layer) 32 passivates the top surface of conductor 18. Structure
300 shown in FIG. 3(a) may be fabricated by starting with structure
200 shown in FIG. 2(a), electrofilling opening 13 with conductor
18, and removing by a planarization technique, such as, for
example, a CMP technique, the excess plated conductor 18 over
opening 13 (not shown), and the metallic barrier 16 and film 22
from the field 14 of dielectric 11. What was film 22 in FIG. 2(a),
will thus end up as film (or layer) 30 in FIG. 3(a). As for film 22
described above, layer 30 advantageously comprises one or more
chalcogenide materials selected from the group consisting of copper
sulfide, copper selenide, copper telluride, silver sulfide, silver
selenide, silver telluride, and mixtures of two or more of these
chalcogenides.
[0062] Advantageously, in accordance with one or more embodiments
of the present invention, it is believed that because film 30 is
chemically bonded to metallic barrier layer 16 and to copper (or
silver) conductor 18, film 30 adheres well to both. As such, film
30 may advantageously function as a passivation layer on sidewalls
15 and bottom 17 and/or as a barrier layer against copper (or
silver) outdiffusion into surrounding dielectric 11, thereby
reducing or eliminating EM and/or SIV. Similarly, it is believed
that because film 32 is chemically bonded (and adheres well) to
conductor 18, film 32 may function as a passivation capping and/or
barrier capping layer over conductor 18.
[0063] FIG. 3(b) shows a structure 310, similar to structure 300 of
FIG. 3(a), but without metallic barrier layer 16. In accordance
with one or more embodiments of the present invention, film 30
functions as a passivation layer and/or as a barrier layer against
outdiffusion of conductor 18 into dielectric 11.
[0064] 2. FIG. 4(a) shows a pictorial representation of a
longitudinal (along the length) cross-section (not to scale for
ease of understanding) of structure 400 used to fabricate, for
example and without limitation, a Dual Damascene metallic
interconnect in a semiconductor device. Structure 400 comprises an
embedded or filled conductive interconnect 18 in dielectrics 11 and
40. Conductive interconnect 18 is encased by film 42 at sidewalls
15 and (line) bottom 41, and its top surface is covered with film
44, in accordance with one or more embodiments of the present
invention. Structure 400 also comprises a metallic barrier layer 16
formed over sidewalls 15 of dielectrics 11, 40 and over line bottom
41. In accordance with one or more embodiments of the invention,
film (or layer) 42 passivates the sides of conductor 18 (which
conductor may comprise Cu, Ag, or an alloy comprising one or more
of these metals), and capping film (or layer) 44 passivates the top
surface of conductor 18. In accordance with one or more embodiments
of the invention, film 42 and/or barrier 16 are removed from bottom
17 of the via, as shown in FIG. 4(a).
[0065] In accordance with one or more embodiments of the present
invention, layers or films 42, 44 comprise one or more of
CuS.sub.X, Cu.sub.2S.sub.X, CuSe.sub.X, Cu.sub.2S.sub.X,
CuTe.sub.X, Cu.sub.2Te.sub.X (where 0.7.ltoreq.X.ltoreq.1.3; and
X=1.0 for stoichiometric compounds), and other materials comprising
one or more of these compounds. In accordance with one or more
further embodiments of the present invention, films 42, 44 may
comprise silver sulfide (AgS.sub.X and/or Ag.sub.2S.sub.X, where
0.7.ltoreq.X.ltoreq.1.3; and X=1.0 for stoichiometric compounds)
and/or other mixtures of sulfides comprising one or more atoms
selected from the group consisting of Cu and Ag. Advantageously in
accordance with one or more embodiments of the present invention,
it is believed that because film 42 is chemically bonded to
metallic barrier layer 16 and to copper (or silver) conductor 18,
film 42 adheres well to both. As such, film 42 may advantageously
function as a passivation layer on sidewalls 15 and/or a barrier
layer against copper (or silver) outdiffusion into surrounding
dielectrics 11, 40, thereby reducing or eliminating EM and/or SIV.
Similarly, it is believed that because film 44 is chemically bonded
(and adheres well) to the top of conductor 18, film 44 may function
as a passivation capping and/or barrier capping layer over
conductor 18. Film 42 can be deposited or grown by a deposition
process or by an intermixing process, similar to deposition or
growth of film 22 (in FIGS. 2(a) and 2(b)), in accordance with one
or more embodiments described above. Film 44 can be grown by an
intermixing process or deposited similar to growth or deposition of
film 12 (in FIGS. 1(a) and 1(b)), in accordance with one or more
embodiments described above.
[0066] FIG. 4(b) shows a structure 410, similar to structure 400 of
FIG. 4(a), but without metallic barrier layer 16. In accordance
with one or more embodiments of the present invention, film 42
functions as a passivation layer and/or as a barrier layer against
outdiffusion of conductor 18 into dielectrics 11 and 40.
[0067] Although the description of the embodiments and examples
above has concentrated on metallic interconnect structures used to
fabricate a device such as a semiconductor integrated circuits,
these embodiments can also be used in the fabrication of other
devices, such as (coils in) thin film heads, Micromachined
Microelectromechanical Systems (MEMS) devices, or interconnects in
high density integrated circuit packages.
[0068] Those skilled in the art will recognize that the foregoing
description has been presented for the sake of illustration and
description only. As such, it is not intended to be exhaustive or
to limit the invention to the precise form disclosed.
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