U.S. patent application number 12/629322 was filed with the patent office on 2010-08-19 for solid-state imaging device having penetration electrode formed in semiconductor substrate.
Invention is credited to Ikuko Inoue, Mariko SAITO.
Application Number | 20100207224 12/629322 |
Document ID | / |
Family ID | 42559158 |
Filed Date | 2010-08-19 |
United States Patent
Application |
20100207224 |
Kind Code |
A1 |
SAITO; Mariko ; et
al. |
August 19, 2010 |
SOLID-STATE IMAGING DEVICE HAVING PENETRATION ELECTRODE FORMED IN
SEMICONDUCTOR SUBSTRATE
Abstract
A solid-state imaging device includes an imaging element, an
external terminal, an insulating film, a penetration electrode, a
first insulating interlayer, a first electrode, and a first contact
plug. The imaging element is formed on a first main surface of a
semiconductor substrate. The external terminal is formed on a
second main surface facing the first main surface of the substrate.
The insulating film is formed in a through-hole formed in the
substrate. The penetration electrode is formed on the insulating
film in the through-hole and electrically connected to the external
terminal. The first insulating interlayer is formed on the first
main surface of the substrate and the penetration electrode. The
first electrode is formed on the first insulating interlayer. The
first contact plug is formed in the first insulating interlayer
between the penetration electrode and the first electrode to
electrically connect the penetration electrode and the first
electrode.
Inventors: |
SAITO; Mariko;
(Yokohama-shi, JP) ; Inoue; Ikuko; (Yokohama-shi,
JP) |
Correspondence
Address: |
OBLON, SPIVAK, MCCLELLAND MAIER & NEUSTADT, L.L.P.
1940 DUKE STREET
ALEXANDRIA
VA
22314
US
|
Family ID: |
42559158 |
Appl. No.: |
12/629322 |
Filed: |
December 2, 2009 |
Current U.S.
Class: |
257/432 ;
257/E31.127 |
Current CPC
Class: |
H01L 27/14627 20130101;
H01L 2224/0401 20130101; H01L 27/14636 20130101; H01L 27/14618
20130101; H01L 31/02002 20130101; H01L 2224/05548 20130101; H01L
2224/06181 20130101; H01L 2224/13022 20130101; H01L 21/76898
20130101; H01L 27/14621 20130101; H01L 23/481 20130101; H01L
2224/13024 20130101; H01L 2224/02372 20130101 |
Class at
Publication: |
257/432 ;
257/E31.127 |
International
Class: |
H01L 31/0232 20060101
H01L031/0232 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 13, 2009 |
JP |
2009-031430 |
Claims
1. A solid-state imaging device comprising: an imaging element
formed on a first main surface of a semiconductor substrate; an
external terminal formed on a second main surface facing the first
main surface of the semiconductor substrate; an insulating film
formed in a through-hole formed in the semiconductor substrate; a
penetration electrode formed on the insulating film in the
through-hole and electrically connected to the external terminal; a
first insulating interlayer formed on the first main surface of the
semiconductor substrate and the penetration electrode; a first
electrode formed on the first insulating interlayer; and a first
contact plug formed in the first insulating interlayer between the
penetration electrode and the first electrode to electrically
connect the penetration electrode and the first electrode to each
other.
2. The solid-state imaging device according to claim 1, wherein,
when being viewed from a direction perpendicular to the first main
surface of the semiconductor substrate, the first contact plug is
arranged in a region in which the penetration electrode and the
first insulating interlayer are in contact with each other.
3. The solid-state imaging device according to claim 1, further
comprising: a second insulating interlayer formed on the first
electrode; a second electrode formed on the second insulating
interlayer; a passivation film formed on the second electrode and
the second insulating interlayer to have an opening, the opening
partially exposing the second electrode; and a second contact plug
formed between the first electrode and the second electrode to
electrically connect the first electrode and the second electrode
to each other.
4. The solid-state imaging device according to claim 3, wherein,
when being viewed from a direction perpendicular to the first main
surface of the semiconductor substrate, the second contact plug is
arranged in a region which does not overlap the through-hole.
5. The solid-state imaging device according to claim 3, wherein,
when being viewed from a direction perpendicular to the first main
surface of the semiconductor substrate, the second contact plug is
arranged in a region which does not overlap the opening held in the
passivation film.
6. The solid-state imaging device according to claim 1, further
comprising: a color filter arranged on the imaging element to
correspond to the imaging element; and a microlens arranged on the
color filter.
7. The solid-state imaging device according to claim 6, further
comprising: an optically transparent support substrate arranged
above the semiconductor substrate; and an adhesive agent which
causes the semiconductor substrate and the optically transparent
support substrate to adhere to each other.
8. The solid-state imaging device according to claim 7, wherein a
cavity is present between the microlens and the optically
transparent support substrate.
9. The solid-state imaging device according to claim 7, further
comprising an imaging lens arranged above the optically transparent
support substrate.
10. The solid-state imaging device according to claim 9, further
comprising an infrared cut filter arranged between the optically
transparent support substrate and the imaging lens.
11. The solid-state imaging device according to claim 1, wherein
the penetration electrode electrically connects the imaging element
and the external element to each other.
12. The solid-state imaging device according to claim 1, wherein
the imaging element includes a photodiode and a transistor.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from prior Japanese Patent Application No. 2009-031430,
filed Feb. 13, 2009, the entire contents of which are incorporated
herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a solid-state imaging
device having a penetration electrode formed in a semiconductor
substrate, for example, a camera module.
[0004] 2. Description of the Related Art
[0005] In recent years, miniaturization of various electronic
appliances has progressed, and a solid-state imaging device having
a semiconductor image sensor is also required to be miniaturized.
As one technique to realize the miniaturization, there is a
penetration electrode in which a through-hole is formed to extend
from a rear surface side of a semiconductor chip on which a
semiconductor image sensor is formed to an internal electrode on a
front surface side so as to electrically connect an electrode on
the rear surface side to the internal electrode on the front
surface side through a conductor layer buried in the
through-hole.
[0006] A conventional method of forming a penetration electrode has
the following structure, for example. A through-hole is formed to
extend from a rear surface side of a silicon substrate to a front
surface side. Thereafter, an insulating film is formed in the
through-hole. After the through-hole is extended to the insulating
film and an insulating interlayer which are present between a
bottom surface of the through-hole and an internal electrode, a
conductor layer (penetration electrode) is buried in the
through-hole (for example, see Jpn. Pat. Appln. KOKAI Publication
No. 2007-53149).
[0007] However, when the through-hole is formed in the insulating
interlayer, a small-size through-hole having a diameter ranging
from about 20 to 30 .mu.m is formed. For this reason, a resist film
thickness must be made large, and the manufacturing cost increases
because a long developing time is required to pattern the resist.
The insulating film formed on the silicon substrate in the
through-hole is damaged by plasma asher used in removal of the
resist, and a short circuit occurs between the silicon substrate
and the conductor layer.
BRIEF SUMMARY OF THE INVENTION
[0008] According to an aspect of the present invention, there is
provided a solid-state imaging device comprising: an imaging
element formed on a first main surface of a semiconductor
substrate; an external terminal formed on a second main surface
facing the first main surface of the semiconductor substrate; an
insulating film formed in a through-hole formed in the
semiconductor substrate; a penetration electrode formed on the
insulating film in the through-hole and electrically connected to
the external terminal; a first insulating interlayer formed on the
first main surface of the semiconductor substrate and the
penetration electrode; a first electrode formed on the first
insulating interlayer; and a first contact plug formed in the first
insulating interlayer between the penetration electrode and the
first electrode to electrically connect the penetration electrode
and the first electrode to each other.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0009] FIG. 1 is a sectional view showing a configuration of a
camera module according to an embodiment of the present
invention;
[0010] FIG. 2 is an enlarged sectional view of portions of a
silicon semiconductor substrate and a glass substrate in the camera
module according to the embodiment;
[0011] FIG. 3 is an enlarged sectional view of a penetration
electrode and an electrode pad portion in the camera module
according to the embodiment;
[0012] FIG. 4 is a plan view of the penetration electrode and the
electrode pad portion when being viewed from a pad opening side in
the camera module according to the embodiment;
[0013] FIG. 5 is a sectional view of a first step showing a method
of manufacturing the penetration electrode in the camera module
according to the embodiment;
[0014] FIG. 6 is a sectional view of a second step showing the
method of manufacturing the penetration electrode in the camera
module according to the embodiment;
[0015] FIG. 7 is a sectional view of a third step showing the
method of manufacturing the penetration electrode in the camera
module according to the embodiment;
[0016] FIG. 8 is a sectional view of a fourth step showing the
method of manufacturing the penetration electrode in the camera
module according to the embodiment;
[0017] FIG. 9 is a sectional view of a fifth step showing the
method of manufacturing the penetration electrode in the camera
module according to the embodiment; and
[0018] FIG. 10 is a sectional view of a sixth step showing the
method of manufacturing the penetration electrode in the camera
module according to the embodiment.
DETAILED DESCRIPTION OF THE INVENTION
[0019] An embodiment of the present invention will be described
below with reference to the accompanying drawings. In this
embodiment, a camera module is exemplified as a solid-state imaging
device. In this explanation, the same reference numerals as in all
the drawings denote the same parts in the drawings.
[0020] FIG. 1 is a sectional view showing a configuration of a
camera module according to an embodiment of the present invention.
On a first main surface of a silicon semiconductor substrate
(imaging element chip) 10 on which an imaging element (not shown)
is formed, an optically transparent substrate, for example, a glass
substrate 12 is formed through-an adhesive agent 11. An infrared
(IR) cut filter 14 is arranged on the glass substrate 12 through an
adhesive agent 13, and a lens holder 17 including an imaging lens
16 is arranged on the IR cut filter 14 through an adhesive agent
15. On a second main surface of the silicon semiconductor substrate
10 facing the first main surface, an external terminal (electrode),
for example, a solder ball 18 is formed. A light-shielding and
electromagnetic shield 19 is arranged around the silicon
semiconductor substrate 10 and the glass substrate 12, and the
light-shielding and electromagnetic shield 19 is caused to adhere
to the lens holder 17 by an adhesive agent 20. With this structure,
a camera module 100 is formed.
[0021] The camera module 100 is directly mounted (chip-on-board
[COB]) on a mounting substrate 200 consisting of, for example, a
resin or ceramics through the solder ball 18.
[0022] Sectional structures of the silicon semiconductor substrate
10 and the glass substrate 12 in FIG. 1 will be described below in
detail. FIG. 2 is an enlarged sectional view of portions of a
silicon substrate and a glass substrate in the camera module
according to the embodiment. The camera module has an imaging pixel
unit in which an imaging element 21 is formed and a peripheral
circuit unit which processes a signal output from the imaging pixel
unit.
[0023] The imaging pixel unit of the camera module has the
following configuration. On the first main surface of the silicon
semiconductor substrate 10, element isolation insulating layers
(for example, shallow trench isolation [STI]) 22 and element
regions isolated by the element isolation insulating layers 22. In
the element region, the imaging element 21 including a photodiode
and a transistor is formed. An insulating interlayer 23 is formed
on the first main surface on which the imaging element 21 is
formed, and an insulating interlayer 24 is formed on the insulating
interlayer 23. Furthermore, in the insulating interlayer 24, an
interconnection 25 is formed in the insulating interlayer 24.
[0024] On the insulating interlayer 24, a passivation film 26 is
formed, and a base layer 27 is formed on the passivation film 26.
On the base layer 27, color filters 28 are formed to correspond the
imaging elements 21. On the color filter 28, an overcoat 29 is
formed. On the overcoat 29, microlenses 30 are formed to correspond
to the imaging elements 21 (or color filters 28). Furthermore, a
cavity 31 is formed above the microlenses 30, and an optically
transparent support substrate (transparent substrate), for example,
the glass substrate 12 is arranged above the cavity 31.
[0025] In the peripheral circuit unit of the camera module, the
following penetration electrode and the following electrode pad are
formed. The insulating interlayer 23 is formed on the first main
surface of the silicon semiconductor substrate 10, and an internal
electrode 32 is formed on the insulating interlayer 23. In the
insulating interlayer 24 between the internal electrode 32 and an
element surface electrode 33, a contact plug 34 which electrically
connects these electrodes to each other is formed. The contact plug
34 is formed in a region which does not overlap the through-hole
when being viewed from a direction perpendicular to the first main
surface. The element surface electrode 33 is used to apply a
voltage and read a signal through, for example, the contact plug 34
and the internal electrode 32. For example, in a die sort test, a
test probe is brought into contact with the element surface
electrode 33.
[0026] In the silicon semiconductor substrate 10, a through-hole
extending from a second main surface to the first main surface,
i.e., the second main surface to the insulating interlayer 23 is
formed. An insulating film 35 is formed on a side surface of the
through-hole and the second main surface. Furthermore, on an
internal surface of the through-hole, i.e., on the insulating film
35 and the insulating interlayer 23, a conductor layer (penetration
electrode) 36 is formed. In this case, in the insulating interlayer
23 between the conductor layer 36 and the internal electrode 32, a
contact plug 37 which electrically connects the conductor layer 36
and the internal electrode 32 to each other is formed. The contact
plug 37 is arranged in a region in which the conductor layer 36 and
the insulating interlayer 23 are in contact with each other when
being viewed from a direction perpendicular to the first main
surface. The internal electrode 32 is electrically connected to a
peripheral circuit (not shown) formed in the imaging elements 21 or
the peripheral circuit unit. In this manner, the penetration
electrode formed in the through-hole electrically connects the
solder ball 18 and the imaging elements 21 or the peripheral
circuit to each other.
[0027] On the conductor layer 36 and the insulating film 35 on the
second main surface, a protecting film, for example, a solder
resist 38 is formed. Furthermore, on the second main surface, the
solder resist 38 on the conductor layer 36 is partially bored, and
the solder ball 18 is formed on the exposed conductor layer 36.
[0028] On the element surface electrode 33, the conductor layer 36
is formed. The base layer 27 is formed on the passivation film 26,
and the overcoat 29 is formed on the base layer 27. A styrene resin
layer 39 is formed on the overcoat 29. The passivation film 26, the
base layer 27, the overcoat 29, and the styrene resin layer 39
which are arranged on the element surface electrode 33 are bored to
form a pad opening 40. On the styrene resin layer 39 and the
element surface electrode 33, the glass substrate 12 is formed
through the adhesive agent 11. The adhesive agent 11 is patterned
and is not arranged on the imaging elements 21 (on the microlenses
30).
[0029] The solder resist 38 consists of, for example, a phenolic
resin, a polyimide resin, an amine resin, or the like. As the
solder ball 18, for example, Sn--Pb (eutectic) or 95Pb--Sn
(high-lead high-melting-point solder) is used. As a Pb-free solder,
Sn--Ag, Sn--Cu, Sn--Ag--Cu, or the like is used.
[0030] The penetration electrode and the electrode portion in the
camera module according to the embodiment will be described below
in detail. FIG. 3 is an enlarged sectional view of the penetration
electrode and the electrode pad portion in the camera module. FIG.
4 is a plan view of the penetration electrode and the electrode
portion when being viewed from a pad opening side. FIGS. 3 and 4
show the penetration electrode and the electrode portion up to the
passivation film 26 formed on the insulating interlayer 24, and do
not show members formed on the passivation film 26.
[0031] In FIG. 3, as described above, a penetration electrode 36
extending from the second main surface of the silicon semiconductor
substrate 10 to the first main surface thereof is formed. The
internal electrode 32 is formed on the first main surface of the
silicon semiconductor substrate 10 through the insulating
interlayer 23. In the insulating interlayer 23 between the
conductor layer 36 and the internal electrode 32, the contact plug
37 is formed. The contact plug 37, as shown in FIG. 4, is arranged
in a region in which the penetration electrode 36 and the
insulating interlayer 23 are in contact with each other when viewed
from a direction perpendicular to the first main surface, i.e.,
when viewed from the pad opening side. In FIGS. 3 and 4, reference
numeral 41 denotes a region in which the penetration electrode 36
and the insulating interlayer 23 are in contact with each other,
and reference numeral 42 denotes an outer shape of the through-hole
on the first main surface.
[0032] A method of manufacturing a penetration electrode in the
camera module according to the embodiment will be described below.
FIGS. 5 to 10 are sectional views of steps showing the method of
manufacturing a penetration electrode in the camera module.
[0033] As shown in FIG. 5, the insulating interlayer 23 is formed
on the first main surface of the silicon semiconductor substrate
10. Subsequently, the contact plug 37 is formed on the insulating
interlayer 23, and the internal electrode 32 is formed on the
contact plug 37 and the insulating interlayer 23. In this manner,
the silicon semiconductor substrate 10 and the internal electrode
32 are connected to each other through the contact plug 37. The
contact plug 37 is formed as follows. After a hole is formed in the
insulating interlayer 23 by a photolithography process, a metal
material, for example, tungsten (W) is deposited on the insulating
interlayer 23 to bury the hole with tungsten. Subsequently, an
excessive tungsten on the insulating interlayer 23 is polished by
the chemical mechanical polishing (CMP) process. Thereafter, the
internal electrode 32, for example, an aluminum (Al) film or a
copper (Cu) film is formed on the insulating interlayer 23.
[0034] As shown in FIG. 6, a through-hole 43 is formed in the
silicon semiconductor substrate 10. Subsequently, as shown in FIG.
7, the insulating film 35 is formed on the internal surface of the
through-hole 43, i.e., on the side surface and the bottom surface
(surface of the insulating interlayer 23) of the through-hole 43.
Thereafter, as shown in FIG. 8, a resist 44 is coated on the
insulating film 35, and, as shown in FIG. 9, the resist 44 is
patterned by a photolithography process.
[0035] As shown in FIG. 10, the insulating film 35 which is not
protected by the resist 44 is removed. More specifically, the
insulating film 35 on the insulating interlayer 23 on which the
contact plug 37 is formed is removed. Thereafter, after the resist
44 is peeled, as shown in FIG. 3, the conductor layer 36 is formed
on the insulating film 35, the contact plug 37, and the insulating
interlayer 23. With the above operations, a penetration electrode
(conductor layer) connected to the internal electrode 32 through
the contact plug 37 is manufactured.
[0036] According to the embodiment having the above structure, the
penetration electrode (conductor layer) 36 and the internal
electrode 32 are connected by the contact plug 37 to make it
possible to omit a process of forming a through-hole in the
insulating interlayer 23 on the first main surface. In this manner,
since the thickness of the resist 44 can be reduced, a patterning
time for the resist 44 can be shortened, and a manufacturing cost
can be reduced. Furthermore, since the resist 44 can be thinned,
damage to the insulating film 35 by plasma asher used when the
resist 44 is peeled can be reduced. In this manner, short circuits
occurring between the penetration electrode 36 and the silicon
semiconductor substrate 10 can be reduced.
[0037] In the example described above, two electrodes (internal
electrode 32 and element surface electrode 33) are arranged.
However, an electrode may be arranged in at least one layer. For
example, one electrode pad or a plurality of electrode pads may be
arranged in the insulating interlayer 24 between the internal
electrode 32 and the element surface electrode 33. In this case,
three interconnection layers 25 are formed in the insulating
interlayer 24.
[0038] In the pad opening 40 above the element surface electrode
33, an opening end position of the passivation film 26 is different
from opening end positions of the base layer 27, the overcoat 29,
the styrene resin layer 39 to form a step. However, the pad opening
40 may be formed such that the opening end positions are matched
with each other. A step may be formed but need not be formed
between the opening end position of the overcoat 29 and the opening
end position of the styrene resin layer 39. Furthermore, in the
example, openings are formed in the passivation film 26, the base
layer 27, the overcoat 29, and the styrene resin layer 39 to obtain
the pad opening 40. However, a structure in which the openings in
the films and the pad opening are not formed may be used.
[0039] The embodiment of the present invention provides a
solid-state imaging device which can reduce defects due to
short-circuit occurring between a silicon substrate and a conductor
layer in a penetration electrode formed in a through-hole in a
silicon substrate.
[0040] The embodiment described above is merely an exemplary
embodiment, and various embodiments can be configured by changing
the above constituents or adding various constituents.
[0041] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concept as defined by the
appended claims and their equivalents.
* * * * *