U.S. patent application number 12/756368 was filed with the patent office on 2010-07-29 for chip package without core and stacked chip package structure.
This patent application is currently assigned to CHIPMOS TECHNOLOGIES INC.. Invention is credited to Shih-Wen Chou, Hui-Ping Liu, Yu-Tang Pan, Cheng-Ting Wu.
Application Number | 20100187691 12/756368 |
Document ID | / |
Family ID | 37660934 |
Filed Date | 2010-07-29 |
United States Patent
Application |
20100187691 |
Kind Code |
A1 |
Pan; Yu-Tang ; et
al. |
July 29, 2010 |
CHIP PACKAGE WITHOUT CORE AND STACKED CHIP PACKAGE STRUCTURE
Abstract
A chip package including a base, a chip, a molding compound and
a plurality of outer terminals is provided. The base is essentially
consisted of a patterned circuit layer having a first surface and a
second surface opposite to each other and a solder mask disposed on
the second surface, wherein the solder mask has a plurality of
first openings by which part of the patterned circuit layer is
exposed. The chip is disposed on the first surface and is
electrically connected to the patterned circuit layer. The molding
compound covers the pattern circuit layer and fixes the chip onto
the patterned circuit layer. The outer terminals are disposed in
the first openings and electrically connected to the patterned
circuit layer.
Inventors: |
Pan; Yu-Tang; (Tainan
County, TW) ; Wu; Cheng-Ting; (Tainan County, TW)
; Chou; Shih-Wen; (Tainan County, TW) ; Liu;
Hui-Ping; (Tainan County, TW) |
Correspondence
Address: |
J C PATENTS
4 VENTURE, SUITE 250
IRVINE
CA
92618
US
|
Assignee: |
CHIPMOS TECHNOLOGIES INC.
Hsinchu
TW
CHIPMOS TECHNOLOGIES (BERMUDA) LTD.
Hamilton
BM
|
Family ID: |
37660934 |
Appl. No.: |
12/756368 |
Filed: |
April 8, 2010 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
12196791 |
Aug 22, 2008 |
7723853 |
|
|
12756368 |
|
|
|
|
11302736 |
Dec 13, 2005 |
7436074 |
|
|
12196791 |
|
|
|
|
Current U.S.
Class: |
257/738 ;
257/E23.07 |
Current CPC
Class: |
H01L 25/105 20130101;
H01L 23/49816 20130101; H01L 23/49822 20130101; H01L 2224/48091
20130101; H01L 2224/73204 20130101; H01L 2924/181 20130101; H01L
2924/00014 20130101; H01L 2224/73204 20130101; H01L 2224/73215
20130101; H01L 23/3128 20130101; H01L 2924/01079 20130101; H01L
2225/1023 20130101; H01L 2224/45144 20130101; H01L 2924/181
20130101; H01L 23/4951 20130101; H01L 2221/68345 20130101; H01L
24/45 20130101; H01L 2924/18161 20130101; H01L 2224/73215 20130101;
H01L 2924/00014 20130101; H01L 2224/16225 20130101; H01L 2924/15311
20130101; H01L 2924/18165 20130101; H01L 23/49534 20130101; H01L
21/6835 20130101; H01L 2924/15311 20130101; H01L 2224/4824
20130101; H01L 2924/15331 20130101; H01L 2924/00 20130101; H01L
2924/00 20130101; H01L 2224/73215 20130101; H01L 2224/16225
20130101; H01L 2224/48091 20130101; H01L 2924/00014 20130101; H01L
2224/32225 20130101; H01L 2224/32225 20130101; H01L 2224/32225
20130101; H01L 2224/4824 20130101; H01L 2924/00 20130101; H01L
2224/4824 20130101; H01L 2224/45015 20130101; H01L 2924/00012
20130101; H01L 2224/32225 20130101; H01L 2924/00014 20130101; H01L
2924/207 20130101; H01L 2224/73204 20130101; H01L 2924/00012
20130101; H01L 24/48 20130101; H01L 2224/16225 20130101; H01L
2224/32225 20130101; H01L 2225/1058 20130101; H01L 2224/45144
20130101; H01L 2924/1532 20130101; H01L 2924/15311 20130101 |
Class at
Publication: |
257/738 ;
257/E23.07 |
International
Class: |
H01L 23/498 20060101
H01L023/498 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 14, 2005 |
TW |
94123850 |
Claims
1. A chip package, comprising: a base, consisting of: a patterned
circuit layer having a first surface and a second surface opposite
to each other; and a solder mask disposed on the second surface,
wherein the solder mask has a plurality of first openings by which
part of the patterned circuit layer is exposed; a chip disposed on
the first surface; a plurality of conductive wires, wherein the
chip is electrically connected to the second surface of the
patterned circuit layer through the conductive wires; a molding
compound covering the pattern circuit layer and fixing the chip
onto the patterned circuit layer; and a plurality of outer
terminals disposed in the first openings, wherein the outer
terminals are electrically connected to the patterned circuit
layer, the molding compound, the solder mask and the outer
terminals cover the second surface of the patterned circuit layer
entirely.
2. The chip package as claimed in claim 1, wherein the outer
terminals include solder balls.
3. The chip package as claimed in claim 1, wherein part of the chip
is exposed by the molding compound.
4. The chip package as claimed in claim 1, further comprising an
adhesive compound disposed between the chip and the first surface
of the patterned circuit layer.
5. The chip package as claimed in claim 1, wherein the molding
compound encapsulates the chip, the patterned circuit layer, the
conductive wires, and part of the solder mask.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of and claims the priority
benefit of an application Ser. No. 12/196,791, filed on Aug. 22,
2008, which is a divisional of an application Ser. No. 11/302,736,
filed on Dec. 13, 2005, now U.S. Pat. No. 7,436,074. The
application Ser. No. 11/302,736 claims the priority benefit of
Taiwan application serial no. 94123850, filed on Jul. 14, 2005. The
entirety of each of the above-mentioned patent applications is
hereby incorporated by reference herein and made a part of this
specification.
BACKGROUND OF THE INVENTION
[0002] 1. Field of Invention
[0003] The present invention relates to a chip package without a
core and stacked package structure thereof. More particularly, the
present invention relates to a chip package having small thickness
and without a core, and stacked package structure thereof.
[0004] 2. Description of Related Art
[0005] In the information era today, users prefer electronic
products with high speed, high quality and versatile functions. In
terms of product appearance, the design of the electronic products
tends to be lighter, thinner, shorter and smaller. In order to
achieve the above aspects, many companies have incorporated a
systematic concept in the circuit design. Accordingly, the single
chip can have versatile functions to reduce the number of the chips
disposed in the electronic products. Moreover, in the technology of
electronic package, in order to meet the light, thin, short and
small design trend, the package design concept of the of multi-chip
module (MCM), chip scale package (CSP) and stacked multi-chip have
been developed. The following is a description of several
conventional chip package structures.
[0006] FIG. 1 is a cross-sectional diagram of a conventional
stacked chip package structure. Referring to FIG. 1, the
conventional stacked chip package structure 50 includes a package
substrate 100 and multiple chip packages 200a, 200b, wherein the
chip packages 200a, 200b stacked on the circuit substrate 100 are
electrically connected to the circuit substrate 100. Each of the
chip packages 200a, 200b includes a package substrate 210, a chip
220, multiple bumps 230, an under fill 240 and multiple solder
balls 250. The chip 220 and the bumps 230 are disposed on the
package substrate 210, the bumps 230 are disposed between the chip
220 and the package substrate 210, and the chip 220 is electrically
connected to the package substrate 210 via the bumps 230. The under
fill 240 disposed between the chip 220 and the package substrate
210 cover these bumps 230.
[0007] The package substrate 210 has multiple conductive poles 212
and multiple bonding pads 214, wherein each conductive pole 212
passes through the package substrate 210, and each bonding pad 214
is disposed on the conductive pole 212. Moreover, each solder ball
250 is disposed on the bonding pad 214. Accordingly, the chip
package 200a is electrically connected to the chip package 200b by
the solder ball 250, and the chip package 200b is electrically
connected to the circuit substrate 100 by the solder ball 250.
[0008] In general, in the manufacturing method of the package
substrate 210, the core dielectric layer is used as the core
material, the patterned circuit layer and the patterned dielectric
layer are inter-stacked on the core dielectric layer in a fully
additive process, semi-additive process, subtractive process or
other process. Accordingly, the core dielectric layer may take a
major proportion in the entire thickness of the package substrate
210. Therefore, if the thickness of the core dielectric layer can
not be reduced effectively, it would be a big obstacle in reducing
the thicknesses of the chip package 200a and 200b.
[0009] Of course, when a bottleneck is met in the reduction of the
thicknesses of the chip package 200a and 200b, the entire thickness
of the stacked chip package structure 50 cannot be effectively
reduced, such that the package integrity of the stacked chip
package structure 50 cannot be improved effectively.
SUMMARY OF THE INVENTION
[0010] Accordingly, the present invention is directed to provide a
chip package and a stacked chip package structure with thinner
thickness and high package integrity.
[0011] As embodied and broadly described herein, the present
invention is directed to provide A chip package, comprising a base,
a chip, a plurality of conductive wires, a molding compound, and a
plurality of outer terminals. The base, consists of a patterned
circuit layer having a first surface and a second surface opposite
to each other and a solder mask disposed on the second surface,
wherein the solder mask has a plurality of first openings by which
part of the patterned circuit layer is exposed. The chip is
disposed on the first surface. The chip is electrically connected
to the second surface of the patterned circuit layer through the
conductive wires. The molding compound covers the pattern circuit
layer and fixes the chip onto the patterned circuit layer. The
plurality of outer terminals is disposed in the first openings,
wherein the outer terminals are electrically connected to the
patterned circuit layer, the molding compound, the solder mask and
the outer terminals cover the second surface of the patterned
circuit layer entirely.
[0012] In an embodiment of the present invention, the outer
terminals include solder balls.
[0013] In an embodiment of the present invention, part of the chip
is exposed by the molding compound.
[0014] In an embodiment of the present invention, the chip package
further comprises an adhesive compound disposed between the chip
and the first surface of the patterned circuit layer.
[0015] In an embodiment of the present invention, the molding
compound encapsulates the chip, the patterned circuit layer, the
conductive wires, and part of the solder mask.
[0016] Compared with the conventional technology, the chip package
in the present invention does not have the core dielectric layer,
thus having thinner thickness. Moreover, the stacked chip package
structure formed by stacked chip packages has high package
integrity because each chip package has thinner thickness.
[0017] In order to the make the aforementioned and other objects,
features and advantages of the present invention comprehensible, a
preferred embodiment accompanied with figures is described in
detail below.
[0018] It is to be understood that both the foregoing general
description and the following detailed description are exemplary,
and are intended to provide further explanation of the invention as
claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The accompanying drawings are included to provide a further
understanding of the invention, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the invention and, together with the description,
serve to explain the principles of the invention.
[0020] FIG. 1 is a cross-sectional diagram of a conventional
stacked chip package structure.
[0021] FIG. 2A to FIG. 2F are flow charts showing the manufacturing
process of the chip package according to the first embodiment of
the present invention.
[0022] FIG. 3A to FIG. 3F are flow charts showing the manufacturing
process of the chip package according to the second embodiment of
the present invention.
[0023] FIG. 4A to FIG. 4E are flow charts showing the manufacturing
process of the chip package according to the third embodiment of
the present invention.
[0024] FIG. 5 is a diagram of the stacked chip package structure
according to the third embodiment of the present invention.
[0025] FIG. 6A to FIG. 6D are flow charts showing the manufacturing
process of the chip package according to the fourth embodiment of
the present invention.
DESCRIPTION OF EMBODIMENTS
The First Embodiment
[0026] FIG. 2A to FIG. 2F are flow charts showing the manufacturing
process of the chip package according to the first embodiment of
the present invention. Referring to FIG. 2A, first, a conductive
layer 310 is provided, wherein the conductive layer 310 has a first
surface 314 and a second surface 312 opposite to each other, and
the material of the conductive layer 310 is copper. Then, a solder
mask 320 is formed on the second surface 312, and the solder mask
320 is patterned in a photolithography and etching process to form
a second opening 322 and multiple first openings 324, wherein part
of the conductive layer 310 is exposed by the second opening 322
and the first opening 324. In one embodiment, a brown oxidation or
a black oxidation process can further be performed on the
conductive layer 310 to improve the surface roughness of the
conductive layer 310. Accordingly, the combination between the
conductive layer 310 and the solder mask 320 is improved.
[0027] Then, referring to FIG. 2B, a diaphragm 330 is formed on the
solder mask 320 to serve as the carrier for the conductive layer
310 and the solder mask 320 in the subsequent manufacturing
processes, wherein the diaphragm 330, for example, can be attached
on the solder mask 320 by the adhesive compound or be directly
formed on the solder mask 320 in another process. Therefore, the
conductive layer 310 and the solder mask layer 320 can obtain
enough support in the subsequent processes to ensure a smooth
operation in the subsequent processes. In one embodiment, the
diaphragm 330 can also be fixed on the frame 340 to provide better
support for the conductive layer 310 and the solder mask 320.
Thereafter, the conductive layer 310 is patterned to form the
patterned circuit layer 350 in a photolithography and etching
manufacturing process.
[0028] Then, referring to FIG. 2C, an opening 332 and multiple
openings 334 are formed on the diaphragm 330 in a photolithography
and etching manufacturing process. Then, a chip 360 is disposed on
the first surface 314 by disposing the adhesive compound 365
between the chip 360 and the patterned circuit layer 350 to fix the
relative positions of each other, for example. Then, in a wire
bonding technology, the chip 330 is electrically connected to the
patterned circuit layer 350 by multiple conductive wires 370.
Wherein, the material of the conductive wires 370 is, for example,
Au. Part of the patterned circuit layer 350 is exposed by the first
opening 324 and the opening 334, and part of the patterned circuit
layer 350 and part of the chip 330 are exposed by the second
opening 322 and the opening 332.
[0029] Of course, the opening 332 and the opening 334 can be formed
after or before the conductive layer 310 is patterned. Then, the
conductive layer 310 is patterned to form the patterned conductive
layer 350.
[0030] Referring to FIG. 2D, a molding compound 380 is formed on
the patterned circuit layer 350 by a suitable mold to cover on the
patterned circuit layer 350 and the chip 360, and also fix the chip
360 onto the patterned circuit layer 350. Moreover, the molding
compound 380 can be further filled into the second opening 322 by a
suitable mold to cover on the conductive wire 370. In addition, an
outer terminal 390 can be formed on each first opening 324.
Accordingly, the outer terminal 390 is electrically connected to
the patterned circuit layer 350 by the first opening 324. For
example, when the outer terminal 390 is a solder ball, the outer
terminal 390 is electrically connected to the patterned circuit
layer 350 by a reflowing process.
[0031] Then, referring to FIG. 2E, the diaphragm 330 is removed to
obtain the chip package 300, wherein the diaphragm 330 is removed,
for example, in an etching process, an ashing process, or other
process. Although part of the chip 360 is exposed by the molding
compound 380 in the embodiment, it is clear that the molding
compound 380 can cover the chip 360 by a suitable mold, as shown in
FIG. 2F.
[0032] Therefore, the chip package 300 of the present invention
mainly includes a patterned circuit layer 350, a chip 360, a solder
mask 320, and a molding compound 380. Wherein, the patterned
circuit layer 350 has a second surface 312 and a first surface 314
opposite to each other. The chip 360 disposed on the first surface
314 is electrically connected to the patterned circuit layer 350.
The solder mask 320 disposed on the second surface 312 has multiple
first openings 324 by which part of the patterned circuit layer 350
is exposed. The molding compound 380 covers the pattern circuit
layer 350 and fixes the chip 360 onto the patterned circuit layer
350.
[0033] Compared with the conventional technology, the chip package
300 does not have the core dielectric layer, thus having thinner
thickness.
The Second Embodiment
[0034] In the manufacturing process of the chip package, the chip
360 can also be electrically connected to the patterned circuit
layer 350 in a flip chip technology, chip on film (COF) technology
or other technology in addition to the wire bonding technology in
the first embodiment. The following will illustrate the
manufacturing process of the chip package in a flip chip technology
as an example.
[0035] FIG. 3A to FIG. 3E are flow charts showing the manufacturing
process of the chip package according to the second embodiment of
the present invention. Referring to FIG. 3A, first, a conductive
layer 310 is provided, wherein the conductive layer 310 has a
second surface 312 and a first surface 314 opposite to each other.
Then, a solder mask 320 is formed on the second surface 312, and
the solder mask 320 is patterned, for example, in a
photolithography and etching process to form multiple first
openings 324, wherein part of the conductive layer 310 is exposed
by the first opening 324. Also, a brown oxidation or a black
oxidation process can be performed on the conductive layer 310 to
improve the surface roughness of the conductive layer 310.
Accordingly, the bonding between the conductive layer 310 and the
solder mask 320 is improved.
[0036] Then, referring to FIG. 3B, the diaphragm 330 is formed on
the solder mask 320 to serve as the carrier for the conductive
layer 310 and the solder mask 320 in the subsequent manufacturing
process, wherein the diaphragm 330, for example, can be attached on
the solder mask 320 by an adhesive compound or be directly formed
on the solder mask 320 in another process. Also, the diaphragm 330
can also be fixed on the frame 340 to provide better support for
the conductive layer 310 and the solder mask 320. Thereafter, the
conductive layer 310 is patterned to form the patterned circuit
layer 350 in a photolithography and etching manufacturing
process.
[0037] Then, referring to FIG. 3C, multiple openings 334 are formed
on the diaphragm 330 in a photolithography and etching
manufacturing process. Then, in a flip chip technology, the chip
360 is disposed on the first surface 314 by disposing multiple
bumps 372 between the chip 360 and the patterned circuit layer 350,
and a reflowing process is performed for the bumps 372.
Accordingly, the chip 330 is electrically connected to the
patterned circuit layer 350 by multiple bumps 372. Wherein, the
material of the bumps 372 is, for example, soldering tin, Au or
other conductive materials, and part of the patterned circuit layer
350 is exposed by the first opening 324 and the opening 334.
Moreover, in the embodiment, an under fill 374 can be further
formed between the chip 360 and the patterned conductive layer 350
to cover each bump 372.
[0038] Referring to FIG. 3D, the molding compound 380 is formed on
the patterned circuit layer 350 by a suitable mold to cover the
patterned circuit layer 350 and the chip 360, and also fix the chip
360 onto the patterned circuit layer 350. Note that if there is no
under fill 374 formed between the chip 360 and the patterned
conductive layer 350 in the process in FIG. 3C, the molding
compound 380 can further substitute the under fill 374 to cover the
bumps 372. In addition, an outer terminal 390 can be formed on each
first opening 324. Accordingly, the outer terminal 390 is
electrically connected to the patterned circuit layer 350 by the
first opening 324. For example, when the outer terminal 390 is a
solder ball, the outer terminal 390 is electrically connected to
the patterned circuit layer 350 in a reflowing process.
[0039] Then, referring to FIG. 3E, the diaphragm 330 is removed to
obtain the chip package 300', wherein, the diaphragm 330 is removed
in a process described in FIG. 3E. Although part of the chip 360 is
exposed by the molding compound 380 in the embodiment, it is clear
that the molding compound 380 can cover the chip 360 by a suitable
mold, as shown in FIG. 3F.
The Third Embodiment
[0040] In addition to the chip package 300 and 300', the
manufacturing process of the chip package of the present invention
can also be used to make another chip package suitable for making a
stacked chip package structure, and the manufacturing process is
described in detail in the following.
[0041] FIG. 4A to FIG. 4E are flow charts showing the manufacturing
process of the chip package according to the third embodiment of
the present invention. Referring to FIG. 4A, first, a conductive
layer 310 is provided, wherein the conductive layer 310 has a
second surface 312 and a first surface 314 opposite to each other.
Then, a solder mask 320 is formed on the second surface 312, and
the solder mask 320 is patterned, for example, in a
photolithography and etching process to form the second opening 322
and a plurality of first openings 324, wherein part of the
conductive layer 310 is exposed by the second opening 322 and the
first opening 324. In one embodiment, a brown oxidation or a black
oxidation process can further be performed on the conductive layer
310 to improve the roughness of the surface of the conductive layer
310, such that the conductive layer 310 and the solder mask 320
have better bonding.
[0042] Then, referring to FIG. 4B, the diaphragm 330 is formed on
the solder mask 320 to serve as the carrier for the conductive
layer 310 and the solder mask 320 in the subsequent manufacturing
process, wherein the diaphragm 330, for example, can be attached on
the solder mask 320 by an adhesive compound or be directly formed
on the solder mask 320 in other process. Accordingly, the
conductive layer 310 and the solder mask layer 320 can have enough
support in the subsequent process to ensure a smooth operation in
the subsequent processes. Also, in one embodiment, the diaphragm
330 can also be fixed on the frame 340 to provide better support
for the conductive layer 310 and the solder mask 320. Thereafter,
the conductive layer 310 is patterned to form the patterned circuit
layer 350 in a photolithography and etching manufacturing
process.
[0043] Then, referring to FIG. 4C, the chip 360 is disposed on the
first surface 314 by disposing the adhesive compound 365 between
the chip 360 and the patterned circuit layer 350, for example.
Then, for example, in a wire bonding technology, the chip 330 is
electrically connected to the patterned circuit layer 350 by
multiple conductive wires 370. Wherein, part of the patterned
circuit layer 350 and part of the chip 330 are exposed
simultaneously by the second opening 322 and the opening 332.
[0044] Of course, the opening 332 and the opening 334 can be formed
after or before the conductive layer 310 is patterned. Then, the
conductive layer 310 is patterned to form the patterned conductive
layer 350.
[0045] Referring to FIG. 4D, the molding compound 380 is formed on
the patterned circuit layer 350 by a suitable mold to cover the
patterned circuit layer 350 and the chip 360, and also fix the chip
360 onto the patterned circuit layer 350. Moreover, the molding
compound 380 can further be filled into the second opening 322 by a
suitable mold to cover the conductive wire 370. In addition,
multiple through holes 382 are formed on the molding compound 380
by which part of the patterned circuit layer 350 is exposed.
Wherein, the forming method of the through hole 382 includes, for
example, forming these through holes 382 while molding the molding
compound 380, or forming these through holes 382 in a mechanical
drill or laser ablation process after the molding compound 380 is
formed, or in other process.
[0046] Then, an outer terminal 390 is formed in each through hole
382, and the outer terminal 390 is electrically connected to the
patterned circuit layer 350 by the through hole 382. In one
embodiment, the outer terminal 390 includes a conductive pole 392
and a solder ball 394. The conductive pole 392 disposed within the
through hole 382 is electrically connected to the patterned circuit
layer 350, wherein the conductive pole 392 is formed within the
through hole 382, for example, in an electroplating process; or, by
filling the conductive material into the through hole 382 directly
to form the conductive pole 392; or, directly disposing the
conductive pole 392 on the predefined position to form the through
hole 392 on the mold, and performing a molding process for the
molding compound 382, and accordingly, the configuration of the
conductive pole 392 is completed at the same time when the through
hole 382 is formed. The solder ball 394 is disposed on the
conductive pole 392 and is electrically connected to the conductive
pole 392.
[0047] Referring to FIG. 4E, the diaphragm 330 is removed to obtain
the chip package 400, and the diaphragm 330 is removed in the
process described in FIG. 2E. Of course, it can be learned from the
first embodiment and the second embodiment that electrical
connection between the chip 360 and the patterned circuit layer 320
can also be achieved by a flip chip technology, chip on film (COF)
technology or other technology, and, the detail is omitted
here.
[0048] Accordingly, the chip package 400 according to the
embodiment mainly includes a patterned circuit layer 350, a chip
360, a solder mask 320, a molding compound 380 and multiple outer
terminals 390. Wherein, the patterned circuit layer 350 has a
second surface 312 and a first surface 314 opposite to each other.
The chip 360 disposed on the first surface 314 is electrically
connected to the patterned circuit layer 350. The solder mask 320
disposed on the second surface 312 has multiple openings 324 by
which part of the patterned circuit layer 350 is exposed. The
molding compound 380 covers the pattern circuit layer 350 and fixes
the chip 360 onto the patterned circuit layer 350, wherein the
molding compound 380 has a plurality of through holes 382. An outer
terminal 390 disposed in each through hole 382 is electrically
connected to the patterned circuit layer 350.
[0049] The present invention further provides a stacked chip
package structure based on the above chip package 400. FIG. 5 is a
diagram of the stacked chip package structure according to the
third embodiment of the present invention. The stacked chip package
structure 500 mainly includes multiple chip packages 400 stacked on
each other, wherein each outer terminal 390 of the chip package 400
disposed in the upper layer is corresponding to the first opening
324 of the chip package 400 disposed in the lower layer, and each
outer terminal 390 of the chip package 400 disposed in the upper
layer is electrically connected to the patterned circuit layer 350
of the chip package 400 disposed in the lower layer. Moreover, the
stacked chip package structure 500 further includes a common
carrier 510 where the chip packages 400 can be stacked, and the
chip package 400 can be electrically connected to the common
carrier 510 by the outer terminal 390 of the chip package 400
disposed in the lowest layer.
[0050] Compared with the conventional technology, the chip package
400 has thinner thickness. The stacked chip package structure 500
having multiple chip packages 400 not only has more thickness
reduction capability, but also higher package integrity.
The Fourth Embodiment
[0051] FIG. 6A to FIG. 6D and FIG. 2B to FIG. 2E are flow charts
showing the manufacturing process of the chip package in sequence
according to the fourth embodiment of the present invention. The
embodiment discloses another manufacture process of the chip
package of the present invention. Referring to FIG. 6A, first, a
conductive layer 310 is provided, wherein the conductive layer 310
has a second surface 312 and a first surface 314 opposite to each
other. Then, a diaphragm 600 is formed on the first surface
314.
[0052] Then, referring to FIG. 6B, the conductive layer 310 is
patterned to form the patterned circuit layer 350 in a
photolithography and etching manufacturing process. Then, a solder
mask 320 is formed on the second surface 312, and the solder mask
320 is patterned in a photolithography and etching process to form
a second opening 322 and a plurality of first openings 324, wherein
part of the conductive layer 310 is exposed by the second opening
322 and the first opening 324.
[0053] Then, referring to FIG. 6C and FIG. 6D, the diaphragm 330 is
first formed on the folder mask 320 to form the structure as shown
in FIG. 6C. Thereafter, as shown in FIG. 6D, the diaphragm 600 is
removed to obtain the structure as shown in FIG. 2B. The subsequent
processes are the same as described in FIG. 2B to FIG. 2E, so that
the details are omitted here. The diaphragm 600 is removed, for
example, in an etching process, a tearing off process, an ashing
process or other process.
[0054] In summary, compared with the conventional technology, the
chip package in the present invention does not have the core
dielectric layer, thus having thinner thickness. Moreover, the
stacked chip package structure with stacked chip packages has
thinner thickness and higher package integrity.
[0055] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
present invention without departing from the scope or spirit of the
invention. In view of the foregoing, it is intended that the
present invention cover modifications and variations of this
invention provided they fall within the scope of the following
claims and their equivalents.
* * * * *