U.S. patent application number 12/636657 was filed with the patent office on 2010-07-22 for chip package structure and method for fabricating the same.
Invention is credited to Tien-Hao HUANG, Chia-Lun TSAI, Shang-Yi WU.
Application Number | 20100181589 12/636657 |
Document ID | / |
Family ID | 42239457 |
Filed Date | 2010-07-22 |
United States Patent
Application |
20100181589 |
Kind Code |
A1 |
HUANG; Tien-Hao ; et
al. |
July 22, 2010 |
CHIP PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME
Abstract
The invention provides a chip package structure and method for
fabricating the same. The chip package structure includes a carrier
substrate. A plurality of isolated conductive layers is disposed on
the carrier substrate. At least one chip is disposed on the carrier
substrate, wherein the chip has a plurality of electrodes. The
electrodes are electrically connected to the conductive layers. A
conductive path is disposed in the carrier substrate, electrically
connected to the electrodes through the conductive layers, wherein
the conductive path comprises a plurality of laminating holes.
Inventors: |
HUANG; Tien-Hao; (Zhongli
City, TW) ; WU; Shang-Yi; (Hsinchu City, TW) ;
TSAI; Chia-Lun; (Tainan City, TW) |
Correspondence
Address: |
Wen Liu;LIU & LIU
Suite 1750, 444 S. Flower Street
Los Angeles
CA
90071
US
|
Family ID: |
42239457 |
Appl. No.: |
12/636657 |
Filed: |
December 11, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61121880 |
Dec 11, 2008 |
|
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|
Current U.S.
Class: |
257/98 ;
257/E21.499; 257/E33.056; 438/26 |
Current CPC
Class: |
H01L 33/486 20130101;
H01L 33/642 20130101; H01L 33/62 20130101; H01L 2224/73265
20130101; H01L 2224/92247 20130101; H01L 33/647 20130101; H01L
2224/48091 20130101; H01L 2924/00014 20130101; H01L 2924/1461
20130101; H01L 2924/1461 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/98 ; 438/26;
257/E33.056; 257/E21.499 |
International
Class: |
H01L 33/62 20100101
H01L033/62; H01L 21/50 20060101 H01L021/50 |
Claims
1. A chip package structure, comprising: a carrier substrate having
a cavity; a plurality of isolated conductive layers disposed on the
carrier substrate; at least one chip disposed in the cavity of the
carrier substrate, wherein the chip has a plurality of electrodes
to electrically connect to the conductive layers; and a conductive
path disposed in the carrier substrate, electrically connected to
the electrodes through the conductive layers, wherein the
conductive path comprises a plurality of laminated holes.
2. The chip package structure as claimed in claim 1, further
comprising an insulating layer isolating the conductive layers and
the carrier substrate or the conductive path and the carrier
substrate from each other.
3. The chip package structure as claimed in claim 1, wherein the
conductive layers are conformably disposed on sidewalls and a
bottom portion of the cavity.
4. The chip package structure as claimed in claim 1, wherein the
carrier substrate is a silicon substrate.
5. The chip package structure as claimed in claim 1, further
comprising a reflection layer disposed on sidewalls and a bottom
portion of the cavity.
6. The chip package structure as claimed in claim 1, wherein the
conductive path passes through the carrier substrate.
7. The chip package structure as claimed in claim 6, wherein the
conductive path comprises a plurality of vertically laminated holes
and the conductive layers extend on a sidewall of the cavity.
8. The chip package structure as claimed in claim 7, wherein a
plurality of the vertically laminated holes comprises a first hole
and a second hole, wherein the first hole and the second hole
comprise a lateral conductive plate therebetween, wherein the
lateral conductive plate electrically connects to the conductive
layers extended on the sidewall of the cavity.
9. The chip package structure as claimed in claim 7, wherein a
plurality of the vertically laminated holes comprises a first hole
and a second hole, wherein a surface of the first hole adjacent to
the second hole is larger than a surface of the second hole
adjacent to the first hole.
10. The chip package structure as claimed in claim 7, wherein a
plurality of the vertically laminated holes comprises a first hole
and a second hole, wherein a surface of the first hole adjacent to
the second hole is larger than a surface of the second hole
adjacent to the first hole, wherein the first hole and the second
hole comprise a lateral conductive plate therebetween, wherein the
lateral conductive plate electrically connects to the conductive
layers extending on the sidewall of the cavity.
11. The chip package structure as claimed in claim 10, wherein the
first hole is a lower-level hole and the second hole is an
upper-level hole.
12. The chip package structure as claimed in claim 11, wherein a
depth of the upper-level hole is the same to that of the
cavity.
13. A method for fabricating a chip package structure, comprising:
providing a carrier substrate; forming a first hole from a first
surface of the carrier substrate; forming a second hole from a
second surface of the carrier substrate, connected and disposed
corresponding to the first hole; forming a cavity on the second
surface of the carrier substrate; forming a conductive path in the
first hole and the second hole and forming a plurality of
conductive layers isolated from each other, electrically connected
to the conductive path; and disposing at least one chip in the
cavity of the carrier substrate, wherein the chip has a plurality
of electrodes to electrically connect to the conductive layers.
14. The method for fabricating a chip package structure as claimed
in claim 13, further comprising forming an insulating layer on the
carrier substrate to isolate the conductive layers from the
conductive path.
15. The method for fabricating a chip package structure as claimed
in claim 14, wherein the first hole and the second hole comprise a
lateral conductive plate therebetween.
16. The method for fabricating a chip package structure as claimed
in claim 14, wherein a surface of the first hole adjacent to the
second hole is larger than a surface of the second hole adjacent to
the first hole.
17. The method for fabricating a chip package structure as claimed
in claim 14, wherein the first hole and the second hole comprise a
lateral conductive plate therebetween, and a surface of the first
hole adjacent to the second hole is larger than a surface of the
second hole adjacent to the first hole.
18. The method for fabricating a chip package structure as claimed
in claim 14, wherein the first hole is a lower-level hole and the
second hole is an upper-level hole.
19. The method for fabricating a chip package structure as claimed
in claim 18, wherein the upper-level hole and the cavity are formed
in the same step.
20. The method for fabricating a chip package structure as claimed
in claim 19, wherein the upper-level hole and the lower-level hole
are formed at different steps.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to a chip package structure
and method for forming the same, and in particular relates to a
light emitted chip package structure and method for forming the
same.
DESCRIPTION OF THE RELATED ART
[0002] The chip packaging process is one of the important processes
for forming chips. A chip package structure, not only provides an
interface for connecting chips to electronic elements, but also
provides protection for chips from environmental contaminants,
along with other functions.
[0003] With increasing development of the semiconductor fabrication
process, chips are being formed in smaller and smaller dimensions.
However, due to the ever-decreasing size and the ever-increasing
density of the chips, number and density of the input/output (I/O)
connections of chips have increased. Therefore, the chip area for
conductive paths between chips and outside features formation is
not enough. The fabrication cost can not be reduced due to a huge
amount of the golden wires using as I/O connections between chip
arrays and outside features, especially in package structure
composed by optoelectronic chips.
[0004] Thus, a novel package structure for improving the package
structure of chips and method for forming the same is desired.
BRIEF SUMMARY OF THE INVENTION
[0005] An exemplary embodiment of a method for fabricating a chip
package structure is provided. The chip package structure comprises
a carrier substrate having a cavity. A plurality of isolated
conductive layers is disposed on the carrier substrate; at least
one chip disposed in the cavity of the carrier substrate, wherein
the chip has a plurality of electrodes to electrically connect to
the conductive layers. A conductive path is disposed in the carrier
substrate, electrically connected to the electrodes through the
conductive layers, wherein the conductive path comprises a
plurality of laminated holes.
[0006] An exemplary embodiment of a method for fabricating a chip
package structure is provided. The method for fabricating a chip
package structure comprises providing a carrier substrate. A first
hole is formed from a first surface of the carrier substrate. A
second hole is formed from a second surface of the carrier
substrate, connected and disposed corresponding to the first hole.
A cavity is formed on the second surface of the carrier substrate.
A conductive path is formed in the first hole and the second hole.
A plurality of conductive layers is formed isolated from each
other, electrically connected to the conductive path. At least one
chip is disposed in the cavity of the carrier substrate, wherein
the chip has a plurality of electrodes to electrically connect to
the conductive layers.
DETAILED DESCRIPTION OF THE INVENTION
[0007] The following description is of a mode for carrying out the
invention. Wherever possible, the same reference numbers are used
in the drawings and the descriptions to refer the same or like
parts. In the drawings, the size of some of the elements may be
exaggerated and not drawn to scale for illustrative purposes. The
dimensions and the relative dimensions do not correspond to actual
dimensions to practice of the invention. This description is made
for the purpose of illustrating the general principles of the
invention and should not be taken in a limiting sense.
[0008] Embodiments of the package structure for chips of the
invention packaged by a wafer level packaging (WLP) process may be
applied to active or passive devices, or electronic components with
digital or analog circuits, such as optoelectronic devices, micro
electro mechanical systems (MEMS), micro fluidic systems, and
physical sensors for detecting heat, light, or pressure.
Particularly, a wafer level packaging (WLP) process may be applied
to package semiconductor chips, such as image sensor devices,
light-emitting diodes (LEDs), solar cells, RF circuits,
accelerators, gyroscopes, micro actuators, surface acoustic wave
devices, pressure sensors, or ink printer heads. The wafer level
packaging process herein mainly means that after the packaging
process is accomplished during a wafer stage, a wafer with chips is
cut to obtain separate independent packages. However, in an
embodiment of the invention, separate independent chips may be
redistributed overlying a supporting wafer and then be packaged,
which may also be referred to as a wafer level packaging process.
In addition, the wafer level packaging process may also be adapted
to form electronic device packages of multi-layered integrated
circuit devices by stacking a plurality of wafers having integrated
circuits together.
[0009] FIGS. 1A-1F are cross sections showing the steps for
fabricating a chip package structure 500 according to an embodiment
of the invention.
[0010] As shown in FIG. 1A firstly, a carrier substrate 200 having
an upper surface 200a and an opposite lower surface 200b is
provided. The carrier substrate 200 may comprise a silicon
substrate, a semiconductor substrate, a compound semiconductor
substrate, a semiconductor wafer, a sapphire substrate or
combinations thereof.
[0011] Next, still referring to FIG. 1A, holes 202a' and 202b'
penetrating through a portion of the carrier substrate 200 are
formed from the lower surface 200b of the carrier substrate 200.
The carrier substrate 200 is exposed from the bottom of the holes
202a' and 202b'. In one embodiment, deposition of the holes may be
selectively arranged. For example, the holes may be located outside
of a cavity formed in the carrier substrate 200 when a chip is
disposed on the carrier substrate 200 in a following step. Forming
through-holes stepwise instead of forming through-holes in a single
process may reduce process difficulty and increase product
yield.
[0012] Next, referring to FIG. 1B, insulating layers 204a' and
204b' are selectively formed on sidewalls of the holes 202a' and
202b' and a portion of the carrier substrate 200. The insulating
layers 204a' and 204b' may be made of non-organic materials
comprising silicon oxide, silicon nitride, silicon oxinitride,
metal oxide or combinations thereof, or organic materials
comprising polyimide, BCB.TM. The insulating layers 204a' and 204b'
may be formed by a spin coating or spray coating method, or may be
formed by other suitable deposition methods, such as a chemical
vapor deposition, low pressure chemical vapor deposition or plasma
enhanced chemical vapor deposition process. In one embodiment,
photo insulating materials may be selectively used to serve as the
insulating layers 204a' and 204b' to facilitate patterning of the
insulating layers 204a' and 204b'. Additionally, if the carrier
substrate is made of an insulating substrate, the step of
depositing the insulating layer before forming a conductive layer
on the carrier substrate can be omitted.
[0013] Next, still referring to FIG. 1B, hole conducting layers
206a' and 206b' are formed on the sidewalls of the holes 202a' and
202b'. The hole conducting layers 206a' and 206b' further extend on
the lower surface 200b of the carrier substrate 200 to serve as
conductive paths between the chip package structure and an outside
feature. For example, the hole conducting layers 206a' and 206b'
extending on the lower surface 200b of the carrier substrate 200
may further electrically connect to an outside feature such as
printed circuit board through solder balls or bumps. The hole
conducting layers 206a' and 206b' may be made of metal materials
including, conductive polymer materials, conductive ceramic
materials or combinations thereof. The hole conducting layers 206a'
and 206b' may be formed by using, for example, a physical vapor
deposition, chemical vapor deposition or chemical electroplating
process. Next, a photolithography/etching process is performed to
pattern the hole conducting layers 206a' and 206b'. In this
embodiment, the hole conducting layers 206a' and 206b' are
preferably formed in the same step. That is, the hole conducting
layers 206a' and 206b' are preferably formed by patterning a single
conductive layer.
[0014] Next, still referring to FIG. 1B, filling layers 208a' and
208b' are selectively formed on the hole conducting layers 206a'
and 206b' in the holes 202a' and 202b'. The filling layers 208a'
and 208b' may comprise polymer materials, for example, solder
masks, polyimides, or polyimide-like materials, which can serve as
permanent materials or combinations thereof. The filling layers
208a' and 208b' may be formed by using, for example, an
electroplating, spin coating, spray coating, curtain coating
process or combinations thereof.
[0015] Next, as shown in FIG. 1C, holes 202a'' and 202b'' are
formed from the upper surface 200a of the carrier substrate 200 by
methods such as an etching or laser drilling process. The holes
202a'' and 202b'' substantially align with the underlying holes
202a' and 202b'. In one embodiment, the holes 202a'' and 202b'' are
formed by an etching process, wherein the lateral hole conducting
layers 206a' and 206b' on the bottom of the holes 202a' and 202b'
may respectively serve as etching stop layers during formation of
the holes 202a'' and 202b'' during an etching process. Therefore,
the hole conducting layers 206a' and 206b' are respectively exposed
from the bottom of the holes 202a'' and 202b''. In one embodiment,
the insulating layers 204a' and 204b' on the bottoms of the holes
202a' and 202b' are also removed when forming the holes 202a'' and
202b''. Additionally, in one embodiment, top surfaces of the
previously formed holes, for example, the lower-level holes 202a'
and 202b', may be larger than top surfaces of the subsequently
formed holes, for example, the upper-level holes 202a'' and 202b'',
thereby facilitating etching alignment.
[0016] Next, still referring to FIG. 1C, a cavity 203 is formed
from the upper surface 200a of the carrier substrate 200 with
extending into the carrier substrate 200. A bottom of the cavity
203 is used for chips to be disposed thereon. In one embodiment,
the cavity 203 and the holes 202a'' and 202b'' are preferably
formed in the same step, thus reducing additional fabrication
processes. In one embodiment, if the chip disposed on the cavity
203 is a light emitted diode (LED) chip, a reflection layer may be
further formed on sidewalls and/or a bottom of the cavity 203 to
increase emitting brightness.
[0017] Next, as shown in FIG. 1D, insulating layers 204a'' and
204b'' are selectively formed on sidewalls and a bottom of the
holes 202a'' and 202b''. The insulating layers 204a'' and 204b''
further extend on the upper surface 200a of the carrier substrate
200 and the sidewalls and the bottom of the cavity 203. The
insulating layers 204a'' and 204b'' may have the same materials and
formation processes as the insulating layers 204a' and 204b'.
[0018] Next, as shown in FIG. 1E, the insulating layers 204a'' and
204b'' on the bottom of the holes 202a'' and 202b'' are removed to
expose the hole conducting layers 206a' and 206b'. The method for
removing the insulating layers 204a'' and 204b'' may comprise, for
example, a photolithography and etching process or a laser removing
process. Next, conductive layers 206a'', 206b'' and 202c'' are
conformably formed on the sidewalls and the bottoms of the holes
202a'' and 202b'' and the cavity 203. The hole conducting layers
206a'' and 206b'' may further extend from the upper surface 200a of
the carrier substrate 200. In one embodiment, an LED array may be
disposed on the bottom of the cavity 203. Preferably, a reflection
layer may be formed on the sidewalls and the bottom of the cavity
203 to increase emitting efficiency of the LED array. In one
embodiment, the reflection layer and the hole conducting layers
206a'' and 206b'' may be formed in the same step. The hole
conducting layers 206a'' and 206b'' may have the same materials and
formation processes as the hole conducting layers 206a' and 206b'.
The reflection layer may be made of metal materials having
reflectivity, and the formation process thereof may be the same to
the hole conducting layers 206a'' and 206b''. In this embodiment,
the reflection layer may be formed by the hole conducting layers
206a'', 206b'' and 202c'' extending on the sidewalls and the
bottoms of the cavity 203.
[0019] Next, filling layers 208a'' and 208b'' are selectively
formed on the hole conducting layers 206a'' and 206b'' in the holes
202a'' and 202b''. The filling layers 208a'' and 208b'' may have
the same materials and formation processes as the filling layers
208a' and 208b'.
[0020] In this embodiment, the vertically laminated holes 202a' and
202a'' and the hole conducting layers 206a' and 206a'' on the
sidewalls of the holes 202a' and 202a'' may construct a first
conductive path 320a. Similarly, the vertically laminated holes
202b' and 202b'' and the hole conducting layers 206b' and 206b'' on
the sidewalls of the holes 202b' and 202b'' may construct a second
conductive path 320b. Additionally, in one embodiment as shown in
FIG. 1E, an insulating layer comprising the insulating layers
204a', 204a'', 204b' and 204b'' is preferably between the first
conductive path 320a/the second conductive path 320b and the
carrier substrate 200. The filling layers 208a', 208a'', 208b' and
208b'' may fill on the hole conducting layers of the first
conductive path 320a and the second conductive path 320b.
[0021] Embodiments of the invention may further have many other
variations. For example, the hole conducting layers of the first
conductive path 320a and the second conductive path 320b may
substantially fill the holes. A lateral conductive layer may be
between the two laminated holes to electrically connect to the hole
conducting layers. The other variations are dependant upon
application and fabrication processes.
[0022] In this embodiment, the formation of the laminated holes
comprise forming the upper holes and the upper conductive layers
and then forming the lower holes and the lower conductive layers,
but the invention is not limited thereto. Alternatively, the
formation of the laminated holes may comprise forming lower holes
and the lower conductive layers and then forming the upper holes
and the upper conductive layers. Additionally, the cavity for the
chip disposed thereon and the upper holes may be formed at the same
step.
[0023] Next, as shown in FIG. 1F, a chip array 301 comprising at
least one chip, for example, a plurality of chips 302a and 302b
(The drawings of the described embodiments only show two chips 302a
and 302b for brevity, but the invention is not limited thereto), is
disposed on the carrier substrate 200 through an adhesive layer 324
such as a silver paste. In one embodiment, the chip array 301 may
comprise an array constructed by light emitting components such as
LEDs or laser diodes (LDs), but the invention is not limited
thereto. The chips 302a and 302b of the chip array 302 may
respectively have first electrodes 310a and 311a and second
electrodes 310b and 311b, wherein the first electrodes 310a and
311a and the second electrodes 310b and 311b of the chips 302a and
302b are disposed on lower surfaces of the chips 302a and 302b.
Alternatively, the first electrodes 310a and 311a and the second
electrodes 310b and 311b may be respectively disposed on the upper
surfaces and the lower surfaces of the chips. The first electrodes
310a and 311a and the second electrodes 310b and 311b may
electrically connect to the first conductive path 320a and the
second conductive path 320b through the hole conducting layer
206''. For example, the first electrode 310a and the second
electrode 310b of the chip 302a respectively electrically connect
to the hole conducting layers 206a'' and 206c''. The first
electrode 311a and the second electrode 311b of the chip 302b
respectively electrically connect to the hole conducting layers
206b'' and 206c''. Therefore, the chips 302a and 302b may be in
parallel or series connection.
[0024] As shown on FIG. 1F, in other embodiments of the light
emitting chips, a fluorescent layer 336 having a uniform thickness
may selectively conformably cover the light emitting chip array
301. Further, in other embodiments, a lens structure 338 may be
selectively formed on the chip array 301. The lens structure 338
may be disposed as required.
[0025] The exemplary embodiments of the chip package structure 500
have the following advantages. For example, the chip package
structure is fabricated by a wafer level package process to package
the chip array. Therefore, the chip package structure has much
smaller dimensions than that of the conventional wire-bonding type
chip package structure. When the chip package structure is arranged
in a pixel array for illumination or display, an exemplary
embodiment of the chip package structure may allow the pixel array
to have a smaller pitch between each light emitting device.
Therefore, improving pixel continuity and visual effect.
Additionally, the conductive path is constructed by laminated the
upper and lower holes, wherein the upper and lower holes further
comprise a lateral conductive layer therebetween to increase
conductive area of the hole conducting layers.
[0026] While the invention has been described by way of example and
in terms of the embodiments, it is to be understood that the
invention is not limited to the disclosed embodiments. To the
contrary, it is intended to cover various modifications and similar
arrangements (as would be apparent to those skilled in the art).
Therefore, the scope of the appended claims should be accorded the
broadest interpretation so as to encompass all such modifications
and similar arrangements.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] FIGS. 1A-1F are cross sections showing the steps for
fabricating a chip package structure according to an embodiment of
the invention.
SYMBOL DESCRIPTION OF THE DRAWINGS
[0028] 500.about.chip package structure; [0029] 200.about.carrier
substrate; [0030] 200a, 200b.about.surface; [0031] 202a', 202b',
202a'', 202b''.about.hole; [0032] 203.about.cavity; [0033] 204a',
204b', 204a'', 204b''.about.insulating layer; [0034] 206a', 206b',
206a'', 206b'', 206c''.about.hole conducting layer; [0035] 208a',
208b', 208a'', 208b''.about.filling layer; [0036] 301.about.chip
array; [0037] 302a, 302b.about.chip; [0038] 310a, 311a.about.first
electrode; [0039] 310b, 311b.about.second electrode; [0040]
320a.about.first conductive path; [0041] 320b.about.second
conductive path; [0042] 324.about.adhesive layer; [0043]
336.about.fluorescent layer; [0044] 338.about.lens structure.
* * * * *