U.S. patent application number 12/350924 was filed with the patent office on 2010-07-08 for slew rate control circuit.
Invention is credited to Yaw-Guang Chang, Lieh-Chiu Lin.
Application Number | 20100171539 12/350924 |
Document ID | / |
Family ID | 42311288 |
Filed Date | 2010-07-08 |
United States Patent
Application |
20100171539 |
Kind Code |
A1 |
Chang; Yaw-Guang ; et
al. |
July 8, 2010 |
SLEW RATE CONTROL CIRCUIT
Abstract
A slew rate control circuit is disclosed. An output impedance
buffer and a slew rate buffer are coupled in parallel. An edge
detector detects an input signal to accordingly control the output
impedance buffer and the slew rate buffer, such that the input
signal passes through the slew rate buffer during a rising or
falling time period, and the input signal only passes through the
output impedance buffer during a stable time period, thereby
conforming to specification requirements for the slew rate and the
output impedance at the same time.
Inventors: |
Chang; Yaw-Guang; (Tainan,
TW) ; Lin; Lieh-Chiu; (Tainan, TW) |
Correspondence
Address: |
STOUT, UXA, BUYAN & MULLINS LLP
4 VENTURE, SUITE 300
IRVINE
CA
92618
US
|
Family ID: |
42311288 |
Appl. No.: |
12/350924 |
Filed: |
January 8, 2009 |
Current U.S.
Class: |
327/170 |
Current CPC
Class: |
H03K 19/00361 20130101;
H03K 5/04 20130101 |
Class at
Publication: |
327/170 |
International
Class: |
H03K 5/12 20060101
H03K005/12 |
Claims
1. A slew rate control circuit, comprising: an output impedance
buffer; a slew rate buffer coupled in parallel to the output
impedance buffer; and an edge detector that detects an input signal
to accordingly control the output impedance buffer and the slew
rate buffer, such that the input signal passes through the slew
rate buffer during a rising or falling time period, and the input
signal only passes through the output impedance buffer during a
stable time period; wherein the edge detector, according to rising
or falling of the input signal, generates at least one output
impedance enable signal to enable the output impedance buffer, and
at least one slew rate enable signal to enable the slew rate
buffer.
2. The slew rate control circuit of claim 1, wherein an output of
the output impedance buffer and an output of the slew rate buffer
are added to be an output of the slew rate control circuit.
3. The slew rate control circuit of claim 2, wherein the output of
the slew rate control circuit is rising or falling toward a
substantial proportion of a required level during the rising or
falling time period, and the output of the slew rate control
circuit is substantially maintained at a high or low level during
the stable time period.
4. The slew rate control circuit of claim 1, wherein the input
signal further passes through the output impedance buffer during
the rising or falling time period.
5. The slew rate control circuit of claim 1, wherein an output
impedance and slew rate of the slew rate control circuit are in
conformity with Mobile Industry Processor Interface (MIPI)
specifications.
6. The slew rate control circuit of claim 1, wherein the output
impedance buffer has an output impedance greater than the slew rate
buffer, and the slew rate buffer has a slew rate greater than the
output impedance buffer.
7. (canceled)
8. The slew rate control circuit of claim 1, wherein the output
impedance enable signal enables the output impedance buffer during
the stable time period, and the slew rate enable signal enables the
slew rate buffer during the rising or falling time period.
9. The slew rate control circuit of claim 8, wherein the output
impedance enable signal further enables the output impedance buffer
during the rising or falling time period.
10. A slew rate control circuit, comprising: an output impedance
buffer including a p-type transistor and an n-type transistor
connected in series between a positive power supply and a negative
power supply; a slew rate buffer coupled in parallel to the output
impedance buffer, the slew rate buffer including a p-type
transistor and an n-type transistor connected in series between the
positive power supply and the negative power supply; and an edge
detector that detects an input signal to accordingly control the
output impedance buffer and the slew rate buffer, such that the
input signal is regenerated through the slew rate buffer during a
rising or falling time period, and the input signal is only
regenerated through the output impedance buffer during a stable
time period; wherein an interconnection node of the p-type
transistor and the n-type transistor of the output impedance buffer
are coupled to an interconnection node of the p-type transistor and
the n-type transistor of the slew rate buffer, and is used as an
output of the slew rate control circuit; wherein the edge detector,
according to rising or falling of the input signal, generates at
least two output impedance enable signals to respectively enable
the p-type transistor and the n-type transistor of the output
impedance buffer, and at least two slew rate enable signals to
respectively enable the p-type transistor and the n-type transistor
of the slew rate buffer.
11. The slew rate control circuit of claim 10, wherein the output
of the slew rate control circuit is pulling up or pulling down
toward a substantial proportion of a required level during the
rising or falling time period, and the output of the slew rate
control circuit is substantially maintained at a high or low level
during the stable time period.
12. The slew rate control circuit of claim 10, wherein the input
signal is further regenerated through the output impedance buffer
during the rising or falling time period.
13. The slew rate control circuit of claim 10, wherein an output
impedance and slew rate of the slew rate control circuit are in
conformity with Mobile Industry Processor Interface (MIPI)
specifications.
14. The slew rate control circuit of claim 10, wherein the output
impedance buffer has an output impedance greater than the slew rate
buffer, and the slew rate buffer has a slew rate greater than the
output impedance buffer.
15. (canceled)
16. The slew rate control circuit of claim 10, wherein the output
impedance enable signals enable the output impedance buffer during
the stable time period, and the slew rate enable signals enable the
slew rate buffer during the rising or falling time period.
17. The slew rate control circuit of claim 16, wherein the output
impedance enable signals further enable the output impedance buffer
during the rising or falling time period.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention generally relates to the output stage
of a circuit, and more particularly to a slew rate control circuit
for a high-speed low-power transmitter.
[0003] 2. Description of the Prior Art
[0004] A Mobile Industry Processor Interface (MIPI) is a high-speed
low-power (LP) serial transceiver interface developed to support
interconnections of low-power high-speed mobile applications such
as for digital camera, display or other portable devices. A D-PHY
specification further defines physical layer devices that transport
high-speed data on the link between the transmitters and the
receivers.
[0005] The MIPI specification regulates, among other things, the
slew rate and the output impedance (R.sub.out) of a transmitter
(Tx).
[0006] The slew rate is the maximum rate of change of a signal in a
circuit. Low slew rate causes signal distortion. On the other hand,
the output impedance of a transmitter should be as large as
possible such that the output of the transmitter may not be
affected by an external load. In general, for designing a practical
circuit, such as the MIPI low-power transmitter (LP Tx) mentioned
above, a compromise between the slew rate and the output impedance
should be reached. According to the MIPI specification, the slew
rate of a transmitter with a load of capacitance of 0-70 pF should
be within a specific range, and the output impedance should be not
less than a specific value. In order to be in conformity with both
the slew rate and the output impedance, the design of a MIPI
low-power transmitter thus becomes complex and costly.
[0007] FIG. 1 shows a schematic circuit illustrating the output
stage of a MIPI transmitter. In the figure, a capacitor 10 and a
resistor 12 are connected between the output node and the input
node as shown to compromisingly arrive at an acceptable slew rate
and output impedance. Unfortunately, when the external load
increases, the transmitter may necessarily be designed to increase
its output to maintain the slew rate, while disadvantageously
decreasing its output impedance at the same time. In other words,
the slew rate and the output impedance usually affect each other in
a manner that a designer would prefer mostly to avoid.
[0008] For the reason that conventional circuit, such as a MIPI
transmitter, could not be effectively designed without using
complex circuitry to reach an acceptable tradeoff between the slew
rate and the output impedance, a need thus has arisen to propose a
high-speed interface circuit that can take account of the slew rate
and the output impedance at the same time.
SUMMARY OF THE INVENTION
[0009] In view of the foregoing, it is an object of the present
invention to provide an uncomplicated and inexpensive interface
circuit that is capable of making the output stage of a circuit,
such as a low-power transmitter, conform to specification
requirements for the slew rate and the output impedance at the same
time.
[0010] According to one embodiment, an output impedance buffer and
a slew rate buffer are coupled in parallel, and the output of the
output impedance buffer and the output of the slew rate buffer are
added to be an output of the whole slew rate control circuit. An
edge detector detects an input signal to accordingly control the
output impedance buffer and the slew rate buffer. As a result, the
input signal passes through the slew rate buffer during a rising or
falling time period, during which the output of the slew rate
control circuit is rising or falling toward a substantial
proportion of a required level; the input signal only passes
through the output impedance buffer during a stable time period,
during which the output of the slew rate control circuit is
substantially maintained at a required high or low level.
Accordingly, the slew rate and the output impedance of the slew
rate control circuit can be in conformity with the specification
requirements of, for example, the MIPI specification, at the same
time.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 shows a schematic circuit illustrating the output
stage of a conventional MIPI transmitter (Tx);
[0012] FIG. 2 is a block diagram of a slew rate control circuit
according to one embodiment of the present invention;
[0013] FIG. 3 shows various signal waveforms associated with the
slew rate control circuit of FIG. 2;
[0014] FIG. 4 shows a schematic circuit illustrating an exemplary
slew rate control circuit according to one embodiment of the
present invention; and
[0015] FIG. 5 shows various signal waveforms associated with the
slew rate control circuit of FIG. 4.
DETAILED DESCRIPTION OF THE INVENTION
[0016] FIG. 2 illustrates in block-diagram format a slew rate
control circuit 20 according to one embodiment of the present
invention, and FIG. 3 shows various signal waveforms associated
with the slew rate control circuit 20. It is appreciated that an
input signal (in) having a waveform other than the depicted square
wave, such as a sinusoidal wave, may also be processed by the slew
rate control circuit 20. The slew rate control circuit 20 is
capable of making the output stage of a circuit, such as a
low-power transmitter, conform to the specification requirements
for the slew rate and the output impedance at the same time.
Although the embodiment is described in the context of applying a
Mobile Industry Processor Interface (MIPI) specification, which is
a high-speed low-power (LP) serial transceiver interface developed
to support interconnections of low-power high-speed mobile
applications, the present invention can be well adapted to other
transceivers or, in general, the output stage of a circuit.
[0017] In the embodiment, the slew rate control circuit 20 includes
an output impedance (R.sub.out) buffer 202 that conforms to the
output impedance specification requirement of, for example, the
MIPI specification. The slew rate control circuit 20 also includes
a slew rate buffer 204 that conforms to the slew rate specification
requirement of the MIPI specification. The output impedance buffer
202 and the slew rate buffer 204 are coupled in parallel such that
the respective input nodes are connected together to receive an
input signal (in), and the output (R) of the output impedance
buffer 202 and the output (SR) of the slew rate buffer 204 are
added up as the output signal (out) of the slew rate control
circuit 20. In practice, the output nodes of the output impedance
buffer 202 and the slew rate buffer 204 may be coupled together to
perform the addition without using any real adder 206.
[0018] The slew rate control circuit 20 further includes an edge
detector 208 that detects the rising edges and the falling edges of
the input signal (in). In the embodiment, the edge detector 208
generates at least an output impedance enable signal EN_R and a
slew rate enable signal EN_SR according to the rising/falling
edges. The output impedance enable signal EN_R is used to enable
the output impedance buffer 202, and the slew rate enable signal
EN_SR is used to enable the slew rate buffer 204. As shown in FIG.
3, the slew rate enable signal EN_SR becomes active, or high, for a
specific period of time whenever the input signal (in) is rising or
falling, for example, during a period from t1 to t2. The specific
period of time is set to be long enough for the output signal (out)
to rise or fall a substantial proportion (for example, 80%) of the
required level. The output impedance enable signal EN_R becomes
active, or high, whenever the input signal (in) is stable, for
example, during a period from t2 to t3. The output impedance enable
signal EN_R may be active or inactive when the input signal (in) is
rising or falling, for example, during the period from t1 to t2. In
one embodiment, the output impedance enable signal EN_R (30) is
always active. In another embodiment, the output impedance enable
signal EN_R (32) becomes active only when the slew rate enable
signal EN_SR becomes inactive, or low.
[0019] According to FIG. 3, when the rising edge is detected (for
example, at time t1), the slew rate buffer 204 is enabled (by the
active signal EN_SR) such that the input signal (in) primarily
passes through the slew rate buffer 204, which provides a greater
slew rate than the output impedance buffer 202. In one embodiment,
the input signal (in) passes through both the slew rate buffer 204
and the output impedance buffer 202 at time t1. In another
embodiment, the input signal (in) only passes through the slew rate
buffer 204 at time t1. At this time, the output (SR), or slew rate,
of the slew rate buffer 204 is pulled high, and the output signal
(out) thus rises correspondingly with a slew rate large enough to
be in conformity with the MIPI specification.
[0020] Subsequently, for example, at time t2, the signal EN_SR
becomes inactive to disable the slew rate buffer 204, and the
output (SR) of the slew rate buffer 204 is off or with high
impedance (Hi-Z). At this time, the input signal (in) solely passes
through the output impedance buffer 202, and the output signal
(out) thus stays high with an output impedance large enough to be
in conformity with the MIPI specification.
[0021] When the falling edge is detected (for example, at time t3),
the slew rate buffer 204 is enabled again (by the active signal
EN_SR) such that the input signal (in) primarily passes through the
slew rate buffer 204. At this time, the output (SR) of the slew
rate buffer 204 is pulled low, and the output signal (out) thus
falls correspondingly with a slew rate large enough to be in
conformity with the MIPI specification.
[0022] Subsequently, for example, at time t4, the signal EN_SR
becomes inactive again to disable the slew rate buffer 204, and the
output (SR) of the slew rate buffer 204 is off or with high
impedance (Hi-Z). At this time, the input signal (in) solely passes
through the output impedance buffer 202, and the output signal
(out) thus stays low with an output impedance large enough to be in
conformity with the MIPI specification.
[0023] According to the embodiment discussed above, the input
signal (in) primarily passes through the slew rate buffer 204
during the rising/falling time period (for example, t1 to t2) such
that the slew rate specification requirement of, for example, the
MIPI specification, can be met. Subsequently, the input signal (in)
solely passes through the output impedance buffer 202 during the
stable time period (for example, t2 to t3) such that the output
impedance specification requirement of, for example, the MIPI
specification, can be met.
[0024] FIG. 4 shows a schematic circuit illustrating an exemplary
slew rate control circuit 20A according to one embodiment of the
present invention, and FIG. 5 shows various signal waveforms
associated with the slew rate control circuit 20A. In the
embodiment, the slew rate control circuit 20A includes an output
impedance buffer 202A that conforms to the output impedance
specification requirement of, for example, the MIPI specification.
The output impedance buffer 202A includes a p-type transistor Rp
and an n-type transistor Rn connected in series between a positive
power supply V.sub.DD and a negative power supply V.sub.SS. The
slew rate control circuit 20A also includes a slew rate buffer 204A
that conforms to the slew rate specification requirement of the
MIPI specification. The slew rate buffer 204A includes a p-type
transistor SRp and an n-type transistor SRn connected in series
between the positive power supply V.sub.DD and the negative power
supply V.sub.SS. The output impedance buffer 202A and the slew rate
buffer 204A are coupled in parallel between the positive power
supply V.sub.DD and the negative power supply V.sub.SS. The
interconnection node of the transistors SRp and SRn is coupled to
the interconnection node of the transistors Rp and Rn, and is used
as the output (out).
[0025] The slew rate control circuit 20A further includes an edge
detector 208A that receives and detects the rising edges and the
falling edges of the input signal (in). In the embodiment, the edge
detector 208A generates output impedance enable signals EN_R_H and
EN_R_L coupled respectively to the transistors Rp and Rn, and
generates slew rate enable signals EN_SR_H and EN_SR_L coupled
respectively to the transistors SRp and SRn according to the
rising/falling edges. The output impedance enable signals EN_R_H
and EN_R_L are together used to enable the output impedance buffer
202A, and the slew rate enable signals EN_SR_H and EN_SR_L are
together used to enable the slew rate buffer 204A.
[0026] According to FIG. 5, when the rising edge is detected (for
example, at time t1), the slew rate buffer 204A is enabled with low
(0) slew rate enable signals EN_SR_H and EN_SR_L, such that the
output signal (out) is pulled high. Equivalently speaking, the
input signal (in) is regenerated through the slew rate buffer 204A.
At this time, the output impedance buffer 202A is disabled with
high (1) output impedance enable signal EN_R_H (50) and low (0)
enable signal EN_R_L. In another embodiment, the output impedance
buffer 202A is also enabled with low (0) output impedance enable
signals EN_R_H (52) and EN_R_L.
[0027] Subsequently, for example, at time t2, the slew rate buffer
204A is disabled with high (1) slew rate enable signal EN_SR_H and
low (0) enable signal EN_SR_L, such that the slew rate buffer 204A
has high impedance (Hi-Z). At this time, the output impedance
buffer 202A is enabled with low (0) output impedance enable signals
EN_R_H and EN_R_L, such that the output signal (out) is kept high.
Equivalently speaking, the input signal (in) is regenerated through
the output impedance buffer 202A.
[0028] When the falling edge is detected (for example, at time t3),
the slew rate buffer 204A is enabled again with high (1) slew rate
enable signals EN_SR_H and EN_SR_L, such that the output signal
(out) is pulled low. At this time, the output impedance buffer 202A
is disabled with high (1) output impedance enable signal EN_R_H
(50) and low (0) enable signal EN_R_L. In another embodiment, the
output impedance buffer 202A is also enabled with low (0) output
impedance enable signals EN_R_H (52) and EN_R_L.
[0029] Subsequently, for example, at time t4, the slew rate buffer
204A is disabled with high (1) slew rate enable signal EN_SR_H and
low (0) enable signal EN_SR_L, such that the slew rate buffer 204A
has high impedance (Hi-Z). At this time, the output impedance
buffer 202A is enabled with high (1) output impedance enable
signals EN_R_H and EN_R_L, such that the output signal (out) is
kept low.
[0030] It is noted, in the embodiment, that the slew rate buffer
204A should avoid shorting between V.sub.DD and V.sub.SS with low
(0) slew rate enable signal EN_SR_H and high (1) enable signal
EN_SR_L. The output impedance buffer 202A should also avoid
shorting between V.sub.DD and V.sub.SS with low (0) output
impedance enable signal EN_R_H and high (1) enable signal
EN_R_L.
[0031] The input signal (in), the output signal (out), the various
enable signals, and the buffers 202A and 204A in different times
are summarized in the following Table 1.
TABLE-US-00001 TABLE 1 t1 t2 t3 t4 in rising high falling low
R.sub.out buffer disabled, enabled, disabled, enabled, Hi-Z pull
high Hi-Z pull low or or enabled, enabled, pull high pull low
EN_R_H 1/0 0 1 1 EN_R_L 0/0 0 0 1 SR buffer enabled, disabled,
enabled, disabled, pull high Hi-Z pull low Hi-Z EN_SR_H 0 1 1 1
EN_SR_L 0 0 1 0 out rising high falling low
[0032] According to the embodiment discussed above, the input
signal (in) primarily passes through the slew rate buffer 204A
during the rising/falling time period such that the slew rate
specification requirement of, for example, the MIPI specification,
can be met. Subsequently, the input signal (in) solely passes
through the output impedance buffer 202A during the stable time
period such that the output impedance specification requirement of,
for example, the MIPI specification, can be met.
[0033] Although specific embodiments have been illustrated and
described, it can be appreciated by those skilled in the art that
various modifications may be made without departing from the scope
and spirit of the present invention, which is intended to be
limited solely by the appended claims.
* * * * *