U.S. patent application number 12/529473 was filed with the patent office on 2010-06-24 for memory system.
This patent application is currently assigned to Kabushiki Kaisha Toshiba. Invention is credited to Kosuke Hatsuda, Yasushi Nagadomi, Daisaburo Takashima.
Application Number | 20100161881 12/529473 |
Document ID | / |
Family ID | 41056177 |
Filed Date | 2010-06-24 |
United States Patent
Application |
20100161881 |
Kind Code |
A1 |
Nagadomi; Yasushi ; et
al. |
June 24, 2010 |
MEMORY SYSTEM
Abstract
A memory system (10) is disclosed, which comprises a
flash-EEPROM nonvolatile memory (11) having a plurality of memory
cells that have floating gates and in which data items are
electrically erasable and writable, a cache memory (13) that
temporarily stores data of the flash-EEPROM nonvolatile memory
(11), a control circuit (12, 14) that controls the flash-EEPROM
nonvolatile memory (11) and the cache memory (13), and an interface
circuit (16) that communicates with a host, in which the control
circuit functions to read data from a desired target area
to-be-determined of the flash-EEPROM nonvolatile memory and detect
an erased area to determine a written area/unwritten area by using
as a determination condition whether or not a count number of data
"0" of the read data has reached a preset criterion count
number.
Inventors: |
Nagadomi; Yasushi;
(Yokohama-shi, JP) ; Takashima; Daisaburo;
(Yokohama-shi, JP) ; Hatsuda; Kosuke; (Tokyo,
JP) |
Correspondence
Address: |
OBLON, SPIVAK, MCCLELLAND MAIER & NEUSTADT, L.L.P.
1940 DUKE STREET
ALEXANDRIA
VA
22314
US
|
Assignee: |
Kabushiki Kaisha Toshiba
Minato-ku, Tokyo
JP
|
Family ID: |
41056177 |
Appl. No.: |
12/529473 |
Filed: |
March 3, 2009 |
PCT Filed: |
March 3, 2009 |
PCT NO: |
PCT/JP2009/054375 |
371 Date: |
September 1, 2009 |
Current U.S.
Class: |
711/103 ;
711/E12.008 |
Current CPC
Class: |
G06F 11/1016 20130101;
G11C 16/102 20130101; G06F 2212/7203 20130101; G06F 2212/7209
20130101; G06F 12/0246 20130101 |
Class at
Publication: |
711/103 ;
711/E12.008 |
International
Class: |
G06F 12/02 20060101
G06F012/02 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 7, 2008 |
JP |
2008-058549 |
Claims
1. A memory system comprising a flash-EEPROM nonvolatile memory
having a plurality of memory cells that have floating gates and in
which data items are electrically erasable and writable, a cache
memory that temporarily stores data of the flash-EEPROM nonvolatile
memory, a control circuit that controls the flash-EEPROM
nonvolatile memory and the cache memory, and an interface circuit
that communicates with a host, in which the control circuit
functions to read data from a desired target area to-be-determined
of the flash-EEPROM nonvolatile memory and detect an erased area to
determine a written area/unwritten area by using as a determination
condition whether or not a count number of data "0" of the read
data has reached a preset criterion count number.
2. The memory system according to claim 1, wherein the control
circuit further has a function of using an identification number
added to data to be written into the flash-EEPROM memory as the
determination condition.
3. The memory system according to claim 1, wherein the control
circuit has a function of transferring read data from the target
area to the cache memory.
4. The memory system according to claim 1, wherein the control
circuit has a function of variably changing the preset criterion
count number of data "0".
5. The memory system according to claim 4, wherein the control
circuit further has a function of using an identification number
added to data to be written into the flash-EEPROM memory as the
determination condition.
6. The memory system according to claim 4, wherein the control
circuit includes a setting register functioning as means for
variably changing the criterion count number of data "0", and a "0"
data count module that counts the count number of data "0" of the
read data and functions to compare the criterion count number set
by the setting register with the count number of data "0" counted
by the "0" data count module to detect an erased area and determine
the written area/unwritten area.
7. The memory system according to claim 1, wherein the target area
is an individual memory block of the flash-EEPROM nonvolatile
memory and the control circuit reads data for each unit area of the
memory block that is the target area, determines whether the unit
area from which data is read is an erased area according to the
determination condition to determine a written area/unwritten
area.
8. The memory system according to claim 7, wherein one unit of the
memory block is a page unit and the data is read in an ascending
order of page addresses from individual pages of one memory
block.
9. The memory system according to claim 8, wherein the control
circuit determines whether a page from which data is read is an
erased page according to the determination condition to determine a
written area/unwritten area while transferring data read from the
individual pages to the cache memory.
10. The memory system according to claim 9, wherein the control
circuit interrupts transfer of read data to the cache memory and
reading of data from the flash-EEPROM nonvolatile memory when it is
determined that the page of the read data is an erased area.
11. The memory system according to claim 10, wherein the control
circuit further has a function of using a successive number of
erased pages as the determination condition.
12. The memory system according to claim 10, wherein the control
circuit further has a function of using an identification number
added to data to be written into the flash-EEPROM memory as the
determination condition.
13. The memory system according to claim 1, wherein the control
circuit further has a function of using an error correction result
based on an ECC system with respect to write data of the
flash-EEPROM nonvolatile memory as the determination condition.
14. The memory system according to claim 13, wherein the control
circuit further has a function of using an identification number
added to data to be written into the flash-EEPROM memory as the
determination condition.
Description
TECHNICAL FIELD
[0001] This invention relates to a memory system using a
flash-EEPROM nonvolatile memory, and more particularly to a memory
system that uses a NAND flash memory having an ascending-order
programming restriction and is used instead of a hard disk device,
for example.
BACKGROUND ART
[0002] At present, semiconductor memories are used in various
devices, including main memory devices of large-scale computers,
personal computers, home electrical appliances, mobile phones and
the like. Memories that are now dominantly used in the market are
flash-EEPROM nonvolatile memories, represented by NAND-Flash
memories. Since the flash-EEPROM nonvolatile memories are
configured to maintain data even if the power source is turned off
and have structures suitable for integration with high density,
they are now used in various information devices such as mobile
telephones and digital cameras. That is, the flash-EEPROM
nonvolatile memories are widely used as storage media for digital
cameras, digital video devices, portable personal computer and MP3
music devices, storage media for storing information items of
images, moving pictures, sound, games in digital television
receivers, or various memory cards (SD cards, MMC cards, MS cards,
CF cards and the like). Further, they are also widely used as
memories (USB memories) that are compatible with USB as storage
media of personal computers and memories of mobile telephones.
[0003] The flash-EEPROM nonvolatile memories are mainly divided
into. NOR memories (NOR flash memories) and NAND memories (NAND
flash memories). The NOR flash memory has a characteristic that the
number of read/read operations is approximately 10.sup.13 making it
suitable for use as a storage medium of instruction codes in a
mobile device. However, since the effective bandwidth of writing is
small, it is not suitable for file recording.
[0004] On the other hand, the NAND flash memory has a read
characteristic that the access time is approximately 25 .mu.s,
which is long, but it can be integrated with higher density in
comparison with the NOR flash memory. Further, burst reading can be
performed and the effective bandwidth is large. In the write
characteristic, the program time is 200 .mu.s and the erase time is
1 ms, which are long. However, since the number of bits that can be
simultaneously programmed or erased is large, write data can be
taken in by a burst operation and a large number of bits can be
simultaneously programmed in units of pages, the effective
bandwidth becomes large.
[0005] Since the NAND flash memory can be integrated with high
density so as to attain a large storage capacity, its use in place
of a hard disk has recently been considered. However, there are
some restrictions on usage. First, since data degradation occurs
due to writing/erasing (programming/erasing), there are
restrictions on the number of writable/erasable operations. That
is, in the program operation of the NAND flash memory, electrons
are injected into the floating gate by applying a high voltage to
the gate of a memory cell transistor with respect to the substrate.
If the above operations are repeatedly performed, an oxide film
around the floating gate of the memory cell transistor is degraded
and data is destroyed. In the NAND flash memory now used, the
number of writable/erasable operations is approximately 10.sup.5
and is extremely small in comparison with that of other types of
nonvolatile memory. Further, it is predicted that the number of
writable/erasable operations will be further reduced with
miniaturization in the future processing and multivalue-coding of
cells. If the NAND flash memory is used as a memory card or USB
memory, it takes a relatively long time to make approximately
10.sup.5 accesses, thus the NAND flash memory can be used in
practice. However, if the NAND flash memory is mounted in a system
and used instead of a hard disk, accesses of approximately 10.sup.5
times will occur in a relatively short period of time.
[0006] Further, a restriction of rewriting inhibition is imposed on
the NAND flash memory. That is, programming of the NAND flash
memory can be controlled only in the direction (the direction of
data "1".fwdarw.data "0": "0" writing) in which electrons are
injected into the floating gate and erasing must be performed when
electrons are extracted (the direction of data "0".fwdarw.data "1":
"1" writing). At this time, generally, programming is performed in
page units but erasing can be performed only in block units,
comprised of several pages. Therefore, when data of a programmed
page is changed, it is necessary to temporarily save the entire
amount of data in a block containing the page of the data to be
changed into another area, erase the data and then perform the
program operation again. In practice, since the number of
rewritable/erasable operations is restricted, the program/erase
operations are prevented from being excessively performed by
writing a to-be-rewritten page into another erased area and
managing the same by using a logical-physical conversion table.
[0007] As a further restriction condition of the NAND flash memory,
page reverse-order programming is inhibited in the NAND flash
memory. For example, there is a restriction that programming must
be performed in an ascending order from the page address "0" when
programming is performed in a block.
[0008] When a memory system using the above NAND flash memory is
configured, particularly, when a memory system used instead of a
hard disk is configured, at present, the memory system is often
configured by a volatile RAM for data cache and management
information storage and a NAND flash memory for nonvolatile main
storage. With the above configuration, since a command (flash cache
command) for saving data of the volatile memory area into the
nonvolatile memory area is frequently issued from the host side as
a countermeasure against instantaneous turn-off of the memory
system, it resultantly becomes necessary to add an updating portion
of management information (that is hereinafter referred as a
management log) into the NAND flash memory.
[0009] In the above memory system, it is necessary to extract the
newest information from the management log written into the NAND
flash memory and reconstruct management information each time the
power source is turned on. At this time, it is necessary to grasp
the boundary of a storage area of the management log in the memory
area indicating a portion of the memory area to which the storage
area of the management log extends in the memory area, that is, the
range of a valid information storage area.
[0010] Further, recently, a configuration is proposed in which a
nonvolatile RAM (for example, FeRAM, MRAM or the like) for data
cache and management information storage and a NAND flash memory
are combined based on the large capacity of the nonvolatile RAM and
the various restriction conditions of the NAND flash memory. With
this configuration, a problem relating to the management log as
described before can be avoided by arranging management information
that is frequently rewritten on the nonvolatile RAM. However, it is
necessary to grasp data that has been written, that is, one of the
pages that has been programmed in the block when the memory system
is instantaneously turned off while data is being written into the
NAND flash memory.
[0011] In "Semiconductor Device containing Flash Memory, Control
Method of Flash Memory and Programming thereof", Jpn. Pat. Appln.
KOKAI Publication No. 2004-310268, it is disclosed that storage of
newest data having a given data length is additionally provided in
a block of the flash memory erase unit. As a concrete example,
storage data is searched for while addresses are changed in units
of words from the start address of the block to the end address
when data rewriting is performed in each erase block unit, and if
the searched data items are all set at the logical level "1", which
indicates the erase state, newest data items are sequentially
written from the start address. On the other hand, when the
searched data is set in the non-erase state, newest data is written
from an address value if a derived address value derived by adding
a preset numerical value to the address value is smaller than the
end address value. On the other hand, if the derived address value
derived by addition is larger than the end address value, data of
the block is erased and newest data is written from the start
address.
[0012] Further, in "Semiconductor Memory Device and Blank Page
Searching Method thereof", Publication No. 2005-353171, a method
for detecting a blank page in which the entire page is set in a
data initial state (erased state) at high speed without reading
data in the page in units of bytes is disclosed. As a concrete
example, the potential of a bit line is sensed at the time of
reading data from the memory cell, data of a selected memory cell
is determined and the determined data is held in a data buffer.
Then, whether or not all of the data buffers hold "0" data and
whether or not all of the data buffers hold "1" data are both
detected.
[0013] Jpn. Pat. Appin. KOKAI Publication No. 2004-310268 and Jpn.
Pat. Appin. KOKAI Publication No. 2005-353171 propose a method for
solving the problem by performing a process in the NAND flash
memory.
DISCLOSURE OF INVENTION
[0014] This invention has been made to solve the conventional
problems described above and an object of this invention is to
provide a memory system capable of detecting the boundary between a
data storage area (valid area of write data) and a data non-storage
area (invalid area of write data) by detecting an erased page when
data is stored in a flash-EEPROM nonvolatile memory.
[0015] According to one aspect of this invention, there is provided
a memory system comprising a flash-EEPROM nonvolatile memory having
a plurality of memory cells that have floating gates and in which
data items are electrically erasable and writable, a cache memory
that temporarily stores data of the flash-EEPROM nonvolatile
memory, a control circuit that controls the flash-EEPROM
nonvolatile memory and the cache memory, and an interface circuit
that communicates with a host, in which
[0016] the control circuit functions to read data from a desired
target area to-be-determined of the flash-EEPROM nonvolatile memory
and detect an erased area to determine a written area/unwritten
area by using as a determination condition whether or not a count
number of data "0" of the read data has reached a preset criterion
count number.
BRIEF DESCRIPTION OF DRAWINGS
[0017] FIG. 1 is a block diagram of a memory system according to a
first embodiment of the present invention.
[0018] FIG. 2 is a diagram showing one example of a flowchart of
processing steps in the memory system of FIG. 1.
[0019] FIG. 3 is a diagram showing part of the configuration of the
memory system of FIG. 1 and one example of a data processing
operation.
[0020] FIG. 4 is a diagram showing one example of a flowchart of
processing steps in a memory system of a second embodiment of the
present invention.
[0021] FIG. 5 is a diagram showing one example of a flowchart of
processing steps in a memory system of a third embodiment of the
present invention.
[0022] FIG. 6 is a diagram showing part of the configuration of the
memory system of the third embodiment and one example of a data
processing operation.
[0023] FIG. 7 shows one example of a flowchart of processing steps
in a memory system of a fourth embodiment of the present
invention.
[0024] FIG. 8 shows part of the configuration of the memory system
of the fourth embodiment and one example of a data processing
operation.
[0025] FIG. 9 shows one example of a flowchart of processing steps
in a memory system of a fifth embodiment of the present
invention.
[0026] FIG. 10 shows part of the configuration of the memory system
of the fifth embodiment and one example of a data processing
operation.
[0027] FIG. 11 shows an example of the flash-EEPROM nonvolatile
memory of the memory system.
BEST MODE FOR CARRYING OUT THE INVENTION
[0028] There will now be described embodiments of the present
invention with reference to the drawings. In the description,
common reference symbols are attached to common portions throughout
the drawings.
First Embodiment
[0029] FIG. 1 is a block diagram showing a memory system according
to a first embodiment of the present invention. FIG. 2 shows one
example of a flowchart of processing steps in the memory system of
FIG. 1. FIG. 3 shows part of the configuration of the memory system
of FIG. 1 and one example of a data processing operation.
[0030] As shown in FIG. 1, a memory system 10 includes a
flash-EEPROM (electrically erasable and programmable read only
memory) nonvolatile memory (in this example, NAND flash memory) 11
having a plurality of memory cells each of which has a floating
gate and in which data can be electrically erased and written, a
cache memory (in this example, DRAM (dynamic random access memory))
13 that temporarily stores data of the NAND flash memory 11, a
control circuit 17 (NAND memory controller 12, DRAM controller 14)
that controls the above two types of memories, an MPU (micro
processor unit) 15, and an interface circuit IF 16 that
communicates with a host computer. The NAND flash memory is
integrated with high density and has a large capacity and the DRAM
has a higher read/write speed in comparison with a flash memory and
has a medium capacity.
[0031] The MPU 15 has a function of setting information (start
address, the number of transfer pages) of a target area of the NAND
flash memory 11 in which an erased page is to be detected and an
erased page detection mode into the NAND memory controller 12.
[0032] As shown in FIG. 3, the NAND memory controller 12 includes a
control register 31, NAND-IF control module 32 and direct memory
access controller (DMAC) 33. The NAND-IF control module 32 includes
a "0" data count module ("0" data counter) 34, a sequence control
circuit (sequencer) 35 that controls the procedure of processing
operations, and the like.
[0033] The NAND memory controller 12 has a function of determining
a written/unwritten area of the NAND flash memory 11 by determining
an erased area of the NAND flash memory 11. In this example, the
NAND memory controller 12 has a function of counting the number of
data items "0" for each page in the NAND memory controller 12 while
sequentially reading data items from the start address of the
target area of the NAND flash memory 11 to the DRAM 13.
[0034] As the cache memory 13, either a volatile memory (such as a
DRAM or SRAM) or nonvolatile memory (such as an FeRAM, MRAM, PRAM
or RRAM) can be used.
[0035] In the process of the memory system of FIG. 1, first, the
MPU 15 sets information (start address, the number of transfer
pages) of a target area of the NAND flash memory 11 in which an
erased page is to be detected and an erased page detection mode
(Erase detection mode) into the NAND memory controller 12. Thus,
the NAND memory controller 12 sequentially reads data items from
the NAND flash memory 11 starting from the start position of the
target area (in an ascending order from the page address "0") and
starts page transfer. Since a page reverse-order programming
inhibition restriction is set in the NAND flash memory 11, the NAND
memory controller 12 reads data items starting from the page
address "0" in an ascending order in the same block, that is,
sequentially reads data items from the respective addresses in an
address order in which data is first read from the page address
"0", then data is read from the page address "1", data is read from
the page address "2" and the like. In this example, the NAND memory
controller 12 controls so that data is transferred from the NAND
flash memory 11 to the DRAM 13 and the number of data items "0" for
each page is counted in the NAND memory controller 12. At this
time, if the target area is a written page, "0" data is generally
mixed in with data itself read from the page. Therefore, when the
number of data items "0" at the time of page transfer of data read
from the NAND flash memory 11 is 0, it is regarded that the erased
page is detected and the address thereof is stored in the control
register 31 of the NAND memory controller 12. In this case, if it
is detected that a page of a certain address is an erased page, it
can be determined that pages of the addresses after the above
address are erased pages based on the page reverse-order
programming inhibition restriction. That is, the boundary between
validity and invalidity of write data can be determined. In other
words, since the data items stored in each page in the erased state
are all "1" data items, data is read from an area in which the
validity/invalidity of data is to be determined by the NAND memory
controller 12, data "0" is counted for each unit area (one page) in
the NAND memory controller 12, and it is determined that the unit
area is an erased page if the count number is 0. At this time,
since the page reverse-order programming inhibition restriction is
set in the NAND flash memory 11, an address at which an erased page
is first detected is held, and even if a new erased page is
detected in the following data transfer, the page address at which
the new erased page is detected is prevented from being written
over the page address at which the erased page is first detected.
The above detecting operation is continuously performed up to the
final page. Then, the erased page detection result is notified to
the MPU 15 by interruption or the like. As a result, the MPU 15
acquires a page address of erased page detection from the control
register 31, grasps the boundary of valid data and configures
management information.
[0036] In this embodiment, when in the erased page detection mode,
it is assumed that data read from the NAND flash memory 11 is
transferred to the DRAM 13. However, since there are some cases in
which it is desired to detect only an erased page address without
requiring data transfer, it is desirable to additionally provide a
mode option indicating whether read data is transferred to the DRAM
13 or not.
[0037] The above process can also be performed by the MPU 15
connected to the NAND flash memory 11. In this case, however, since
the time required for comparison of data items becomes long and
becomes an overhead for other processes, the function of the
process is provided on the NAND memory controller 12 in this
embodiment.
Second Embodiment
[0038] FIG. 4 shows one example of a flowchart of processing steps
in a memory system of a second embodiment of the present invention.
In comparison with the memory system of the first embodiment
described before, the memory system adds a function of immediately
interrupting transfer of erased page detection to the DRAM 13 and
reading from the NAND flash memory 11 in a case where an erased
page is detected in the same block when the number of data items
"0" is counted while transferring data of a target area in which an
erased page is to be detected to the DRAM 13 to a sequencer 35
(FIG. 3).
[0039] Determination of validity/invalidity of write data can be
made when an erased page is detected and since data after detection
of the erased page is invalid data (erased data), it is not
necessary to transfer the data to the DRAM 13. With this function,
the extra data transfer time can be omitted and a processing time
required in the system can be shortened.
Third Embodiment
[0040] FIG. 5 shows one example of a flowchart of processing steps
in a memory system of a third embodiment of the present invention.
FIG. 6 shows part of the configuration of the memory system of the
third embodiment and one example of a data processing
operation.
[0041] In the memory system of the first or second embodiment, the
count number of data "0" is set to a value not smaller than one as
a determination condition when the number of data "0" is counted
while transferring data of an area in which an erased page is to be
detected to the DRAM 13. In a NAND flash memory, it is common
practice to use an error correction (ECC: error check and
correction) circuit to take a countermeasure against aging
deterioration of data and deterioration of cells accompanied by an
increase in the number of writings during the operation. In this
case, the data of a portion of each erased page may be set to "0"
data even if the erase process is performed.
[0042] Therefore, in the memory system of the third embodiment, a
function of making a determination threshold value of the count
number of data "0" variable is provided. As one example of means
for realizing the above function, as shown in FIG. 6, a setting
register 62 that sets the count number of data "0" is provided in a
control register 61 of the NAND memory controller 12 and
determination is made by comparing the set value of the setting
register 62 with the count value of the "0" data count module 34
that counts data "0".
[0043] Thus, if the number of defective bits is previously known,
an erased page can be detected for a memory containing a defective
bit by setting the "0" count number set value in the setting
register 62 by the MPU 15.
Fourth Embodiment
[0044] FIG. 7 shows one example of a flowchart of processing steps
in a memory system of a fourth embodiment of the present invention.
FIG. 8 shows part of the configuration of the memory system of the
fourth embodiment and one example of a data processing
operation.
[0045] In the memory system the first to third embodiments, only
the count number of data "0" is used as the erased page detection
condition. On the other hand, recently, it is absolutely required
to add an ECC code to data at the time of usage of a NAND flash
memory. Further, in the NAND flash memory, a redundancy area used
to store ECC codes is provided in one page. Since an ECC code is
added to data written in the NAND flash memory and no ECC code is
added in an erased page, an ECC error naturally occurs.
[0046] Therefore, as shown in FIG. 8, in the memory system of the
fourth embodiment, an ECC module 81 is provided in a NAND memory
controller 12. Then, a function for selecting a creation polynomial
containing data "0" as an ECC code to be added to data even if data
items written in the NAND memory controller 12 are all "1" data and
determining the page being erased by using an ECC correction result
in addition to the count number of data "0" as an erased page
detection condition (determination condition) is provided in a
sequencer 35.
[0047] Then, even in a structure in which an ECC code is added to
data in view of the use of the NAND flash memory, the erased page
can be precisely detected by performing an erased page detection
process in two stages of determination based on the count number
obtained by counting the number of data "0" by using a "0" data
count module 34 and determination of presence or not of an ECC
error while transferring data read from a target area of the NAND
flash memory 11 in which an erased page is to be detected to the
DRAM 13.
Fifth Embodiment
[0048] FIG. 9 shows one example of a flowchart of processing steps
in a memory system of a fifth embodiment of the present invention
and FIG. 10 shows part of the configuration of the memory system of
the fifth embodiment and one example of a data processing
operation.
[0049] In comparison with the memory system of the fourth
embodiment, in the memory system of the fifth embodiment, a
function of adding an identification number to write data itself is
provided. As one example of a means for realizing the function, as
shown in FIG. 10, a module (identification number checking module)
101 that checks an identification number is provided in a NAND
memory controller 12 and an identification number containing a
plurality of data items "0" is provided when data is written into a
NAND flash memory 11. Since the data size of a log of management
information is not limited, it is easy to add the identification
number. On the other hand, if the data size of data from the host
side is determined (for example, the minimum unit of ATA that is
HDD IF is 512 B), it is previously determined so as to write an
identification number in the redundancy area of the NAND flash
memory 11.
[0050] Thus, the erased page can be more precisely detected by
adding a process of checking an identification number added to data
at the write time and an identification number added to data at the
read time when the read operation is performed for erase detection
and determining the data as valid (written) data at the time of
coincidence and as invalid (erased page) data at the time of
non-coincidence to the detection condition of the fourth embodiment
described before.
[0051] The method of writing the identification number in the write
data itself as described above can be applied to not only the
fourth embodiment but also the first to third embodiments.
Sixth Embodiment
[0052] Since a page reverse-order programming inhibition
restriction is set in a NAND flash memory, it is considered that a
page following after a page which is detected as an erased page is
an erased page in the same block. In the memory system of each of
the above embodiments described before, whether a page is an erased
page or not is independently determined in the page unit, but in
the sixth embodiment, a function of determining an erased page
based on the relation between plural pages is provided in a
sequencer 35.
[0053] For example, after an erased page is detected in the
detection condition of the first to fifth embodiments, and if the
next two pages are successively detected as erased pages (that is,
three successive pages are erased pages), it is determined that the
detected page is an erased page. In this case, a design is made to
set the number of successive pages ("3" in the above example) used
as a detection reference by use of a controller. However, even when
successive pages are set to plural pages and if an erased page is
detected in the remaining one page in the block, a process of
ignoring the number of successive pages as the detection condition
is performed.
[0054] FIG. 11 shows an example of the flash-EEPROM nonvolatile
memory 11 of the memory system described in each of the
embodiments, which is formed of a NAND flash memory. The
flash-EEPROM nonvolatile memory 11 comprises a plurality of NAND
cell units NU arranged in a matrix. Each of the NAND cell units
comprises a plurality of series-connected memory cell transistors
MC (in this example, MC0 to MC31). The NAND cell units NU arranged
in the row direction constitute a memory block BLK as a minimum
unit of data erase. In this example, memory blocks BLK0 to BLKn are
arranged in the row direction. Each of the memory cell transistors
MC has a floating gate electrode formed on a semiconductor
substrate via a tunnel insulating film, and a control gate
electrode laminated on the floating gate electrode via an
inter-gate insulating film.
[0055] One end of each NAND cell unit NU is connected to a
corresponding bit line BL via a selection gate transistor ST1, and
the other end thereof is connected to a common source line CELSRC
via a selection gate transistor ST2. The control gate electrodes of
the memory cell transistors MC of the same row extend in the memory
cell row direction and are connected in common to constitute a word
line WL (in this example, WL0 to WL31). The control gate electrodes
of the selection gate transistors ST1 of the NAND cell units NU in
the same block BLK extend in the memory cell row direction and are
connected in common to constitute a selection gate line SGD.
Similarly, the control gate electrodes of the selection gate
transistors ST2 of the NAND cell units NU in the same block BLK
extend in the memory cell row direction and are connected in common
to constitute a selection gate line SGS. The word lines WL, the
selection gate lines SGD and the selection gate lines SGS are
driven in accordance with address inputs supplied from the NAND
memory controller 12.
INDUSTRIAL APPLICABILITY
[0056] It is effective to apply the disclosed memory system to a
NAND flash memory that is restricted by various restriction
conditions since it is possible to detect the boundary between the
data storage area and the data non-storage area (the boundary
between the valid area and invalid area of write data) by detecting
an erased page when data is stored in the flash-EEPROM nonvolatile
memory that can be formed with a large capacity.
* * * * *