U.S. patent application number 12/639730 was filed with the patent office on 2010-06-17 for semiconductor memory device having selective activation circuit for selectively activating circuit areas.
This patent application is currently assigned to Elpida Memory, Inc.. Invention is credited to Makoto KITAYAMA.
Application Number | 20100149900 12/639730 |
Document ID | / |
Family ID | 42240338 |
Filed Date | 2010-06-17 |
United States Patent
Application |
20100149900 |
Kind Code |
A1 |
KITAYAMA; Makoto |
June 17, 2010 |
SEMICONDUCTOR MEMORY DEVICE HAVING SELECTIVE ACTIVATION CIRCUIT FOR
SELECTIVELY ACTIVATING CIRCUIT AREAS
Abstract
A semiconductor memory device includes a plurality of memory
banks each including a plurality of circuit areas selected based on
an address signal, any one of which is selected by a corresponding
bank selective signal (source transistor control signals), and a
selective activation circuit that, from among circuit areas
included in a memory bank that is selected based on the bank
selective signal, activates any one of the circuit areas based on
the address signal, and deactivates at least one of rest of the
circuit areas. According to the present invention, the power
consumption can be reduced in an active state by a dynamic power
control in response to an address signal, not by entire power
control by an external command.
Inventors: |
KITAYAMA; Makoto; (Chuo-ku,
JP) |
Correspondence
Address: |
SUGHRUE MION, PLLC
2100 PENNSYLVANIA AVENUE, N.W., SUITE 800
WASHINGTON
DC
20037
US
|
Assignee: |
Elpida Memory, Inc.
Tokyo
JP
|
Family ID: |
42240338 |
Appl. No.: |
12/639730 |
Filed: |
December 16, 2009 |
Current U.S.
Class: |
365/230.03 ;
365/226; 365/230.06 |
Current CPC
Class: |
G11C 11/4076 20130101;
G11C 8/08 20130101; G11C 11/408 20130101; G11C 11/4074
20130101 |
Class at
Publication: |
365/230.03 ;
365/230.06; 365/226 |
International
Class: |
G11C 8/00 20060101
G11C008/00; G11C 8/08 20060101 G11C008/08 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 17, 2008 |
JP |
2008-320637 |
Claims
1. A semiconductor memory device comprising: a plurality of memory
banks each including a plurality of circuit areas selected based on
an address signal, any one of the memory banks being selected by a
corresponding bank selective signal; and a selective activation
circuit that activates any one of the circuit areas and deactivates
at least one of remaining circuit areas based on the address signal
included in a memory bank that is selected based on the bank
selective signal.
2. The semiconductor memory device as claimed in claim 1, wherein
each of the circuit areas includes a main power source line, a sub
power source line, a switch circuit connected between the main
power source line and the sub power source line, and a logic
circuit connected to the main power source line and the sub power
source line, and the selective activation circuit turns on the
switch circuit that is included in a circuit area to be activated,
and turns off the switch circuit included in a circuit area to be
deactivated based on the address signal and the bank selective
signal.
3. The semiconductor memory device as claimed in claim 2, wherein
the main power source lines provided in the circuit areas are
commonly connected to each other and the sub power source lines
provided in the circuit areas are provided separately from one
another.
4. The semiconductor memory device as claimed in claim 1, wherein
each of the circuit areas includes a word driver, and the selective
activation circuit activates a selected word driver and deactivates
remaining word drivers based on a row address signal included in
the address signal and the bank selective signal.
5. The semiconductor memory device as claimed in claim 4, further
comprising a row pre-decoder that generates a pre-decode signal by
decoding a part of the row address signal, wherein each bit of the
pre-decode signal is associated one of the word drivers included in
each of the circuit areas, and the selective activation circuit
controls activation and deactivation of the word driver based on
the pre-decode signal and the bank selective signal.
6. The semiconductor memory device as claimed in claim 5, wherein
each of the circuit areas further includes a sense amplifier
controller that is selected even when any one of associated two or
more pre-decode signals is in an active state, and the selective
activation circuit activates a selected sense amplifier controller
and deactivates remaining amplifier controllers based on the
pre-decode signal and the bank selective signal.
7. The semiconductor memory device as claimed in claim 5, wherein
the bank selective signal is activated in response to an input of
the row address signal and deactivated in response to completion of
a sense operation of the memory bank, and the selective activation
circuit activates a word driver with at least one of the bank
selective signal and the corresponding pre-decode signal in an
activation state.
8. The semiconductor memory device as claimed in claim 1, wherein
each of the circuit areas includes a column select circuit, and the
selective activation circuit controls activation and deactivation
of the column select circuit based on a column address signal
included in the address signal and the bank selective signal.
9. The semiconductor memory device as claimed in claim 1, wherein
the circuit area activated by the selective activation circuit
generates an output signal in an active state when the address
signal indicating a predetermined value and generates the output
signal in an inactive state when the address signal indicating a
different value from the predetermined value, and the circuit area
deactivated by the selective activation circuit generates the
output signal in the inactive state regardless of the address
signal.
10. A semiconductor memory device comprising: a memory bank that
includes a plurality of memory cells each connected to an
associated one of word lines and an associated one of bit lines; a
row decoder that includes a plurality of word drivers and performs
selection of the word lines based on a row address; a column
decoder that performs selection of the bit lines based on a column
address; and a selective activation circuit that activates any one
of the word drivers and deactivates remaining word drivers based on
the row address, wherein each of the word drivers includes a main
power source line, a sub power source line, a switch circuit
connected between the main power source line and the sub power
source line, and a logic circuit that is connected to the main
power source line and the sub power source line, and the selective
activation circuit turns on the switch circuit that is included in
one of the word drivers to be activated, and turns off the switch
circuit included in the remaining word drivers to be
deactivated.
11. The semiconductor memory device as claimed in claim 10, wherein
the selective activation circuit once activates all of the word
drivers regardless of which one of the word drivers is to be
activated, and then deactivates the remaining word drivers.
12. The semiconductor memory device as claimed in claim 11, wherein
the selective activation circuit deactivates the rest of the word
drivers in response to completion of a sense operation of the
memory bank.
13. A semiconductor memory device comprising: a plurality of memory
banks each including a plurality of memory cell arrays, a plurality
of control circuits provided correspondingly to the memory cell
arrays, and a power source line supplied with a power voltage; a
plurality of address terminals receiving address signals
respectively, the address signals including one or more bank
address signals and a plurality of cell address signals; and a bank
control circuit decoding the bank address signals and outputting
decoded bank address signals to select at least one of the memory
banks, wherein each of the memory banks further includes a decoding
circuit decoding the cell address signals and outputting decoded
cell address signals to select one of the control circuits, each of
the control circuits includes an internal source line and a switch,
and the switch of one of the control circuits, which is selected by
the decoded cell address signals and contained in one of the memory
banks selected by the decoded bank address signals, is turned ON to
electrically connect the power source line and the internal source
line.
14. A semiconductor memory device comprising: a plurality of memory
banks each including a plurality of memory cell arrays, a plurality
of control circuits provided correspondingly to the memory cell
arrays, and a power source line supplied with a power voltage; a
plurality of address terminals receiving address signals
respectively, the address signals including one or more bank
address signals and a plurality of cell address signals; a bank
control circuit decoding the bank address signals and outputting
decoded bank address signals to select at least one of the memory
banks; and a decoding circuit decoding the cell address signals and
outputting decoded cell address signals to at least one of the
memory banks to select one of the control circuits in associated
one or ones of the memory banks, wherein each of the control
circuits includes an internal source line and a switch, and the
switch of one of the control circuits, which is selected by the
decoded cell address signals and contained in one of the memory
banks selected by the decoded bank address signals, being turned ON
to electrically connect the power source line and the internal
source line.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor memory
device, and particularly relates to a semiconductor memory device
in which power consumption is reduced.
[0003] 2. Description of Related Art
[0004] In recent years, the operation voltage of a semiconductor
device is gradually lowered in order to reduce its power
consumption. At present, a considerably low operation voltage on
the order of 1 volt is often used. However, as the operation
voltage is lowered, because it is required to lower the threshold
voltage in proportion to the decrease of the operation voltage, it
causes a problem that the sub-threshold current of the transistor
is increased in a non-conductive state.
[0005] To deal with such problems, there has been proposed a method
for a semiconductor device disclosed in Japanese Patent Application
Laid-open No. H11-31385, which has a structure in which a power
source line of a circuit area where logic is fixed at a standby
time is divided into a main power source line and a sub power
source line. That is, in an active state, the main power source
line and the sub power source line are short-circuited so that the
power is supplied to both of the lines, thus correctly supplying
the operation voltage to the circuit area. On the other hand, in a
standby state, the main power source line and the sub power source
line are disconnected so that no power is supplied to the sub power
source line, thus terminating a power supply to a transistor that
does not contribute to maintaining fixed logic that is determined
beforehand.
[0006] As a result, even when a transistor having a low threshold
is used, the power consumption is reduced because the sub-threshold
current is reduced in the standby state. In addition, because a
switching speed of the transistor having a low threshold is high, a
high speed operation of a semiconductor device can be achieved in
the active state. That is, it is possible to achieve both the high
speed operation and the low power consumption in the semiconductor
device.
[0007] In a case of applying a low power technology using such a
sub power source line as described above to a semiconductor memory
device such as a DRAM (Dynamic Random Access Memory), the main
power source line and the sub power source line can be disconnected
in a period during which the circuit area is in the standby state
in response to an external command supplied from outside.
[0008] However, if the main power source line and the sub source
line are merely disconnected during the period during which the
circuit area is in the standby state in response to the external
command, it only controls whether to enter the entire chip in the
standby mode or to enter the entire chip in the active state. That
is, it is not possible to control to enter only a part of an
internal circuit in the standby state and to disconnect the main
power source line and the sub power source line only in the
corresponding circuit portion. Therefore, the power consumption
cannot be reduced to a satisfactory extent, and a semiconductor
memory device that can further reduce the power consumption has
been desired.
SUMMARY
[0009] The present invention seeks to solve one or more of the
above problems, or to improve upon those problems at least in
part.
[0010] In one embodiment, there is provided a semiconductor memory
device comprising: a plurality of memory banks each including a
plurality of circuit areas selected based on an address signal, any
one of the memory banks being selected by a corresponding bank
selective signal; and a selective activation circuit that activates
anyone of the circuit areas and deactivates at least one of
remaining circuit areas based on the address signal included in a
memory bank that is selected based on the bank selective
signal.
[0011] In another embodiment, there is provided a semiconductor
memory device comprising: a memory bank that includes a plurality
of memory cells each connected to an associated one of word lines
and an associated one of bit lines; a row decoder that includes a
plurality of word drivers and performs selection of the word lines
based on a row address; a column decoder that performs selection of
the bit lines based on a column address; and a selective activation
circuit that activates any one of the word drivers and deactivates
remaining word drivers based on the row address, wherein each of
the word drivers includes a main power source line, a sub power
source line, a switch circuit connected between the main power
source line and the sub power source line, and a logic circuit that
is connected to the main power source line and the sub power source
line, and the selective activation circuit turns on the switch
circuit that is included in one of the word drivers to be
activated, and turns off the switch circuit included in the
remaining word drivers to be deactivated.
[0012] The "activation" of a circuit area in the present invention
means that an output signal of the circuit area can be changed in
response to an address signal. That is, if the circuit area is
activated, an output signal is activated when a predetermined
address signal is provided and the output signal is deactivated
when an address signal that is different from the predetermined
address signal is provided. On the other hand, the "deactivation"
means that the output signal of the circuit area is fixed
regardless of the address signal. That is, if the circuit area is
deactivated, the output signal is not activated even when the
predetermined address signal is provided. Of course, the output
signal is not activated either when an address signal that is
different from the predetermined address signal is provided.
[0013] As described above, in the semiconductor memory device
according to the present invention, a circuit area where an
operation is required in response to an address signal is activated
and a circuit area where the operation is not required is
deactivated. Therefore, the power consumption can be reduced in the
active state by a dynamic power control in response to an address
signal, not by entire power control by an external command.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The above features and advantages of the present invention
will be more apparent from the following description of certain
preferred embodiments taken in conjunction with the accompanying
drawings, in which:
[0015] FIG. 1 is an overall block diagram of a semiconductor memory
device 10 according to a first embodiment of the present
invention;
[0016] FIG. 2 is a block diagram of a bank configuration of the
memory cell array 20;
[0017] FIG. 3 is an enlarged diagram of pain parts of the memory
bank 21;
[0018] FIG. 4 shows the row decoder array 31 and its peripheral
circuits in detail;
[0019] FIG. 5 is a timing chart for explaining an operation of the
selective activation circuit 200;
[0020] FIG. 6 is a circuit diagram of the main word driver 80;
[0021] FIG. 7 is a waveform chart for explaining an operation of
the main word driver 80;
[0022] FIG. 8 is a circuit diagram of the sense amplifier
controller 91;
[0023] FIG. 9 is a waveform chart for explaining an operation of
the sense amplifier controller 91;
[0024] FIG. 10 is a block diagram for explaining a case that the
main power source lines VPP, VDD, VSS, and VKK are shared by a
plurality of main word drivers and sense amplifier controllers;
[0025] FIG. 11 is an enlarged block diagram of a memory bank 21
according to the second embodiment showing its main parts;
[0026] FIG. 12 shows a row decoder array 31 according to the second
embodiment and its peripheral circuits in detail;
[0027] FIG. 13 shows an operation waveform of the selective
activation circuit 300; and
[0028] FIG. 14 is a block diagram of a semiconductor memory device
according to a third embodiment of the present invention.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0029] Preferred embodiments of the present invention will be
explained below in detail with reference to the accompanying
drawings.
[0030] FIG. 1 is an overall block diagram of a semiconductor memory
device 10 according to a first embodiment of the present
invention.
[0031] As shown in FIG. 1, the semiconductor memory device 10
includes a memory cell array 20 that includes a plurality of memory
cells, a row decoder 30 that performs a row access to the memory
cell array 20, and a column decoder 40 that performs a column
access to the memory cell array 20. The memory cell array 20
includes a sub-word line SWL, a bit line BL, and a memory cell MC
that is connected to the sub-word line SWL and the bit line BL. The
sub-word line SWL is connected to a sub-word driver SWD that is
controlled by a main-word signal on a main-word line MWL. The bit
line BL is connected to a sense amplifier SAMP that is selected by
a column selection signal on a column selection line YS. Selection
of the main-word line MWL and the sub-word line SWL is performed by
the row decoder 30 based on a row address signal XA. Selection of
the column selection line YS and the bit line BL is performed by
the column decoder 40 based on a column address signal YA. The
memory cell MC that is selected by the selection of the sub-word
line. SWL and the selection of the bit line BL is connected to a
data amplifier 50, by which an output of read data and an input of
write data can be performed via a data input/output terminal
DQ.
[0032] Both the row address signal XA that is supplied to the row
decoder 30 and the column address signal YA that is supplied to the
column decoder 40 are supplied from outside via an address terminal
ADD. The row address signal XA and the column address signal YA are
supplied to the row decoder 30 and the column decoder 40,
respectively, via an address buffer 60. Among address signals
supplied to the address terminal ADD, an address signal supplied in
synchronization with an active command is the row address signal
XA, and an address signal supplied in synchronization with a read
command or a write command is the column address signal YA.
Therefore, the row address signal XA that is supplied in
synchronization with the active command is supplied to the row
decoder 30 via the address buffer 60, and the column address signal
YA that is supplied in synchronization with the read command or the
write command is supplied to the column decoder 40 via the address
buffer 60.
[0033] The various commands described above are supplied from the
outside via a command terminal CMD, and are supplied to a command
decoder 70. The command decoder 70 is a circuit that interprets the
command supplied via the command terminal CMD, which generates
various types of internal commands ICMD based on a result of
interpretation. The generated internal commands ICMD are supplied
to each corresponding circuit block.
[0034] As shown in FIG. 1, one of the circuits to which the
internal commands ICMD are supplied is a source transistor control
circuit (bank control circuit) 100. The source transistor control
circuit 100 is a circuit that generates a source transistor control
signal STC based on an address signal and a command. The source
transistor control signal STC is a signal for activating, from
among the memory cell array 20, a circuit area that is related to a
memory bank, which is an access target, and deactivating a circuit
area that is related to a memory bank, which is not the access
target. That is, the source transistor control signal STC is a bank
selective signal.
[0035] FIG. 2 is a block diagram of a bank configuration of the
memory cell array 20.
[0036] As shown in FIG. 2, in the first embodiment, the memory cell
array 20 is divided into four memory banks 21 to 24. Selection of a
memory bank is performed by a bank address that is a part of the
row address signal XA. That is, the source transistor control
circuit 100 receives a command and a bank address, and based on the
received command and bank address, activates any one of source
transistor control signal STC1 to STC4 corresponding to the memory
banks 21 to 24, respectively.
[0037] FIG. 3 is an enlarged diagram of pain parts of the memory
bank 21.
[0038] As shown in FIG. 3, the memory bank 21 includes memory cell
areas 21a and 21b that are evenly divided in an X direction.
Between the memory cell areas 21a and 21b, a row decoder array 31
is arranged extending in a Y direction. The row decoder array 31
includes eight main word drivers 80 to 87 (eight circuit areas).
The main word drivers 80 to 87 are circuits that activates
corresponding main word lines (not shown), respectively.
Furthermore, the memory bank 21 is configured with memory areas #0
to #7 that are evenly divided in the Y direction. The activation of
the main word line enables corresponding one of the memory areas #0
to #7 to be accessed.
[0039] In the first embodiment, the row address signal XA that is
supplied to the memory bank 21 is divided into a 10-bit lower
address consisting of X0 to X9 and a 3-bit upper address consisting
of X10 to X12. The upper addresses X10 to X12 are supplied to a row
pre-decoder 32, by which any one bit of an 8-bit pre-decode signals
PX0 to PX7 is activated. In the example shown in FIG. 3, the row
decoder array 31 and the row pre-decoder 32 are components included
in the memory bank 21. However, the present invention is not
limited thereto, and the row decoder array 31 and the row
pre-decoder 32 can be circuit blocks that constitute the row
decoder 30 shown in FIG. 1. In this case, the row pre-decoder 32
can be provided such that it is shared by the memory banks 21 to
24.
[0040] The pre-decode signals PX0 to PX7 are signals for selecting
the main word drivers 80 to 87, respectively. As described above,
because only one bit is activated from among the 8-bit pre-decode
signals PX0 to PX7, only one main word driver is activated from
among the main word drivers 80 to 87. This means that only one
memory area is accessed from among the memory areas #0 to #7, and
the rest of seven memory areas are not accessed.
[0041] Meanwhile, the lower addresses X0 to X9 are pre-decoded by a
row pre-decoder (not shown), and then a part of the lower address
is commonly supplied to the main word drivers 80 to 87. The other
part of the lower address is supplied to a sub-word driver (not
shown) that is arranged in the memory bank 21. That is, any one of
the memory areas #0 to #7 is selected by the upper addresses X10 to
X12, and any one of sub-word lines included in the selected one of
the memory areas #0 to #7 is selected by the lower addresses X0 to
X9.
[0042] Although the row decoder array 31 is arranged at the center
of the memory bank 21 that is divided into two parts in the example
shown in FIG. 3, the present invention is not limited thereto.
Thus, the row decoder array 31 can be arranged along a side of the
memory bank without dividing the memory bank 21. Alternatively, the
row decoder array 31 can be divided into two or more columns and
arranged in the memory bank 21 that is divided into three or more
areas. In addition, the upper address to be pre-decoded is not
necessarily to be 3 bits.
[0043] The other memory banks 22 to 24 have the same configuration
as the memory bank 21 described above.
[0044] FIG. 4 shows the row decoder array 31 and its peripheral
circuits in detail.
[0045] As shown in FIG. 4, in the row decoder array 31, a plurality
of the main word drivers 80, 81, . . . are arranged in the Y
direction, and sense amplifier controllers 90, 91, 92, . . . are
respectively arranged on both sides of the main word driver in the
Y direction. As described above, the main word drivers 80, 81, . .
. are circuits for activating their corresponding main word lines
MWLB, and each of the main word lines MWLB is supplied to a
sub-word driver SWD arranged at its corresponding one of the memory
areas #0 to #7. The sense amplifier controllers 90, 91, 92, . . .
are circuits for respectively activating their corresponding sense
amplifier control signals ASAPT, and each of the sense amplifier
control signals ASAPT is supplied to a sense amplifier SA arranged
at its corresponding one of the memory areas #0 to #7.
[0046] The main word drivers 80, 81, . . . are respectively
activated based on their corresponding source gate control signals
SGC0, SGC1, . . . . On the other hand, the sense amplifier
controllers 90, 91, 92, . . . are activated simultaneously when the
adjacent main word driver is activated. Therefore, the source gate
control signal SGC0 is supplied as it is to the sense amplifier
controller 90 that is located at the edge, and an OR signal SGC01
of the source gate control signals SCG0 and SGC1 is supplied to the
sense amplifier controller 91 that is sandwiched by the main word
drivers 80 and 81.
[0047] Such source gate control signals SCG0, SGC1, . . . , and
SGC01, SGC12, . . . are generated by a selective activation circuit
200 shown in FIG. 4. The selective activation circuit 200 is a
logic circuit that generates the source gate control signals SCG0,
SGC1, . . . based on the source transistor control signal STC1 and
the pre-decode signals PX0, PX1, . . . .
[0048] As shown in FIG. 4, the selective activation circuit 200
according to the first embodiment includes AND gates 210, 211, . .
. that respectively take logical products of the source transistor
control signal STC1 and the pre-decode signals PX0, PX1, . . . ,
and their outputs are the source gate control signals SCG0, SGC1, .
. . , respectively. As described above, the source gate control
signals SCG0, SGC1, . . . are respectively supplied to their
corresponding main word drivers 80, 81, . . . , and at the same
time, the two adjacent source gate signals SCG0, SGC1, . . . are
subject to logical sums by OR gates 221, 222, . . . , respectively
so that their outputs SGC01, SGC12, . . . are supplied to the sense
amplifier controllers 91, 92, . . . (other than the sense amplifier
controller located at the edge).
[0049] With this configuration, any one of the word drivers is
activated based on the pre-decode signals PX0 to PX 7 from among
the main word drivers 80, 81, . . . that are included in a memory
bank selected based on the source transistor control signals STC1
to STC3 that are the bank selective signals, and at the same time,
the rest of the word drivers are all deactivated. In addition, as
for the sense amplifier controllers 90, 91, 92, . . . , only the
two sense amplifier controllers adjacent to an activated word
driver are activated, and at the same time, the rest of the sense
amplifier controllers are all deactivated. Therefore, only one main
word driver and two sense amplifier controllers that are related to
a memory area, which is the access target, are activated, while the
others are deactivated.
[0050] FIG. 5 is a timing chart for explaining an operation of the
selective activation circuit 200.
[0051] As shown in FIG. 5, when an access to the memory bank 21 is
requested based on the address signal and the command, the source
transistor control signal STC1 is activated regardless that which
memory area included in the memory bank is selected. On the other
hand, any one bit of the pre-decode signals PX0 to PX7 is activated
based on the upper addresses X10 to X12 of the row address XA. In
the example shown in FIG. 5, the pre-decode signal PX0 is activated
for a period T0, and the pre-decode signal PX1 is activated for a
period T1. The source transistor control signal STC1 is activated
for both the periods T0 and T1.
[0052] Because the AND gates 210, 211, . . . that respectively take
the logical products of the source transistor control signal STC1
and the pre-decode signals PX0, PX1, . . . are provided in the
selective activation circuit 200, the source gate control signal
SCG0 is activated for the period T0, and the source gate control
signal SGC1 is activated for the period T1. Therefore, for the
period T0, only the main word driver 80 is activated, and the other
main word drivers 81 to 87 are maintained in a deactivation state.
Similarly, for the period T1, only the main word driver 81 is
activated, and the other main word drivers 80, 82 to 87 are
maintained in a deactivation state.
[0053] Furthermore, because the OR gates 221, 222, . . . that
respectively take the logical sums of two source gate control
signals SCG0, SGC1, . . . are provided in the selective activation
circuit 200, the source gate control signal SGC01 is activated for
both the periods T0 and T1. As described above, the source gate
control signal SCG0 is supplied as it is to the sense amplifier
controller 90. Therefore, for the period T0, only the sense
amplifier controllers 90 and 91 are activated, and the other sense
amplifier controllers 92 to 98 are maintained in a deactivation
state. Similarly, for the period T1, only the sense amplifier
controllers 91 and 92 are activated, and the other sense amplifier
controllers 90 and 93 to 98 are maintained in a deactivation
state.
[0054] FIG. 6 is a circuit diagram of the main word driver 80.
[0055] As shown in FIG. 6, the main word driver 80 is a logic
circuit that receives internal signals RMS1 to RMS3, and drives the
main word line MWLB. The internal signals RMS1 to RMS3 are signals
(pre-decode signals) generated based on the row address XA.
[0056] Among P-channel MOS transistors P11 to P15 that constitute
the logic of the main word driver 80, the sources of the
transistors P11, P12, and P15 are connected to a main power source
line VPP, and the source of the transistor P13 is connected to a
sub power source line VPPZ. A PMOS source transistor P1 as a switch
is connected between the main power source line VPP and the sub
power source line VPPZ. An inversion signal SCG0B of the source
gate control signal SCG0 is supplied to the gate of the transistor
P1. Therefore, if the level of the source gate control signal SCG0
is High (an activation state), the main power source line VPP and
the sub power source line VPPZ are short-circuited, so that the
same potential is supplied to the sub power source line VPPZ as
that supplied to the main power source line VPP. On the other hand,
if the level of the source gate control signal SCG0 is Low (a
deactivation state), the main power source line VPP and the sub
power source line VPPZ are disconnected, so that no power is
supplied to the sub power source line VPPZ.
[0057] Furthermore, from among N-channel MOS transistors N11 to N14
that constitute the logic of the main word driver 80, the sources
of the transistors N12 and N13 are connected to a main power source
line VSS or VKK, and the source of the transistor N14 is connected
to a sub power source line VKKZ. An NMOS source transistor N1 as a
switch is connected between the main power source line VKK and the
sub power source line VKKZ. The source gate control signal SCG0 is
supplied to the gate of the transistor N1. Therefore, if a level of
the source gate control signal SCG0 is High (an activation state),
the main power source line VKK and the sub power source line VKKZ
are short-circuited, so that the same potential is supplied to the
sub power source line VKKZ as that supplied to the main power
source line VKK. On the other hand, if the level of the source gate
control signal SCG0 is Low (a deactivation state), the main power
source line VKK and the sub power source line VKKZ are
disconnected, so that no power is supplied to the sub power source
line VKKZ.
[0058] The transistors connected to the main power source lines
VPP, VSS, and VKK are transistors that are required to fix the
logic of the main word driver in a deactivation state (transistors
to be turned ON), and the transistors connected to the sub power
source lines VPPZ and VKKZ are transistors that are not required to
fix the logic of the main word driver in the deactivation state
(transistors to be turned OFF). Therefore, if the source gate
control signal SCG0 is deactivated, no power is supplied to the
sources of the transistors that are not required to fix the logic,
so that there is virtually no power consumption due to the
sub-threshold current in a deactivation state. As a result, it is
possible to reduce the power consumption in a deactivation state
while utilizing a high speed transistor having a low threshold
voltage.
[0059] The other main word drivers 81 to 87 have the same circuit
configuration as the main word driver 80. In addition, the main
power source lines VPP, VSS, and VKK can be provided such that they
are shared by the main word drivers 80 to 87.
[0060] FIG. 7 is a waveform chart for explaining an operation of
the main word driver 80.
[0061] As shown in FIG. 7, in a period T11 for which the source
gate control signal SCG0 is activated to a High level, if the
levels of the internal signals RMS1 to RMS3 reach a predetermined
logical level, the main word line MWLB is driven to a Low level, by
which the corresponding sub-word driver SWD is in a selective
state. On the other hand, even when the source gate control signal
SCG0 is activated to a High level, if the levels of the internal
signals RMS1 to RMS3 are logical levels that are different from the
predetermined logical level, the main word line MWLB is driven to a
High level, by which the corresponding sub-word driver SWD is in a
non-selective state.
[0062] In periods T10 and T12 for which the source gate control
signal SCG0 is deactivated to a Low level, as described above, the
PMOS source transistor P1 and the NMOS source transistor N1 are
turned OFF, so that the power supply to the sub power source lines
VPPZ and VKKZ is terminated. Accordingly, the power consumption is
greatly reduced while maintaining the main word line MWLB to a High
level.
[0063] The case that the source gate control signal SCG0 is
deactivated includes a case that the memory bank 21 is not an
access target. In this case, because the source transistor control
signal STC1 itself is in a deactivation state, the source gate
control signal SCG0 is deactivated regardless of the values of the
pre-decode signals PX0 to PX7. Another case is that the memory bank
21 is an access target, but the pre-decode signal PX0 is
deactivated and any one of the pre-decode signals PX1 to PX7 is in
an activation state. In this case, the corresponding memory area #0
is not the access target, and the power consumption of the main
word driver 80 is saved, which does not need to be activated. Still
another case is that the entire unit of the semiconductor memory
device 10 is in a standby state by a command. In this case, all of
the source gate control signals are deactivated.
[0064] FIG. 8 is a circuit diagram of the sense amplifier
controller 91.
[0065] As shown in FIG. 8, the sense amplifier controller 91 is a
logic circuit that receives internal signals RMSB and RSAPB, and
controls a logical level of the sense amplifier control signal
ASAPT. The internal signal RMSB is a pre-decode signal, and the
internal signal RSAPB is a sense start signal.
[0066] From among P-channel MOS transistors P21 to P27 that
constitute the logic of the sense amplifier controller 91, the
sources of the transistors P23, P24, and P26 are connected to a
main power source line VPP or VDD, and the sources of the
transistors P21, P25, and P27 are connected to a sub power source
line VPPZ or VDDZ. A PMOS source transistor P2 as a switch is
connected between the main power source line VPP and the sub power
source line VPPZ. An inversion signal SGC01B of the source gate
control signal SGC01 is supplied to the gate of the transistor P2.
Similarly, a PMOS source transistor P3 as a switch is connected
between the main power source line VDD and the sub power source
line VDDZ. An inversion signal SGC01B of the source gate control
signal SGC01 is supplied to the gate of the transistor P3.
Therefore, if a level of the source gate control signal SGC01 is
High (an activation state), the main power source line VPP and the
sub power source line VPPZ are short-circuited, so that the same
potential is supplied to the sub power source line VPPZ as that
supplied to the main power source line VPP. At the same time, the
main power source line VDD and the sub power source line VDDZ are
short-circuited, so that the same potential is supplied to the sub
power source line VDDZ as that supplied to the main power source
line VDD. On the other hand, if the level of the source gate
control signal SGC01 is Low (a deactivation state), the main power
source line VPP and the sub power source line VPPZ are
disconnected, and at the same time, the main power source line VDD
and the sub power source line VDDZ are disconnected, so that no
power is supplied to the sub power source lines VPPZ and VDDZ.
[0067] Furthermore, from among N-channel MOS transistors N21 to N29
that constitute the logic of the sense amplifier controller 91, the
sources of the transistors N21, N22, N27, and N29 are connected to
a main power source line VSS, and the sources of the transistors
N23, N25, and N28 are connected to a sub power source line VSSZ. An
NMOS source transistor N2 as a switch is connected between the main
power source line VSS and the sub power source line VSSZ. The
source gate control signal SGC01 is supplied to the gate of the
transistor N2. Therefore, if a level of the source gate control
signal SGC01 is High (an activation state), the main power source
line VSS and the sub power source line VSSZ are short-circuited, so
that the same potential is supplied to the sub power source line
VSSZ as that supplied to the main power source line VSS. On the
other hand, if the level of the source gate control signal SGC01 is
Low (a deactivation state), the main power source line VSS and the
sub power source line VSSZ are disconnected, so that no power is
supplied to the sub power source line VSSZ.
[0068] The transistors connected to the main power source lines
VPP, VDD, and VSS are transistors that are required to fix the
logic of the main word driver in the deactivation state
(transistors to be turned ON), and the transistors connected to the
sub power source lines VPPZ, VDDZ, and VSSZ are transistors that
are not required to fix the logic of the main word driver in the
deactivation state (transistors to be turned OFF). Therefore, if
the source gate control signal SGC01 is deactivated, no power is
supplied to the sources of the transistors that are not required to
fix the logic, so that there is virtually no power consumption due
to the sub-threshold current in a deactivation state. As a result,
it is possible to reduce the power consumption in the deactivation
state while utilizing a high speed transistor having a low
threshold voltage.
[0069] The other sense amplifier controllers 90, 92 to 98 have the
same circuit configuration as the sense amplifier controller 91. In
addition, the main power source lines VPP, VDD, and VSS can be
provided such that they are shared by the sense amplifier
controllers 90 to 98.
[0070] FIG. 9 is a waveform chart for explaining an operation of
the sense amplifier controller 91.
[0071] As shown in FIG. 9, in a period T21 for which the source
gate control signal SGC01 is activated to a High level, if the
levels of the internal signals RMSB and RSAPB reach a predetermined
logical level, the level of the sense amplifier control signal
ASAPT becomes a High level, by which a corresponding sense
amplifier SA is in a selective state. On the other hand, even when
the source gate control signal SGC01 is activated to a High level,
if the levels of the internal signals RMSB and RSAPB are logical
levels that are different from the predetermined logical levels,
the sense amplifier control signal ASAPT becomes a Low level, by
which the corresponding sense amplifier SA is in a non-selective
state.
[0072] In periods T20 and T22 for which the source gate control
signal SCG01 is deactivated to a Low level, as described above, the
PMOS source transistors P2 and P3 and the NMOS source transistor N2
are turned OFF, so that the power supply to the sub power source
lines VPPZ, VDDZ, and VSSZ is terminated. Therefore, the power
consumption is greatly reduced while maintaining the sense
amplifier control signal ASAPT to a Low level.
[0073] As described above, according to the first embodiment, the
main word drivers 80 to 87 and the sense amplifier controllers 90
to 98 are selectively deactivated not only in a case that the
entire unit of the semiconductor memory device 10 is in a standby
state, but also in a case that the memory bank in concern is not an
access target or a case that the memory bank in concern is the
access target but a corresponding memory area is not the access
target. That is, even during an access, because circuit areas that
are not the access target can be selectively deactivated, the power
consumption can be reduced as compared to the conventional
case.
[0074] As described above, the main word drivers 80 to 87 can share
the main power source lines VPP, VSS, and VKK. Similarly, the sense
amplifier controllers 90 to 98 can share the main power source
lines VPP, VDD, and VSS. FIG. 10 is a block diagram for explaining
this case, which is a case that the main power source lines VPP,
VDD, VSS, and VKK are shared by a plurality of main word drivers
and sense amplifier controllers. In FIG. 10, the main power source
lines VPP and VSS are provided commonly to the main word drivers 80
to 87 and the sense amplifier controllers 90 to 98. The main power
source line VDD is provided commonly to the sense amplifier
controllers 90 to 98. Moreover, the main power source line VKK is
provided commonly to the main word drivers 80 to 87. On the other
hand, the sub power source lines VPPZ, VDDZ, VSSZ, and VKKZ are
provided separately for each of the main word drivers 80 to 87 and
the sense amplifier controllers 90 to 98, which are not commonly
connected.
[0075] A second embodiment of the present invention is explained
next.
[0076] FIG. 11 is an enlarged block diagram of a memory bank 21
according to the second embodiment showing its main parts, and FIG.
11 corresponds to FIG. 3 for explaining the first embodiment.
[0077] As shown in FIG. 11, the second embodiment is different from
the first embodiment in that the source transistor control circuit
100 includes an SR latch circuit 110 and an output of the SR latch
circuit 110 is the source transistor control signal STC1. Other
features of the second embodiment are identical to those of the
first embedment, and thus explanations thereof will be omitted.
[0078] An internal signal RASB is supplied to a set-side input
terminal S of the SR latch circuit 110 via a pulse generating
circuit 120. The internal signal RASB is a signal that becomes a
Low level in response to issuance of an active command. Therefore,
when the active command is issued, the SR latch circuit 110 is set,
by which the source transistor control signal STC1 is activated to
a High level. That is, when the active command is issued, the
source transistor control signal STC1 is activated regardless of
the value of the row address XA.
[0079] An internal signal RASOKT is supplied to a reset input
terminal R of the SR latch circuit 110 via an inverter 130. The
internal signal RASOKT is a signal that becomes a High level when a
sense operation of the memory bank 21 is complete. Therefore, when
the sense operation is complete, the source transistor control
signal STC1 is returned to a deactivation state.
[0080] FIG. 12 shows a row decoder array 31 according to the second
embodiment and its peripheral circuits in detail, and FIG. 12
corresponds to FIG. 4 for explaining the first embodiment.
[0081] As shown in FIG. 12, a selective activation circuit 300
according to the second embodiment includes OR gates 330, 331, . .
. that take logical sums of the source transistor control signal
STC1 and the pre-decode signals PX0, PX1, . . . , respectively, and
OR gates 340, 341, . . . that take logical sums of the source
transistor control signal STC1 and a pair of the pre-decode signals
PX0, PX1, . . . in order, respectively. Source gate control signals
SCG0, SGC1 , . . . , which are outputs of the OR gates 330, 331, .
. . , are supplied to their corresponding main word drivers 80 to
87, respectively, and at the same time, supplied to sense amplifier
controllers 90 and 98 (not shown) located at both edges. Source
gate control signals SGC01, SGC12, which are outputs of the OR
gates 340, 341, . . . , are supplied to their corresponding sense
amplifier controllers 91, 92, . . . (except for the ones located at
both edges). The operation waveform of the selective activation
circuit 300 is shown in FIG. 13.
[0082] With the above configuration, when the source transistor
control signal STC1, which is a bank selective signal, is
activated, all of the main word drivers 80 to 87 and the sense
amplifier controllers 90 to 98 are once activated regardless of the
values of the pre-decode signals PX0 to PX7. As described above,
because the source transistor control signal STC1 is activated in
response to the issuance of the active command, all of the main
word drivers 80 to 87 and the sense amplifier controllers 90 to 98
become activated once, if the active command is issued.
[0083] Thereafter, when the sense operation of the memory bank 21
is complete, because the source transistor control signal STC1 is
returned to a deactivation state, only one main word driver and two
sense amplifier controllers are maintained in an activation state,
and the other main word drivers and the sense amplifier controllers
are deactivated.
[0084] In this manner, in the second embodiment, when the active
command is issued, all of the main word drivers 80 to 87 and the
sense amplifier controllers 90 to 98 become activated once, which
makes it possible to suppress a decrease of an access speed due to
the existence of the selective activation circuit 300.
[0085] As shown in FIG. 13, a period T30 during which a level of
the internal signal RASB is Low, i.e., the period during which the
semiconductor memory device 10 is in an active state, is 70
microseconds. On the other hand, a period T31 from the time when
the internal signal RASB make transition to a Low level to the time
when the internal signal RASOKT is activated is about 20 to 30
nanoseconds. That is, the period T31 during which all of the main
word drivers 80 to 87 and the sense amplifier controllers 90 to 98
become activated is considerably short as compared to the period
T30 during which the semiconductor memory device 10 is in an active
state. Therefore, although all of the main word drivers 80 to 87
and the sense amplifier controllers 90 to 98 are activated once in
the second embodiment, an increase of the power consumption is
considerably small as compared to the first embodiment. That is, a
high speed access, which is higher than that in the first
embodiment, can be realized, while suppressing an increase of the
power consumption with respect to the first embodiment.
[0086] FIG. 14 is a block diagram of a semiconductor memory device
according to a third embodiment of the present invention.
[0087] In the third embodiment, as shown in FIG. 14, a source
transistor control signal STC1 is supplied to a column select
circuit group 41 that constitutes the column decoder 40. The column
select circuit group 41 includes a plurality of column select
circuits 400, 401, . . . , which are selected based on their
corresponding pre-decode signals PY0, PY1, . . . . The pre-decode
signals PY0, PY1, . . . are signals generated by pre-decoding a
part of the column address YA by a column pre-decoder 42. The
column select circuit group 41 and the column pre-decoder 42 form
the column decoder 40 shown in FIG. 1.
[0088] In the above configuration, the column select circuits 400,
401, . . . are selectively activated based on the source transistor
control signal STC1 and the pre-decode signals PY0, PY1, . . . , as
it is in the first and second embodiments. Therefore, only a column
select circuit that is related to a memory area of an access target
is activated, and the other column select circuits are maintained
in a deactivation state. In the similar manner to the first and
second embodiments, the activation state indicates a state where a
main power source line and a sub power source line are
short-circuited in a column select circuit, and the deactivation
state indicates a state where the main power source line and the
sub power source line are disconnected in the column select
circuit.
[0089] In this manner, selectively deactivating circuit areas that
are not the access target also in the column decoder 40, the power
consumption can be reduced as compared to the conventional case. Of
course, by selectively deactivating circuit areas that are not the
access target in both the row decoder 30 and the column decoder 40,
the power consumption can be even more reduced.
[0090] When pursuing a high speed access by activating once all of
the column select circuits 400, 401, . . . , in the same manner as
the second embodiment, an internal signal CASB that becomes a Low
level in response to issuance of a read command or a write command
can be used instead of the internal signal RASB shown in FIG.
11.
[0091] It is apparent that the present invention is not limited to
the above embodiments, but may be modified and changed without
departing from the scope and spirit of the invention.
[0092] For example, although any one of the main word drivers is
activated by the selective activation circuit 200 while
deactivating all of the other main word drivers, it is not
essential to deactivate all of the other main word drivers, but it
suffices as at least one of the other main word drivers is
deactivated.
* * * * *