U.S. patent application number 12/707989 was filed with the patent office on 2010-06-10 for digital communication system and method.
This patent application is currently assigned to Gennum Corporation. Invention is credited to Aapoolcoyuz Biman, John Hudson, Stephen P. Webster, Eliyahu D. Zamir.
Application Number | 20100142611 12/707989 |
Document ID | / |
Family ID | 28045402 |
Filed Date | 2010-06-10 |
United States Patent
Application |
20100142611 |
Kind Code |
A1 |
Biman; Aapoolcoyuz ; et
al. |
June 10, 2010 |
DIGITAL COMMUNICATION SYSTEM AND METHOD
Abstract
A digital communication system for transmitting and receiving
video data signals and control data signals over a transmission
line comprises an open-loop equalizer circuit and a control data
extension circuit. The open-loop equalizer circuit is operable to
receive video signals transmitted over the transmission line and
output equalized video data signals. The control data extension
circuit is operable to inject a boost current at the receive end of
the transmission line during a positive transition in the control
data signal, and clamp the receive end of the transmission line
during a negative transition of the control data signal.
Inventors: |
Biman; Aapoolcoyuz;
(Hamilton, CA) ; Hudson; John; (Burlington,
CA) ; Zamir; Eliyahu D.; (Toronto, CA) ;
Webster; Stephen P.; (Oakville, CA) |
Correspondence
Address: |
PATENT GROUP 2N;JONES DAY
NORTH POINT, 901 LAKESIDE AVENUE
CLEVELAND
OH
44114
US
|
Assignee: |
Gennum Corporation
Burlington
CA
|
Family ID: |
28045402 |
Appl. No.: |
12/707989 |
Filed: |
February 18, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11820311 |
Jun 19, 2007 |
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12707989 |
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10388899 |
Mar 14, 2003 |
7230989 |
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11820311 |
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60364430 |
Mar 15, 2002 |
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60441010 |
Jan 17, 2003 |
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60364430 |
Mar 15, 2002 |
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60441010 |
Jan 17, 2003 |
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Current U.S.
Class: |
375/233 |
Current CPC
Class: |
H03F 2203/45702
20130101; G09G 2330/04 20130101; G09G 5/006 20130101; H04L 25/08
20130101; H03F 2203/45612 20130101; H04L 25/03878 20130101; H03F
2203/45496 20130101; H04L 25/10 20130101; H03F 3/191 20130101; H03F
3/45197 20130101; G09G 2370/047 20130101; H04L 25/0272 20130101;
H03F 2203/45458 20130101 |
Class at
Publication: |
375/233 |
International
Class: |
H03K 5/159 20060101
H03K005/159 |
Claims
1. A digital communication system for processing transition
minimized differential signal (TMDS) communication data signals and
Display Data Channel (DDC) communication signals over a
transmission line, the system comprising: an open-loop equalizer
circuit to receive TMDS communication signals transmitted over the
transmission line and output equalized TMDS communication data
signals, the open-loop equalizer circuit providing either
proportional or disproportional equalization to the TMDS
communication data signal, wherein proportional equalization
provides a frequency dependent gain that is at or about the inverse
of a frequency dependent attenuation caused by the transmission
line, and wherein disproportionate equalization provides a
frequency dependent gain that is greater than the inverse of a
frequency dependent attenuation caused by the transmission line.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This is a continuation of U.S. application Ser. No.
11/820,311, filed on Jun. 19, 2007, which was a divisional of U.S.
application Ser. No. 10/388,899, filed on Mar. 14, 2003, and which
claims the benefit of and priority to U.S. Provisional Application
Ser. No. 60/364,430, entitled "Equalization In Digital Video
Interfaces," and filed on Mar. 15, 2002, and U.S. Provisional
Application Ser. No. 60/441,010, entitled "Systems And Methods For
Data Communication And Transmission," and filed on Jan. 17, 2003.
The entire disclosures of Application Ser. Nos. 60/364,430 and
60/441,010 are incorporated herein by reference. This application
is also related to U.S. Re-Issue application Ser. No. 12/478,032,
filed Jun. 4, 2009.
BACKGROUND
[0002] 1. Technical Field
[0003] This application generally relates to digital communication
systems and methods, and particularly relates to Digital Visual
Interface (DVI) communications.
[0004] 2. Description of the Related Art
[0005] The Digital Visual Interface (DVI) Specification, Revision
1.0, dated Apr. 2, 1999, and published by Digital Display Working
Group, provides for a high speed digital connection for visual data
types that is display technology independent. A DVI interface is
typically focused on providing a connection between a computer and
the computer display device. A DVI system uses a transition
minimized differential signal (TMDS) for a base electrical
connection, in which 8 bits of data are encoded into a 10-bit,
transition minimized DC balanced character.
[0006] DVI accommodates several different serial signal rates, the
highest of which is a signal rate of 1650 Mb/s. This signal rate
corresponds to a data rate of 825 MHz. The DVI data may be
transmitted over a video bus in a computer device, such as in
laptop computer, or may be transmitted over a cable that is
external to a computer device, such as a video cable used to
connect a remote monitor to a computer. Typically, cables over
short distances and low frequencies can be considered ideal
channels having minimal loss and a bandwidth much greater than the
input signal. The ideal cable with infinite bandwidth produces no
dispersion of the input data.
[0007] Real cables, however, have a loss characteristic that is a
function of the data frequency and the cable length. Thus, the
longer the cable length, the greater the loss characteristic. In
practical applications, the attenuation of the high frequency
components of the DVI data signal at 1650 MHz typically limits DVI
cable lengths to about 5 meters.
[0008] Equalizers may be used to restore the integrity of the DVI
data so that the cable length between the source and the
destination does not reduce the system performance. Many equalizers
comprise a differential pair having an automatic gain control (AGC)
feedback block between the output of the differential pair and the
inputs of the differential pair. Additionally, many of these
differential pairs utilize inductors, which demand a relatively
large amount of semiconductor area and are susceptible to
noise.
[0009] The DVI specification also supports the VESA Display Data
Channel (DDC), which enables the computer display, the computer,
and a graphics adapter to communicate and automatically configure
the system to support different features available in the computer
display. The DDC link is typically a lower bandwidth signal, e.g.,
400 kHz, and thus may be transmitted over a longer cable length
than the DVI data signal. However, the DDC cable is typically not
terminated in an impedance match, and thus reflections in the DDC
cable may degrade the DDC signal as the DDC cable length increases.
Additionally, the bandwidth of the DDC signal is limited by the
amount of pull-up current injected into the DDC cable during a
transition of the data signal from a low voltage level to a high
voltage level.
SUMMARY
[0010] A digital communication system for transmitting and
receiving Digital Visual Interface (DVI) communication data signals
and Display Data Channel (DDC) communication signals over a
transmission line comprises an open-loop equalizer circuit and a
DDC extension circuit. The open-loop equalizer circuit is operable
to receive DVI communication signals transmitted over the
transmission line and output equalized DVI communication data
signals. The DDC extension circuit is operable to inject a boost
current at the receive end of the transmission line during a
positive transition in the DDC communication signal, and clamp the
receive end of the transmission line during a negative transition
of the DDC communication signal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a block diagram of a DVI communication system;
[0012] FIG. 2 is a block diagram of a digital communication system
comprising equalizers and a DDC extender circuit;
[0013] FIG. 3 is a block diagram of an equalizer configured to
equalize data signals received at a receive end of a transmission
line;
[0014] FIG. 4 is a block diagram of an equalizer configured to
pre-emphasize data signals to be transmitted on the transmission
line.
[0015] FIG. 5 is a block diagram of a pair of equalizers, the first
equalizer configured to pre-emphasize data signals to be
transmitted on the transmission line, and the second equalizer
configured to equalize data signals received at a receive end of
the transmission line;
[0016] FIG. 6A is a block diagram of a receive side of the system
of FIG. 3;
[0017] FIG. 6B is a block diagram of a transmit side of the system
of FIG. 4;
[0018] FIG. 7 is a block diagram of an open-loop equalizer stage
utilized in the systems of FIGS. 3-6B;
[0019] FIG. 8 is a timing diagram of one DC pulse in a DC balanced
data signal and a corresponding differential signal transmitted
over the transmission line and equalized by the open-loop equalizer
stage of FIG. 7;
[0020] FIG. 9 is a block diagram of an input follower stage
implemented at the input open-loop equalizer stage of FIG. 7;
[0021] FIG. 10 is a circuit diagram on an embodiment of the
open-loop equalizer of FIG. 7;
[0022] FIG. 11 is a block diagram of an electrostatic discharge
(ESD) compensation circuit utilizing the open-loop equalizer stage
of FIG. 7;
[0023] FIG. 12 is a timing diagram of a data signal passing through
the ESD compensation circuit of FIG. 12;
[0024] FIG. 13 is a block diagram of a DDC extender circuit
connected to the receive end of the transmission line;
[0025] FIGS. 14-17 are timing diagrams illustrating the receive end
response during a data signal transition;
[0026] FIG. 18 is a schematic representation of the transmission
line after activation of a voltage clamp circuit;
[0027] FIG. 19 is a timing diagram of the current in the
transmission line after activation of the voltage clamp
circuit;
[0028] FIG. 20 is a timing diagram of the DDC data signal received
at the receive end of the transmission line without a boost current
injected into the transmission line;
[0029] FIG. 21 is a block diagram of the DDC extender circuit of
FIG. 14;
[0030] FIG. 22 is a schematic diagram one embodiment of the DDC
extender circuit of FIG. 14; and
[0031] FIG. 23 is a timing diagram of the DDC data signal received
at the receive end of the transmission line with a boost current
injected into the transmission line.
DETAILED DESCRIPTION
[0032] FIG. 1 is a block diagram of a DVI communication system 1,
which includes a graphics controller 10, a DDC controller 12, a
transmitter 14, a receiver 16, and a display controller 18. A DVI
data line typically comprises three data channels, shown as Data
Channels 0, 1 and 2, and a clock.
[0033] The graphics controller 10 is operable to encode 8 bits of
video data into a 10-bit TMDS DC balanced character on each data
channel. The graphics controller 10 may be one of many
DVI-compliant graphics controllers. The transmitter 14 and receiver
16 are operable to transmit and receive the 10-bit TMDS DC balanced
characters over a transmission line. The display controller 18 is
operable to decode the 10-bit character back into the 8 bits of
video data for each data channel. The display controller 18 may be
one of many DVI-compliant display controllers.
[0034] The DDC controller 12 is operable to transmit DDC data and
receive DDC data over the transmission line. Unlike the DVI data,
the DDC data is not DC balanced. The DDC data link typically
comprises a clock channel and a digital data channel.
[0035] Usually, the physical path between the transmitter 14 and
the receiver 16 is less than five meters. For example, the
transmitter 14 and receiver 16 may be enclosed in a single
enclosure, such as when connected by a short video bus within a
laptop computer. Alternatively, the receiver 16 may be connected to
the transmitter 14 by a relatively short cable. Because the cable
impedance, signal attenuation, and reflection are proportional to
the cable length, signal degradation does not typically affect data
integrity for relatively short cables.
[0036] Table 1 below provides the maximum allowable attenuation for
a transmitted DVI signal.
TABLE-US-00001 TABLE 1 Maximum Attenuation Data Frequency Maximum
(MHz) Attenuation (dB) 1 0.14 10 0.45 50 1.0 100 1.5 200 2.1 400
3.0 700 4.3 1000 5.4
[0037] From Table 1, it can be seen that the maximum attenuation
for a data frequency rate of 825 MHz is approximately 5 dB, which
corresponds to a maximum cable length of about 5 meters.
Accordingly, to transmit DVI data over a cable in excess of 5
meters, equalization of the DVI data is usually required.
Additionally, as the cable length increases, signals on the DDC
data channel begin to degrade due to reflections and decreased rise
times. Thus, a DDC extender circuit may be used in conjunction with
an equalizer.
[0038] FIG. 2 is a block diagram of a digital communication system
20 comprising four equalizers 22, 24, 26, and 28 and a DDC extender
circuit 30. The four equalizers 22, 24, 26, and 28 each correspond
to one of the data channels 0, 1, 2, and the clock channel. While
each of these equalizers 22, 24, 26 and 28 may accommodate
different data rates, the equalizer 22, 24, and 26 are typically
matched equalizers as the data rate over each data channel is the
same. The equalizer 28 may be configured to accommodate a data rate
different than that of the equalizers 22, 24 and 26, as the clock
rate may be different than the data rate of the data channels 0, 1
and 2.
[0039] Each of the equalizers 22, 24, 26 and 28 comprise an
open-loop architecture in which the output signal of the equalizer
is not fed back to adjust the input signal to the equalizer, and
are configured to receive a DC balanced differential signal as the
input signal.
[0040] The DDC channel comprises a DDC data channel and DDC clock
channel, and the DDC extender circuit 30 comprises circuitry
serving both of these channels. Because the DDC channel is
typically a lower frequency channel as compared to the DVI data
channels, the DDC channel does not incorporate an equalizer
circuit. The DDC extender circuit 30 is located on a receiving end
of a transmission line and provides voltage clamping during data
transition from a positive voltage data signal to a zero voltage
data signal, and also provides a boost current during data
transition from a zero voltage data signal to a positive voltage
data signal.
[0041] The digital communication system 20 may be located on the
side of the transmitter 14, or on the side of the receiver 16, or
on both the side of the transmitter 14 and the receiver 16.
Typically, the DDC extender circuit 30 is located on the receive
end of the transmission line. Additionally, the DDC extender
circuit 30 may be located on both ends of the transmission line if
the transmission line is used for bi-directional communication. The
DDC extender circuit 30 need not be located on both ends of the
transmission line for bi-directional communication, however. For
example, the DDC extender circuit 30 may be located at the receiver
16, and the transmitter 14 may have different reflection and
impedance mitigation circuitry, or none at all.
[0042] The equalizers 22, 24, 26 and 28 may be located on the
receive end of the transmission line before the receiver 16, or on
the transmitting side of the transmission line after the
transmitter 14, or on both the receive end of the transmission line
before the receiver 16 and on the transmitting side of the
transmission line after the transmitter 14. FIGS. 3-5 show several
equalizer configurations. Because the positioning of the DDC
extender circuit 30 has already been discussed, reference to the
DDC extender circuit 30 is omitted from FIGS. 3-5.
[0043] FIG. 3 is a block diagram of an equalizer 40 configured to
equalize data signals received at a receive end of a transmission
line 32. The equalizer 40 may comprise equalizers 22, 24, 26 and
28, as described with reference to FIG. 2 above. In this
embodiment, the equalizer 40 is configured to compensate for
attenuation and dispersion of the DVI data signal received at the
receive end of a transmission line 32.
[0044] In one variation of this embodiment, the equalizer 40 is
configured to compensate for the length of the transmission line
32. For example, the equalizer 40 may be implemented in a remote
monitor having a 20-meter video cable 32. The equalizer 40 may then
be adjusted to compensate for frequency dependent attenuation
corresponding to a 20-meter long video cable.
[0045] In another variation of this embodiment, the equalizer 40
may be adjusted to compensate for a maximum length D of the video
cable 32. For example, the equalizer 40 may be implemented in a
remote monitor having a receptacle for receiving a video cable, and
the equalizer 40 is adjusted to compensate for a video cable 32
length of 30 meters. The remote monitor may thus be "rated" for a
maximum video cable length of 30 meters.
[0046] In yet another variation of this embodiment, the equalizer
40 may be configured to compensate for frequency dependent
attenuation caused by electrostatic discharge (ESD) protection
circuitry located at the input of the receiver 16. An exemplary ESD
protection circuit comprises a pair of diodes connected to a ground
potential and a high potential, with an output pin or receptacle
corresponding to a conductor of the transmission line 32 interposed
between the diodes. The diodes tend to act as low pass filters due
to their inherent capacitances, and thus attenuate the high
frequency components of a data signal. Accordingly, the equalizer
40 is configured to compensate for the diode capacitances such that
the output signal of the equalizer 40 includes restored high
frequency components of the original data signal.
[0047] FIG. 4 is a block diagram of an equalizer 42 configured to
pre-emphasize data signals to be transmitted on the transmission
line 32. The equalizer 42 may comprise equalizers 22, 24, 26 and
28, as described with respect to FIG. 2. For example, the equalizer
42 may be implemented in a computer device for generating video
signals and having a 20-meter video cable 32. The equalizer 42 may
then be adjusted to compensate for frequency dependent attenuation
corresponding to a 20-meter long video cable.
[0048] In another variation of this embodiment, the equalizer 42
may be adjusted to compensate for a maximum length D of the video
cable 32. For example, the equalizer 42 may be implemented in a
computer device for generating video signals and having a
receptacle for receiving a video cable, and the equalizer 42 is
adjusted to compensate for a video cable 32 length of 30 meters.
The computer device may thus be "rated" for a maximum video cable
length of 30 meters.
[0049] In yet another variation of this embodiment, the equalizer
42 may be configured to compensate for frequency dependent
attenuation caused by ESD protection circuitry located at the
output of the transmitter 14. The equalizer 42 is configured to
compensate for the ESD protection circuitry such that the output
signal of the equalizer 42 includes restored high frequency
components of the original data signal.
[0050] FIG. 5 is a block diagram of a pair of equalizers 44 and 46,
the first equalizer 44 configured to pre-emphasize data signals to
be transmitted on the transmission line 32, and the second
equalizer 46 configured equalize data signals received at a receive
end the transmission line 32. The equalizer 44 and 46 may be
configured in a similar manner as the equalizers 42 and 40, as
described with reference to FIGS. 3 and 4 above.
[0051] FIG. 6A is a block diagram of the system of FIG. 3. The
system includes tunable resistors 50, an ESD compensation circuit
60, an open-loop equalizer stage 70, and an output driver 80. A DVI
data channel typically implements a current mode output driver to
generate a differential current data signal that is transmitted
over the transmission line 32. The open-loop equalizer stage 70,
however, is configured to receive a differential voltage signal as
an input signal. Accordingly, the tunable resistors 50 are matched
to the impedance of the transmission line 32 and convert the
differential current data signal to a corresponding differential
voltage data signal.
[0052] The ESD compensation circuit 60 is configured to compensate
for the high frequency attenuation of the data signal in a manner
as described above with reference to FIG. 3, and the open-loop
equalizer stage 70 is configured to compensate for frequency
dependent attenuation in the data signal caused by the
characteristic impedance of the transmission line 32. Typically,
the ESD compensation circuit 60 may comprise an open-loop equalizer
stage similar to the open-loop equalizer stage 70. Accordingly, in
a variation of the embodiment of FIG. 6A, the ESD compensation
circuit may be combined with the open-loop equalizer stage 70.
[0053] The output driver 80 is configured to receive the equalized
data signal from the open-loop equalizer 70 and provide the
equalized data signal to processing circuitry, such as the display
controller 18 of FIG. 1. The output driver 80 may be a buffer
circuit, or may be a converter circuit operable to convert the
output differential voltage of the open-loop equalizer stage 70
into a differential current signal. The converter circuit may be
utilized as an output driver 80 in the case of a DVI repeater
stage, for example.
[0054] FIG. 6B is a block diagram of a transmit side of the system
of FIG. 4. The system includes resistors 52, an open-loop equalizer
stage 70, and an output driver 80. Because a DVI data channel
implements a current mode output driver to generate a differential
current data signal that is transmitted over the transmission line
32, the resistors 52 are used to covert the current data signal
into a corresponding differential voltage data signal. The
open-loop equalizer stage 70 is configured to provide pre-emphasis
for frequency dependent attenuation in the data signal caused by
the characteristic impedance of the transmission line 32 in a
manner such as described with reference to FIG. 4 above. The output
driver 80 is configured to convert the pre-emphasized differential
voltage data signal into a corresponding differential current data
signal for transmission over the transmission line 32.
[0055] While the embodiments of FIGS. 2-6B have been described with
reference to a DVI application, the ESD compensation circuit 60 and
the open-loop equalizer stage 70 may also be implemented in other
systems designed to transmit and receive DC balanced data signals.
The DC balanced data signals may be either differential current
data signals, as in the case of DVI data signals, or may be
differential voltage data signals, as in the case of other DC
balanced data signals.
[0056] FIG. 7 is a block diagram of an open-loop equalizer stage 70
utilized in the systems of FIGS. 3-6B. The open-loop equalizer
stage 70 comprises an equalizer input stage 72 and at least one
open-loop equalizer core gain stage 74. The equalizer input stage
72 is configured to receive a differential input voltage signal and
condition the differential input voltage signal for input into the
open-loop equalizer core gain stages 74. The conditioning may be an
adjustment of the differential voltage input signal to a DC bias
point, for example. The differential signal is DC balanced and
symmetric about a DC bias point.
[0057] A DC balanced data signal is a data signal comprising DC
characters having an average DC value. For example, a data signal
may be divided into 6-bit characters, and the DC value of each
6-bit character may be 2 volts (for a voltage signal) or 50
milliamps (for a current signal). In the case of DVI graphics data,
a graphics controller, such as the graphics controller 10 of FIG.
1, is operable to encode 8 bits of video data into a 10-bit TMDS DC
balanced character on each data channel. One exemplary method of
creating DC balanced data signals is described in the Digital
Visual Interface Specification, Revision 1.0, dated Apr. 2, 1999,
and published by Digital Display Working Group, the disclosure of
which is incorporated herein by reference.
[0058] The open-loop equalizer core gain stages 74 are configured
to receive the output of the equalizer input stage 70 and equalize
the voltage data signal by conditioning the signal through one or
more of the equalizer circuits described with reference to FIGS. 10
and 11 below. The open-loop equalizer core gain stages 74 comprise
an open-loop architecture in which the output signal of the
equalizer is not fed back to adjust the input signal to the
equalizer. Additionally, the open-loop equalizer core gain stages
74 need not utilize an automatic gain control (AGC) circuit.
Rather, the open-loop equalizer core gain stages 74 utilize an
input follower stage to provide adaptive equalization of the
differential data signal.
[0059] FIG. 8 is a timing diagram of one DC pulse in a DC balanced
data signal and a corresponding differential signal transmitted
over the transmission line and equalized by the open-loop equalizer
stage 70 of FIG. 7. The DC pulse may be either a current data
signal or a voltage data signal, depending on the particular
communication protocol implemented.
[0060] Axis A depicts an ideal data pulse with zero rise and fall
time and a period of t.sub.0, and axis B depicts a corresponding
differential data signal. The differential signal of axis B is
symmetric about the B axis that represents a DC value, and is
transmitted over a transmission line. The differential signal of
axis C depicts a received pulse corresponding to the differential
signal of axis B received at the received end of the transmission
line.
[0061] The received pulse of axis C illustrates the frequency
dependent attenuation of the high frequency components of the
differential signal of axis B as the signal propagates over the
transmission line. As can be seen by inspection of the data signal
of axis C, the transmission line low pass filters the differential
signal of axis B. Because the data signal is DC balanced, however,
crossing points over the DC value define the time period t.sub.0,
which corresponds to the time period of the ideal pulse of axis
A.
[0062] The open-loop equalizer stage 70 is configured to receive
the differential signal of axis C as input, compensate for the
frequency dependent attenuation of the transmission line, and
output an equalized differential data signal. Depending on the
length of the transmission line and the gain of the open-loop
equalizer stage 70, the received differential signal may undergo
proportional equalization or disproportionate equalization. Axes D
and E illustrate equalized data pulses for the case of proportional
equalization and disproportionate equalization, respectively. The
data signal of axis D has been proportionally equalized, i.e., the
open-loop equalizer stage 70 has provided a frequency dependent
gain that is nearly the inverse of the frequency dependent
attenuation caused by the transmission line.
[0063] The data signal of axis E, however, has undergone
disproportionate equalization, i.e., the open-loop equalizer stage
70 has provided a frequency dependent gain that results in gain
that is greater than the inverse of the frequency dependent
attenuation caused by the transmission line. Accordingly, the
differential data signal of axis E has a noticeable ripple due to
the disproportionate magnitude of the high frequency components.
Because the data signal is DC balanced, however, the crossing
points over the DC value define the time period t.sub.0, which
corresponds to the time period of the ideal pulse of axis A. The
open-loop equalizer core gain stage 74, therefore, does not require
an AGC circuit to adjust the output level of the equalized data
signal. Additionally, a monitor or similar receiving device
utilizing an open-loop equalizer stage 70 configured to provide
equalization up to a maximum cable length, e.g., 30 meters, may
thus be used with cables having cable lengths that are less than
the maximum cable length.
[0064] As previously described, the open-loop equalizer core stage
74 provides a frequency dependent gain that is the inverse of the
transmission loss due to the frequency dependent attenuation caused
by the transmission line. The two primary loss mechanisms in a
transmission line are skin effect and dielectric losses. These loss
mechanisms may be expressed as the following transfer function:
G(f)=e.sup.-L(k.sup.s.sup. {square root over (jf)}+k.sup.d.sup.|f|)
(1)
[0065] where f is the frequency, j= {square root over (-1)} is the
length of the transmission line, and k.sub.s and k.sub.d are the
skin and the dielectric loss constants, respectively. These losses
introduce both magnitude and, to a lesser extent, group delay
distortions in data signals transmitted over the transmission line
22. Generally, the skin effect dominates the low frequency losses,
while the dielectric loss dominates the high frequency losses.
[0066] An inverse function of G to compensate for these losses can
be realized by expressing 1/G(f) as:
1 G ( f ) = + L ( k s j f + k d f ) = 1 + .alpha. H ( f ) ( 2 )
##EQU00001##
[0067] where .alpha. is a factor proportional to the length of the
cable. This inverse gain function is implemented in the open-loop
equalizer core stages 74. A typical implementation may use several
open-loop equalizer core stages 74 in cascade to obtain the
required gain for a certain maximum loss, e.g., the maximum
attenuation depending on the length of the transmission line.
Ideally, the equalized signal at the output of the open-loop
equalizer core stages 74 will match the originally transmitted data
signal exactly if the transfer function H(f) can be replicated
exactly.
[0068] FIG. 9 is a block diagram of an input follower stage 90
implemented at the input stage of the open-loop equalizer core gain
stage 74 of FIG. 7. The input follower circuit 90 comprises an
amplifier 90 and a feedback block 94 having a gain .beta.. The
closed-loop output impedance of the feedback topology shown in FIG.
13 may be expressed as:
Z o = R o 1 + a .beta. ( 3 ) ##EQU00002##
[0069] where R.sub.o is the open-loop output impedance, .alpha. is
the open-loop gain and .beta. is the feedback gain. In one
embodiment, with .beta.=1, the open-loop gain may be approximated
by
a = A d c 1 + j .omega. .omega. p 1 ( 4 ) ##EQU00003##
[0070] where A.sub.dc is the dc gain of the amplifier 92,
.omega..sub.p1 is the dominant pole frequency of the amplifier 92
in radians per second, .omega. is the frequency in radians per
second and j= {square root over (-1)}. Substituting equation (4)
into equation (3) with .beta.=1, and assuming A.sub.dc and .omega.
are much smaller than dominant pole .omega..sub.p1, equation (3)
simplifies to:
Z o .apprxeq. R o .omega. p 1 + R o ( .omega. p 1 ) 2 j .omega. ( 5
) ##EQU00004##
[0071] The closed-loop output impedance of the feedback loop may be
approximated by a resistance, represented by the first term
R o .omega. p 1 , ##EQU00005##
in series with an inductance, represented by the second term
R o ( .omega. p 1 ) 2 j .omega. . ##EQU00006##
[0072] FIG. 10 is a circuit diagram on an embodiment of the
open-loop equalizer 74 of FIG. 7 utilizing the input follower stage
90 of FIG. 9. The open-loop equalizer core stage 74 comprises a
differential pair 100 that includes transistors 102 and 104, load
resistors 106 and 108, and current sinks 110 and 112.
[0073] While the transistors 102 and 104 are shown as field effect
transistors, other types of transistors may also be used. A
reactive load 120 comprising capacitors 122, 126, and 128 and
resistors 124, 130 and 132 is coupled to the differential pair 100
at the sources of the transistors 102 and 104. Typically, without
the input follower stages 90, inductors are usually added at the
drains of the transistors 102 and 104 to adjust the response of the
differential pair to match transfer function H(f). Such inductors
are typically large in size, requiring additional cost for silicon
area. Also, the large spiral structure of a physical inductor may
introduce unwanted noise to the circuit. However, as illustrated by
the derivation of equation (5), the input follower stages 90
eliminate the need for such an inductor.
[0074] The input follower stages 90 are realized by a pair of
amplifiers 140 and 142 configured to receive a differential voltage
data signal corresponding to the DVI communication data signals as
input and compare data signals received to a feedback signal from
the reactive load 120. Based on this comparison, the amplifiers 140
and 142 generate corresponding first and second input signals for
the transistors 102 and 104, respectively. In one embodiment,
feedback is a unity gain feedback signal, i.e., .beta.=1. The
open-loop equalizer core stages 74 of FIG. 10 utilize a practical
implementation of input follower stages 90 with
.beta..apprxeq.1.
[0075] In another embodiment, .beta. may be a value other than
unity, or may be a frequency dependent variable. For example,
.beta. may be an adaptive feedback variable.
[0076] In operation, the transistors 102 and 104 are operated in
the linear region. The capacitors 122, 136 and 128 are selected so
that the high frequency gain of the differential pair 100 will
approximate the transfer function H(f). The amplifiers 140 and 142
generate corresponding first and second input signals for the
transistors 102 and 104. In response to the first and second input
signals, the transistors adjust the corresponding drain currents
I.sub.D102 and I.sub.D104, respectively, which in turn induce a
voltage drop across resistors 106 and 108 to generate the equalized
differential output signals V- and V+. Accordingly, the
differential pair 100 operates in an open-loop configuration with
respect to the output data signals V- and V+ generated at the
resistors 106 and 108.
[0077] Thus, by selecting the particular values of the resistors
and capacitors of the reactive load 120, and by cascading multiple
open-loop equalizer core stages 74 such that the output of one of
the open-loop equalizer core stages 74 is connected to the input of
another of the open-loop equalizer core stages 74, the inverse gain
function 1/G(f) of equation (2) may be readily realized.
[0078] FIG. 11 is a block diagram of an ESD compensation circuit
170 utilizing the open-loop equalizer core gain stage 74 of FIG.
10. One conductor of a differential signal channel is shown in FIG.
11. The open-loop equalizer core stage 74 may be configured to
compensate for frequency dependent attenuation caused by ESD
protection circuitry located at the input of the receiver 16. The
exemplary ESD protection circuit 150 comprises a pair of diodes 152
and 154 connected to a high potential and a ground potential,
respectively, with an output pin or receptacle corresponding to the
conductor of the transmission line 32 interposed between the
diodes. A differential current sink 156 represents one of a pair of
differential signals. The differential current sink 156 generates a
differential voltage by inducing a voltage drop across a tunable
resistor 162.
[0079] FIG. 12 is a timing diagram of a data signal at several
points in the circuit of FIG. 11. The differential signal A depicts
the differential current signal at point A in the circuit of FIG.
11, and the differential signal B depicts the differential voltage
signal generated at point B in the circuit of FIG. 11. The diodes
152 and 154 tend to act as low pass filters due to their inherent
capacitances, and thus attenuate the high frequency components of
the differential signal at point B. Accordingly, the ESD
compensator circuit 170 is configured to compensate for the diode
capacitances such that the output signal at point C includes
substantially restored high frequency components of the original
current data signal observed at point A.
[0080] The compensation is realized by configuring the reactive
load 120 of the open-loop equalizer core gain stage 74 of FIG. 10
to provide an inverse gain of the low pass filter effect of the ESD
protection circuit 150. For example, if the diodes 152 and 154 are
modeled as single pole low pass filters having a filter response
G(f), then the reactive load 120 is configured to provide the
inverse gain function 1/G(f).
[0081] The open-loop equalizer core gain stages 74 may also be used
to compensate for any intermediate circuitry between the
transmitter 14 and the receiver 16; the ESD protection circuit 150
is but one example of such intermediate circuitry. Other
intermediate circuitry may also include signal repeaters,
transmission line taps, and the like.
[0082] FIGS. 3-12 depict various embodiments of a system for
facilitating the transmission and reception of DC balanced
differential data signals, and with particular illustrative
emphasis on DVI data signals. The DVI specification also supports
the VESA Display Data Channel (DDC), which enables the computer
display, the computer, and a graphics adapter to communicate and
automatically configure the system to support different features
available in the computer display. The DDC link is typically a
lower bandwidth signal, e.g., 400 kHz, and thus may be transmitted
over a longer cable length than the DVI data signal. Accordingly,
equalization of the DDC data and clock signals is typically not
required. However, the transmission line over which the DDC data
and clock signals are transmitted is typically not terminated in an
impedance match, and thus reflections in the DDC cable may degrade
the DDC signal as the DDC cable length increases. Furthermore, the
bandwidth of the DDC signal is limited by the amount of pull-up
current injected into the DDC cable during a transition from a low
voltage signal (e.g., logic 0) to a high voltage signal (e.g.,
logic 1).
[0083] Accordingly, a DDC extender circuit 30 may be used to extend
the DDC channel over a transmission line. FIG. 13 is a block
diagram of the DDC extender circuit 30 connected to the receive end
of a transmission line 200. The DDC channel typically transmits a
voltage signal, as illustrated by a simple transistor driver 202
with a load transistor 204 interposed between the output terminal
of the transistor 202 and a positive voltage V.sub.DD.
[0084] On the receive end of the transmission line 200, a rail
clamp circuit comprises a pair of diodes 206 and 208 connected to a
ground potential and V.sub.DD, respectively, with an output pin or
receptacle corresponding to a conductor of the transmission line
200 interposed between the diodes.
[0085] The DDC extender circuit 30 comprises a voltage clamp
circuit 300 and a current booster circuit 400. The voltage clamp
circuit 300 is operable to provide voltage clamping during data
transition from a positive voltage data signal to a zero voltage
data signal, and the current booster circuit 400 is operable to
provide a boost current during data transition from a zero voltage
data signal to a positive voltage data signal.
[0086] Typically, the length of the transmission cable 200 causes
inductive clamping at a receive end and also results in bandwidth
limitations. A DDC link typically utilizes an Inter-IC (I2C) bus as
the transmission line 200, which is a bi-directional two-wire
serial bus that provides a communication link between integrated
circuits (ICs). With respect to inductive clamping, the falling
edge of the transmission line 200 voltage data signal is relatively
short, because the element employed for asserting a logic 0 on the
transmission line 200 is typically the transistor 202 having a low
`on` resistance.
[0087] As shown in FIG. 13, the receiving end of the transmission
line 200 has a terminating impedance that is effectively an
open-circuit, limited only by the rail clamping diodes 206 and 208.
Additionally, the transmitting end of the transmission line 200 has
a terminating impedance that is relatively small, and may be
modeled as a short-circuit. Due to the lack of a matched
termination at either the transmitting end or the receiving end of
the transmission line 200, there are multiple reflections after the
falling edge of the data signal is received at the receive end of
the transmission line 200. These reflections can persist for
several microseconds for transmission line lengths on the order of
50 meters.
[0088] FIGS. 14-17 are timing diagrams illustrating the receive end
response during a data signal transition to the logic 0 level,
e.g., from a positive voltage level to a zero voltage level. FIG.
14 illustrates the transmission line 200 voltage during steady
state for a logic 1 data value. The transmission line 200 is
charged to V.sub.DD, and all energy in the transmission line 200 is
stored in the line capacitance.
[0089] FIG. 15 illustrates a logic 0 data signal propagating from
x=0 toward x=X along the transmission line 200. FIG. 15 assumes
that the resistance of the transistor 202 is negligible in
comparison to the characteristic impedance of the transmission line
200, which is typically around 100 ohms. Because the transmission
line 200 voltage is essentially shorted to a logic 0 potential,
e.g., a ground potential, the stored energy in the transmission
line 200 capacitance must transfer to inductive energy as the data
signal propagates through the transmission line 200, and thus the
current pulse I.sub.x is induced. The magnitude of the current
pulse is approximately -V.sub.DD/Z.sub.o.
[0090] FIG. 16 illustrates the effect of a voltage clamp on the
line reflection current I.sub.x and transmission line 200 voltage
characteristic. When the falling edge of the data signal arrives at
the receive end of the transmission line 200 for the first time,
the receive end voltage will swing negative, i.e., below a logic 0
level, and activate a clamping device (e.g. the voltage clamp
circuit 300, or the diode 208 if the voltage clamp circuit 300 is
not present).
[0091] If the receive end voltage falls below the logic 0 level,
then the receive end will ring with multiple reflections. For
example, without a voltage clamp, the voltage at x=X would ring to
a value of -V.sub.DD, and I.sub.x would drop to zero as the energy
in the line is forced to switch from inductive energy back to
capacitive energy. This behavior is analogous to an LC `tank`
circuit. The voltage and current in the transmission line 200 would
continue to ring at diminishing amplitudes as the energy in the
line is dissipated by resistive losses of the transmission line
200.
[0092] A clamping device, such as the diode 208, may be used to
limit the negative voltage swing to a value of -V.sub.CLAMP, which
attenuates the magnitude of the ringing at the receive end of the
transmission line 200. Nevertheless, the ringing around the logic 0
level may compromise the noise margin of the DDC link. Furthermore,
if the ringing persists through the period of the data signal, then
the ringing may impair the detection of a transition from a logic 0
level to logic 1 level. Additionally, the conduction of current in
the clamping device, such as diode 208, may cause significant
injection of minority carriers into the substrate of the receiver
chip, which in turn may cause a malfunction of the receiver
operation. Typical negative clamp currents are 50 milliamps for 5V
signal, and 30 milliamps for 3.3V signal.
[0093] When the receive end voltage is clamped to the logic 0
level, however, the resulting reflections are of negligible
amplitude. Accordingly, a voltage clamp circuit 300 may be
connected in parallel with the clamping diode 208 at the receive
end of the transmission line 200. While the diode 208 is designed
to conduct when a received falling edge of the data signal falls
below the logic 0 level, the voltage clamp circuit 300 may absorb
the negative pulse and prevent conduction of the diode 208.
[0094] FIG. 18 is a schematic representation of the transmission
line after activation of the voltage clamp circuit 300. The voltage
clamp circuit 300 clamps the receive end of the transmission line
200 to a logic 0 level (e.g., 0 volts, a ground potential, etc.).
Because the transmit end of the transmission line 200 is also at
the logic 0 level, the transmission line 200 capacitance is
essentially eliminated. The transmission line 200 may then be
modeled in terms of its line inductance 220, as depicted in FIG.
18. In addition to the line inductance 220, the transmission line
200 also has a line resistance 222. The receiver input resistance
230 and the transistor 202 output resistance 232 are also included,
as the transmission line 200 is loaded by these resistances at both
ends.
[0095] FIG. 19 is a timing diagram of the current in the
transmission line after activation of the voltage clamp circuit
300. The transmission line 200 current I.sub.x decays exponentially
based on a time constant .tau.=L/R, where L is the line inductance
220 and R is the sum of the resistances 222, 230, and 232. The
voltage clamp circuit 300, by clamping the receive end of the
transmission line 200 to a ground potential, causes the duration of
the current flowing in the transmission line 200 to increase as
compared to the duration of the transmission line 200 current
I.sub.x when the transmission line is clamped to a negative value.
The voltage at the receive end of the transmission line, however,
remains at a logic 0 value. Accordingly, voltage oscillations in
the receive end of the transmission line 200 are eliminated.
[0096] While the voltage clamp circuit 300 facilitates a data
transition from a logic 1 to a logic 0 value on the transmission
line 200, it does not primarily facilitate the rise time of a data
transition from a logic 0 to a logic 1 value. The I2C architecture
utilized by the DDC link uses either a passive pull-up resistor or
fixed current source to assert a logic `1` on the transmission line
200, and thus only a finite amount of current is available to
charge the transmission line 200 capacitance. Accordingly, there is
an implicit bandwidth limitation imposed by the transmission line
200 capacitance that is proportional to a product of the pull-up
resistance R and the line capacitance C.
[0097] A pull-up resistor in the range of 1.5K-2.2K may be used,
which will typically limit a DDC link operating at a clock speed of
100 kHz to about 10 meters. A transmission line 200 in excess of
this length will a cause decrease in the rise time for the rising
edge of the voltage data signal. Increasing the length of the
transmission line 200 increases the line capacitance, which will
eventually result in the slew-rate of the 0-1 data transition to be
too small to allow the rising edge of the data signal to cross a
logic level detection threshold in the receiver within a specified
time period.
[0098] FIG. 20 is a timing diagram of the DDC data signal received
at the receive end of the transmission line 200 and with a voltage
clamp circuit 300 connected to the receive end of the transmission
line 200. The timing diagram corresponds to a 100 kHz clock signal
transmitted over 50 meters of transmission line having an
inductance of 1 uII/m, a capacitance of 90 pF/m, and a resistance
of 125 mOhms/m. The voltage clamp 300 prevents oscillations of the
receive end voltage during a transition from a logic 1 to a logic 0
value.
[0099] The RC ramp results in a trapezoidal appearance of the
attenuated logic `1` pulses following an initial voltage step
during a positive transition from logic 0 to logic 1. The initial
voltage step preceding the RC ramp is caused by the inductive
energy trapped in the line by the action of the voltage clamp 300
being released as the transistor 202 turns off to provide a logic 1
value to the transmission line 200. Because the voltage clamp 300
stores inductive energy in the transmission line 200, the voltage
clamp 300 provides a secondary utility of slightly increasing the
rise time of a positive data transition. However, the inductive
energy stored in the transmission line is typically not enough to
fully pull the data signal to a logic 1 level, as shown in FIG.
20.
[0100] While the value of the resistor 204 may be reduced to
increase the pull-up current at the transmitting end of the
transmission line 200, the additional pull-up current would require
an increased power rating of the transistor 202 (or other suitable
driving device). Accordingly, a current booster circuit 400 is
connected to the receive end of the transmission line 200.
[0101] FIG. 21 is a block diagram of the DDC extender circuit 30 of
FIG. 14. The current booster circuit 400 is operable to inject a
boost current at the receive end of the transmission line 200
during a positive transition of the data signal. The current
booster circuit 400 illustratively comprises a positive transition
detector 402 and a switchable current source 404. The positive
transition detector 402 is operable to determine the occurrence of
a positive voltage transition from a logic 0 value to a logic 1
value, and to active the switchable current source 404 during the
detection of such a positive transition. In one embodiment, the
current booster circuit 400 provides the boost current to the
receive end of the transmission line 200 when the data signal
exceeds a first reference value and eliminates the boost current
from the receive end of the transmission line 200 when the data
signal exceeds a second reference value.
[0102] By providing additional pull-up current only for the
duration of a positive data transition, open-collector signal
devices on the transmission line 200 do not conduct at the same
time as the boost current is being injected into the line, and thus
the current booster circuit 400 is transparent to existing
transmitting devices.
[0103] Furthermore, the current booster circuit 400 also provides a
boost current at the receive end of the transmission line 200 when
a digital signal is transmitted from the receive end. Accordingly,
the current booster circuit 400 not only facilitates reception of
digital signals at the receive end of the transmission line 200, it
also facilitates the transmission of digital signals from the
receive end of the transmission line 200. Thus, if the transmission
line 200 is a bi-directional communication line, the current
booster circuit 400 will provide a boost current at the receive end
of the transmission line 200 when the voltage at the receive end
transitions from a low state to a high state due to either
reception of a digital signal from a transmitting device at the
other end of the transmission line 200, or to the generation of a
digital signal from a transmitting device connected to the receive
end of the transmission line 200. Accordingly, bandwidth for both
the transmission and reception of data may be increased.
[0104] FIG. 22 is a schematic diagram of one embodiment of the DDC
extender circuit 30 of FIG. 14. The voltage clamp circuit 300
comprises a comparator 302 having a noninverting input connected to
ground and an inverting input connected to the receive end of the
transmission line 200. The comparator output is connected to the
gate of a transistor 304, which in turn has a drain connected to
ground and a source connected to the receive end of the
transmission line 200.
[0105] During operation of the voltage clamp 300, when the voltage
V.sub.L at the receive end of the transmission line 200 is greater
than the ground potential, the comparator 302 outputs a low signal,
which turns off the transistor 304, thus isolating the receive end
of the transmission line 200 from ground. Conversely, when the
voltage V.sub.L at the receive end of the transmission line 200 is
less than or equal to the ground potential, the comparator 302
outputs a high signal, which turns on the transistor 304, thus
coupling the receive end of the transmission line 200 to ground.
Accordingly, the receive end of the transmission line 200 remains
clamped to the ground potential until a positive voltage signal is
applied to the transmission line 200.
[0106] While a field effect transistor 304 has been illustrated,
other switching devices, such as a bipolar junction transistor, may
also be used. Additionally, a positive offset voltage may also be
interposed between the noninverting terminal of the comparator 302
and ground so that the receive end of the transmission line 200 is
clamped to ground when the receive end of the transmission line 200
is within a noise margin, e.g., 1 mV, 10 mV, or some other noise
margin.
[0107] The current booster circuit 400 comprises a first comparator
412 and a second comparator 414. The first comparator 412 has an
inverting input terminal set at a potential of V.sub.TH1, which is
equal to V.sub.DD-V.sub.1. The noninverting input of the first
comparator 412 is connected to the receive end of the transmission
line 200. Accordingly, when the receive end voltage V.sub.L of the
transmission line 200 is greater than V.sub.TH1, the output of the
comparator 412 is high, and when the receive end voltage V.sub.L of
the transmission line 200 is less than V.sub.TH1, the output of the
comparator 412 is low.
[0108] Likewise, the second comparator 414 has a noninverting input
terminal set at a potential of V.sub.TH0, which is equal to a
ground potential offset by a positive voltage V.sub.0 The inverting
input of the second comparator 414 is connected to the receive end
of the transmission line 200. Accordingly, when the receive end
voltage V.sub.L of the transmission line 200 is greater than
V.sub.TH0, the output of the comparator 414 is low, and when the
receive end voltage V.sub.L of the transmission line 200 is less
than V.sub.TH0, the output of the comparator 414 is high.
[0109] Thus, the first and second reference values V.sub.TH0 and
V.sub.TH1 define a low and high noise margin, respectively.
Comparator 412 outputs a high signal when the receive end voltage
V.sub.L of the transmission line 200 is above the high noise margin
V.sub.TH1, and comparator 414 outputs a high signal when the
receive end voltage V.sub.L of the transmission line 200 is below
the low noise margin V.sub.TH0.
[0110] The output of the comparator 412 is connected as a reset
input to a latch 420, and the output of the comparator 414 is
connected as a set input to the latch 420, and also to an inverter
422. The output of the latch 420 and the output of the inverter 422
are provided as input to a NAND gate 424, which in turn is used to
drive transistor 426. When the transistor 426 is on, a boost
current I.sub.B is injected into the receive end of the
transmission line 200. A resistor 428 coupled between the drain and
the receive end of the transmission line 200 governs the magnitude
of the boost current I.sub.B. Alternatively, the resistor 428 could
be replaced by a current mirror implementation of the transistor
426 drive circuitry. Other current source circuitry may also be
used.
[0111] Operation of the current booster circuit 400 is described
with reference to Table 2 below, which provides a state table
corresponding to the receive end voltage V.sub.1 of the
transmission line 200 during a 1-0-1 logic transition.
TABLE-US-00002 TABLE 2 State Transition Table V.sub.L S R Q S'
(QS')' I.sub.B 1 0 1 0 1 1 OFF V.sub.TH1- 0 0 0 1 1 OFF V.sub.TH0-
1 0 1 0 1 OFF 0 1 0 1 0 1 OFF V.sub.TH0+ 0 0 1 1 0 ON V.sub.TH1+ 0
1 0 1 1 OFF 1 0 1 0 1 1 OFF
[0112] When the receive end line voltage V.sub.L is high, e.g. at a
logic 1 level or V.sub.DD, the output of the NAND gate 424 is high,
and thus the transistor 426 is off, which prevents injection of the
boost current I.sub.B. As the receive end line voltage V.sub.L
falls below the upper threshold V.sub.TH1, the output of the
comparator 412 goes low, and the reset input to the latch 420
likewise goes low. Consequently, there is no state change in the
latch 420 output, and the transistor 426 remains off.
[0113] As the receive end line voltage V.sub.L falls below the
lower threshold value V.sub.TH0, the latch 420 is set. However, the
output of the inverter 422 switches from a high state to a low
state, and thus the output of the NAND gate 424 remains high.
Accordingly, the transistor 426 remains off.
[0114] No state change is induced until the receive end line
voltage V.sub.L exceeds the lower threshold V.sub.TH0 during a
positive voltage transition. At this time, the output of the
comparator 414 goes low, which in turn causes the output of the
inverter 422 to go high. Accordingly, both inputs to the NAND gate
424 are high, which in turn causes the output of the NAND gate 424
to go low. The transistor 426 is thereby turned on, and the boost
current I.sub.B is injected into the receive end of the
transmission line 200.
[0115] The transistor 426 remains in an on state until the receive
end line voltage V.sub.L exceeds the upper threshold voltage
V.sub.TH1, which causes the latch 420 to reset. Accordingly, the
output of the latch 420 goes low, which in turn causes the output
of the NAND gate 424 to go high, shutting off the transistor 426
and eliminating the boost current I.sub.B. The current booster
circuit 400 is then in the original state, and the process of
injecting a boost current I.sub.B is then repeated during the next
1-0-1 logic transition.
[0116] The threshold V.sub.TH0 is typically set high enough so that
noise immunity is not compromised, but not so high that significant
duty-cycle distortion results from the delay of the turn-on boost
current I.sub.B. The low impedance of the signal device driving the
`0` state on the transmission line 200, together with the inductive
energy stored by the voltage clamp circuit 300 may be considered
when selecting V.sub.TH0.
[0117] As illustrated in Table 2, the comparators 412 and 414 form
a level detector operable to output a plurality of 2-bit data
signals corresponding to the voltage level V.sub.1 at the receive
end of the transmission line 200 with respect to the lower
threshold value V.sub.TH0 and the upper threshold voltage
V.sub.TH1. The data signals are input into the Set and Reset inputs
of the latch 420 and the inverter 422 to generate the NAND gate 424
input signals, the output of which drives the transistor 426.
[0118] FIG. 23 is a timing diagram of the DDC data signal received
at the receive end of the transmission line 200 with a boost
current injected into the transmission line 200. In the example of
FIG. 23, the resistor 428 is illustratively 150 ohms, and the
pull-up resistor in the transmitting device (e.g., resistor 204 of
FIG. 13) is illustratively 2.2 kohms. The rising edge of the data
signal is nearly vertical after the boost current I.sub.B is
injected, representing the added voltage pull-up of the boost
current I.sub.B and stored inductive energy. After the stored
inductive energy dissipates, the boost current I.sub.B still
provides additional voltage pull-up until the data signal exceeds
the upper noise margin threshold V.sub.TH1, at which time the boost
current I.sub.B is eliminated.
[0119] The systems and methods herein have been described with
reference to an illustrative DVI-compliant system, but are not
limited to the illustrative DVI-compliant system. For example, the
equalizer core gain stages 74 may be used to equalize any
DC-balanced differential signal. The DC-balanced signal may be a
differential voltage signal, or may be a differential current
signal that is converted to a corresponding differential voltage
signal. Likewise, the voltage clamp circuit 300 and the current
booster circuit 400 of the DDC extender circuit 30 may be used for
receiving any type of digital data signals or digital clock
signals, and are thus not limited to the illustrative DDC channel
implementation.
[0120] Additionally, the equalizer core gain stages 74 and the DDC
extender circuit 30 may be implemented on a single receiver chip,
or, alternatively, may be implemented on different receiver chips.
For example, if the equalizer core gain stages 74 are configured to
operate at the same power supply voltage as that of the DDC
extender circuit 30, both circuits may be provided on a single
receiver chip. Alternatively, if the DDC extender circuit 30 and
the equalizer core gain stages 74 are configured to operate at
different power supply voltages, e.g., 5 V and 3.5 V, respectively,
then the DDC extender circuit 30 and the equalizer core gain stages
74 may be located on different receiver chips.
[0121] This written description uses illustrative embodiments to
disclose the invention, including the best mode, and also to enable
a person of ordinary skill in the art to make and use the
invention. Other embodiments are within the scope of the claims if
they have elements that do not differ from the literal language of
the claims, or have equivalent elements.
* * * * *