U.S. patent application number 12/700428 was filed with the patent office on 2010-06-03 for system and method for forming metal interconnection in image sensor.
Invention is credited to Kyeong-Keun Choi.
Application Number | 20100133642 12/700428 |
Document ID | / |
Family ID | 38214342 |
Filed Date | 2010-06-03 |
United States Patent
Application |
20100133642 |
Kind Code |
A1 |
Choi; Kyeong-Keun |
June 3, 2010 |
SYSTEM AND METHOD FOR FORMING METAL INTERCONNECTION IN IMAGE
SENSOR
Abstract
A method for forming a metal interconnection in an image sensor
includes forming a first interlayer dielectric (ILD) layer having a
contact plug over a substrate, forming a diffusion barrier layer
over the first ILD layer, performing a forming gas annealing,
forming a second ILD layer over the diffusion barrier layer,
etching the second ILD layer and the diffusion barrier layer to
form a trench, forming a conductive layer to fill the trench, and
planarizing the conductive layer to form a metal interconnection
electrically connected to the contact plug
Inventors: |
Choi; Kyeong-Keun;
(Chungcheongbuk-do, KR) |
Correspondence
Address: |
MCANDREWS HELD & MALLOY, LTD
500 WEST MADISON STREET, SUITE 3400
CHICAGO
IL
60661
US
|
Family ID: |
38214342 |
Appl. No.: |
12/700428 |
Filed: |
February 4, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11641788 |
Dec 20, 2006 |
7678688 |
|
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12700428 |
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Current U.S.
Class: |
257/459 ;
257/751; 257/E21.575; 257/E23.011; 257/E31.11; 438/627; 438/98 |
Current CPC
Class: |
H01L 27/14687 20130101;
H01L 27/14636 20130101; H01L 21/76801 20130101; H01L 21/76828
20130101 |
Class at
Publication: |
257/459 ; 438/98;
438/627; 257/751; 257/E31.11; 257/E21.575; 257/E23.011 |
International
Class: |
H01L 31/02 20060101
H01L031/02; H01L 31/18 20060101 H01L031/18; H01L 21/768 20060101
H01L021/768; H01L 23/48 20060101 H01L023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 29, 2005 |
KR |
1020050134203 |
Claims
1. A method for forming a metal interconnection in an image sensor,
the method comprising: forming a first interlayer dielectric (ILD)
layer having substantially planar upper and lower surfaces and a
contact plug that extends from the upper surface to the lower
surface over a substrate; forming a diffusion barrier layer over
the first ILD layer; and performing a forming-gas annealing process
after said forming a diffusion barrier layer.
2. The method of claim 1, further comprising forming a second ILD
layer over the diffusion barrier layer.
3. The method of claim 2, wherein the second ILD layer has a
multi-layered structure.
4. The method of claim 2, further comprising forming a silicon-rich
oxide layer over the second ILD layer.
5. The method of claim 2, wherein the second ILD layer comprises a
fluorinated silicate glass (FSG) layer containing nitrogen.
6. The method of claim 5, wherein the FSG layer includes one of
N.sub.2 or N.sub.2O.
7. The method of claim 5, wherein the FSG layer is formed by
flowing a mixture gas at a flow rate of N.sub.2 ranging from
approximately 300 sccm to approximately 3,000 sccm, a flow rate of
N.sub.2O ranging from approximately 400 sccm to approximately 2,000
sccm, a flow rate of SiH.sub.4 ranging from approximately 100 sccm
to approximately 800 sccm, or a flow rate of SiH.sub.4 ranging from
approximately 300 sccm to approximately 1,000 sccm.
8. The method of claim 5, wherein the FSG layer is formed under a
pressure ranging from approximately 0.1 Torr to approximately 10
Torr.
9. The method of claim 2, further comprising etching through the
second ILD layer and the diffusion barrier layer to form a
trench.
10. The method of claim 1, further comprising filling a trench with
a conductive material that is electrically connected to the contact
plug.
11. The method of claim 1, further comprising planarizing a
conductive layer and an upper surface of a conductive material.
12. The method of claim 1, wherein the diffusion barrier layer
comprises one of SiC or SiN.
13. The method of claim 1, wherein said performing a forming-gas
annealing process is performed in a mixture gas ambient of H.sub.2
and N.sub.2 under a condition that a ratio of H.sub.2/N.sub.2 is in
a range of approximately 3% to approximately 30%.
14. The method of claim 1, wherein said performing a forming-gas
annealing process occurs at a temperature ranging from
approximately 400.degree. C. to approximately 600.degree. C. for
approximately 10 minutes to approximately 3 hours.
15. The method of claim 1, wherein the contact plug comprises
tungsten with a Ti/TiN bilayer stacked.
16. An image sensor comprising: a first interlayer dielectric (ILD)
layer having substantially planar upper and lower surfaces and a
contact plug that extends from the upper surface to the lower
surface over a substrate; a diffusion barrier layer disposed over
the first ILD layer; a second ILD layer disposed over the diffusion
barrier layer; a trench etched through the second ILD layer and the
diffusion barrier layer; and a conductive material within the
trench, wherein the conductive layer is electrically connected to
the contact plug.
17. The image sensor of claim 16, wherein the second ILD layer has
a multi-layered structure.
18. The image sensor of claim 16, further comprising a silicon-rich
oxide layer disposed over the second ILD layer.
19. The image sensor of claim 16, wherein the second ILD layer
comprises a fluorinated silicate glass (FSG) layer containing
nitrogen.
20. The image sensor of claim 19, wherein the FSG layer includes
one of N.sub.2 or N.sub.2O.
21. The image sensor of claim 16, wherein the diffusion barrier
layer comprises one of SiC or SiN.
22. The image sensor of claim 16, wherein the contact plug
comprises tungsten with a Ti/TiN bilayer stacked.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser.
No. 11/641,788, entitled "Method for Forming Metal Interconnection
In Image Sensor," filed Dec. 20, 2006, now U.S. Pat. No. ______,
which, in turn, claims priority of Korean patent application number
10-2005-0134203, filed on Dec. 29, 2005, both which are
incorporated by reference in their entireties.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a method for fabricating an
image sensor, and more particularly, to a method for forming a
metal interconnection in an image sensor.
[0003] An image sensor is a device for converting one or two- or
higher-dimensional optical image into an electrical signal. The
image sensor is mainly classified into a camera tube and a
solid-state image sensor. The camera tube has been widely used in
layer, control, recognition, etc, employing an image processing
technology on the basis of a television, and its application
technology has been developed. As the solid-state image sensor,
which comes into a market currently, there are metal oxide
semiconductor (MOS) image sensors and charge coupled devices
(CCDs).
[0004] The CMOS image sensor converts an optical image into an
electrical signal using a CMOS fabrication technology, and employs
a switch mode to detect outputs one by one using MOS transistors
which are made as many as the number of pixels. In particular, the
CMOS image sensor has advantages in that a driving mode is simple,
various scanning modes can be embodied, and a signal processing
circuit can be integrated into a single chip, which can miniaturize
a chip. In addition, the CMOS image sensor is inexpensive and
consumes a low power, because of utilizing a compatible CMOS
technique.
[0005] Recently, to reduce a noise, various attempts have been made
to reduce an interlayer thickness between metal interconnections in
fabricating an image sensor. One of them is to form a copper (Cu)
interconnection using damascene process. The reason is that the
copper has excellent interconnection characteristic in spite of
relatively small thickness because it has a lower electrical
conductivity than aluminum (Al).
[0006] In the method for fabricating the image sensor using the
copper interconnection, an annealing process is additionally
performed using a forming gas for reducing a dark current in a
device after a padding process. Generally, the dark current
characteristic can be reduced if the annealing process is performed
at a high temperature of 400.degree. C. or higher. This
characteristic can be understood from Fick's diffusion equation as
below.
C(x,t)=erfc(x/(4Dt).sup.1/2) [Diffusion Equation]
D=D.sub.o*exp(-E.sub.a/kT)
[0007] where D, t, C, E.sub.a denote diffusion coefficient, time,
concentration, and activation energy, respectively.
[0008] However, it may be difficult to perform the annealing
process at a high temperature of 450.degree. C. or higher due to a
thermal degradation of the copper interconnection.
SUMMARY OF THE INVENTION
[0009] Embodiments of the present invention are directed to provide
a method for forming a metal interconnection in an image sensor,
which can secure thermal stability of a metal interconnection and
improve dark current characteristic.
[0010] In accordance with an aspect of the present invention, there
is provided method for forming a metal interconnection in an image
sensor, including: forming a first interlayer dielectric (ILD)
layer having a contact plug over a substrate; forming a diffusion
barrier layer over the first ILD layer; performing a forming gas
annealing; forming a second ILD layer over the diffusion barrier
layer; etching the second ILD layer and the diffusion barrier layer
to form a trench; forming a conductive layer to fill the trench;
and planarizing the conductive layer to form a metal
interconnection electrically connected to the contact plug.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIGS. 1A to 1D illustrate cross-sectional views of a method
for forming a metal interconnection in an image sensor in
accordance with a preferred embodiment of the present
invention.
DESCRIPTION OF SPECIFIC EMBODIMENTS
[0012] FIGS. 1A to 1D illustrate cross-sectional views of a method
for forming a metal interconnection in an image sensor in
accordance with a preferred embodiment of the present invention.
Referring to FIG. 1A, a first interlayer dielectric (ILD) layer 12
is formed on a substrate 11. Herein, although not shown, the
substrate 11 includes a device isolation structure and a
transistor.
[0013] The first ILD layer 12 is selectively etched to form a
contact hole 13. Although not shown, a photoresist layer is formed
on the first ILD layer 12 and is exposed and developed to form a
photoresist pattern exposing a predetermined region where the
contact hole 13 will be formed. After forming the contact hole 13
by etching the first ILD using the photoresist pattern as an etch
mask, the photoresist pattern is removed using oxygen plasma.
[0014] A conductive material is formed to fill the contact hole 13,
and thereafter the conductive material is planarized using the
first ILD layer 12 as a target, thereby forming a contact plug 14.
Here, the contact plug 14 may be formed of tungsten with a Ti/TiN
bilayer stacked.
[0015] A first diffusion barrier layer 15 is formed on the
resultant structure. Herein, the first diffusion barrier layer 15
may be formed of SiC or SiN. Afterwards, a forming gas annealing is
performed in a mixture gas ambient of H.sub.2 and N.sub.2 under a
condition that a ratio of H.sub.2/N.sub.2 is in the range of
approximately 3% to approximately 30%. The annealing process is
performed at a high temperature ranging from approximately
400.degree. C. to approximately 600.degree. C. for approximately 10
minutes to approximately 3 hours.
[0016] Such a pad annealing process can maximize
metal-insulator-metal (MIM) capacitor reliability and device
reliability by eliminating side effects in advance which may occur
in a subsequent process of the MIM capacitor.
[0017] Referring to FIG. 1B, a second ILD layer 16 is formed on the
first diffusion barrier layer 15. The second ILD layer 16 is formed
of fluorinated silicate glass (FSG) containing nitrogen. In case of
using the FSG containing nitrogen, it is possible to improve the
dark current characteristic in virtue of high hydrogen
concentration because of N--H contained in the FSG thin film. Other
dielectric materials, such as a CVD SiOC low-k dielectric material
and a spin on dielectric (SOD) low-k dielectric material, can be
used as the second ILD layer 16.
N.sub.2+SiH.sub.4+N.sub.2O+SiF.sub.4SiOF(N, NH) [Formula 1]
SiH.sub.4+SiF.sub.4+CO.sub.2SiOF(C)
[0018] The dark current characteristics according to a kind of an
insulating layer formed through chemical reaction represented as
the above formula 1 will be listed as table 1 below.
TABLE-US-00001 TABLE 1 Insulating Layer Dark Current SiOF(N, NH)
1~20 code(s) SiOF(C) 15~100 codes
[0019] Referring to Table 1, the insulating layer containing N and
NH represents dark current of 1 to 20 codes, but the insulating
layer containing C represents dark current of 15 to 100 codes.
Thus, it is understood that the insulating layer containing N and
NH shows excellently low dark current performance.
[0020] The process for forming the second ILD layer 16 containing N
and NH is performed by mixing N.sub.2, SiH.sub.4, N.sub.2O and
SiF.sub.4 as illustrated in formula 1. Specifically, this process
may be performed under a pressure ranging from approximately 0.1
Torr to approximately 10 Torr at a flow rate of N.sub.2 ranging
from approximately 300 sccm to approximately 3,000 sccm, a flow
rate of N.sub.2O ranging from approximately 400 sccm to
approximately 2,000 sccm, a flow rate of SiH.sub.4 ranging from
approximately 100 sccm to approximately 800 sccm, and a flow rate
of SiF.sub.4 ranging from approximately 300 sccm to approximately
1,000 sccm.
[0021] Although not shown, a silicon-rich oxide layer may be
additionally formed to solve a limitation caused by nitrogen
contained in the second ILD layer 16 during photoexposure for
forming a trench for metal interconnection. The silicon-rich oxide
layer may be formed to a thickness ranging from approximately 500
.ANG. to approximately 2,000 .ANG..
[0022] The second ILD layer 16 is etched to form a first trench 17.
To this end, although not shown, a photoresist layer is formed on
the second ILD layer 16 and is exposed and developed to form a
photoresist pattern exposing a predetermined region where the first
trench 17 will be formed. The second ILD layer 16 and the diffusion
barrier layer 15 are etched using the photoresist pattern as an
etch mask thereby forming the first trench 17 exposing a surface of
the contact plug 14. Thereafter, the photoresist pattern is removed
using oxygen plasma.
[0023] A conductive material is formed to fill the first trench 17.
Thereafter, the conductive material is planarized using the second
insulating layer as a target, thereby forming a first metal
interconnection 18. Herein, the first metal interconnection 18 is
formed as a copper interconnection, and a copper diffusion barrier
layer may be additionally formed before forming the copper
interconnection.
[0024] Referring to FIG. 1C, a second diffusion barrier layer 19 is
formed on the second ILD layer 16 including the first metal
interconnection 18. The second diffusion barrier layer 19 may be
formed of the same material as the first diffusion barrier layer,
e.g., SiC or SiN.
[0025] A third ILD layer 20 is formed on the second diffusion
barrier layer 19. The third ILD layer 20 is also formed of the FSG
containing nitrogen like the second ILD layer 16. To this end, the
process of forming the third ILD layer 20 is performed by mixing
N.sub.2, SiH.sub.4, N.sub.2O and SiF.sub.4. pecifically, this
process may be performed under a pressure ranging from
approximately 0.1 Torr to approximately 10 Torr at a flow rate of
N.sub.2 ranging from approximately 300 sccm to approximately 3,000
sccm, a flow rate of N.sub.2O ranging from approximately 400 sccm
to approximately 2,000 sccm, a flow rate of SiH.sub.4 ranging from
approximately 100 sccm to approximately 800 sccm, and a flow rate
of SiF.sub.4 ranging from approximately 300 sccm to approximately
1,000 sccm.
[0026] Referring to FIG. 1D, the third ILD layer is patterned using
a dual damascene process to form a second trench 21. A conductive
material is formed to fill the second trench. The conductive
material is planarized using the third ILD layer as a target to
thereby form a via and a second metal interconnection 22. The
second metal interconnection is formed as a copper interconnection,
and a copper diffusion barrier layer may be additionally formed
before forming the cooper interconnection.
[0027] In accordance with the present invention, the diffusion
barrier layer is formed of SiC or SiN after forming the contact
plug, and thereafter the annealing process is performed. Thus, it
is possible to secure thermal stability of a metal interconnection
and also improve dark current characteristic by forming the FSG
layer containing nitrogen. This makes it possible to improve
reliability of the metal interconnection and device
reliability.
[0028] While the present invention has been described with respect
to the specific embodiments, it will be apparent to those skilled
in the art that various changes and modifications may be made
without departing from the spirit and scope of the invention as
defined in the following claims.
* * * * *