U.S. patent application number 12/639886 was filed with the patent office on 2010-05-27 for miniature circuitry and inductive components and methods for manufacturing same.
This patent application is currently assigned to Multi-Fineline Electronix, Inc.. Invention is credited to Joe D. Guerra, Ciprian Marcoci, Ronald W. Whittaker.
Application Number | 20100127814 12/639886 |
Document ID | / |
Family ID | 46124165 |
Filed Date | 2010-05-27 |
United States Patent
Application |
20100127814 |
Kind Code |
A1 |
Whittaker; Ronald W. ; et
al. |
May 27, 2010 |
MINIATURE CIRCUITRY AND INDUCTIVE COMPONENTS AND METHODS FOR
MANUFACTURING SAME
Abstract
Miniature circuitry and inductor components in which multiple
levels of printed circuitry are formed on each side of a support
panel, typically a printed circuit board or rigid flex. Magnetic
members are embedded in one or more cavities in said support panel.
Electrical connection between the plural levels of circuitry and
multiple windings around the magnetic members are provided by
plural plated through hole conductors. Small through hole openings
accommodate a plurality of the plated through hole conductors since
each is insulated from the others by a very thin layer of vacuum
deposited organic layer such as parylene having a high dielectric
strength. Adhesion of this plated copper to the organic layer is
provided by first applying an adhesive promotor to the surface of
the organic layer followed by the vacuum deposition of the organic
layer.
Inventors: |
Whittaker; Ronald W.;
(Ninichilk, AK) ; Guerra; Joe D.; (Lake Forest,
CA) ; Marcoci; Ciprian; (Anaheim, CA) |
Correspondence
Address: |
KNOBBE MARTENS OLSON & BEAR LLP
2040 MAIN STREET, FOURTEENTH FLOOR
IRVINE
CA
92614
US
|
Assignee: |
Multi-Fineline Electronix,
Inc.
Anaheim
CA
|
Family ID: |
46124165 |
Appl. No.: |
12/639886 |
Filed: |
December 16, 2009 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
12233553 |
Sep 18, 2008 |
7656263 |
|
|
12639886 |
|
|
|
|
11774180 |
Jul 6, 2007 |
7436282 |
|
|
12233553 |
|
|
|
|
11296579 |
Dec 7, 2005 |
7271697 |
|
|
11774180 |
|
|
|
|
60633742 |
Dec 7, 2004 |
|
|
|
Current U.S.
Class: |
336/229 |
Current CPC
Class: |
H05K 2201/086 20130101;
H05K 2201/10416 20130101; H01F 19/04 20130101; H05K 3/389 20130101;
H05K 3/4644 20130101; H01F 27/266 20130101; H01F 17/0033 20130101;
H01F 27/2804 20130101; H01F 41/046 20130101; H05K 1/165 20130101;
H01F 2017/002 20130101; H05K 1/189 20130101; H05K 2201/097
20130101; H05K 2201/0179 20130101; H05K 3/429 20130101; H01F 17/062
20130101; H05K 2201/09809 20130101 |
Class at
Publication: |
336/229 |
International
Class: |
H01F 27/28 20060101
H01F027/28 |
Claims
1. A miniature magnetic device having a base member, a cavity
formed in said base, a magnetic member located in said cavity, said
member providing a magnetic core of said magnetic device, a
plurality of openings in said base, a plurality of plated through
hole conductors formed in said through hole openings, each of said
conductors being respectively electrically insulated from another
plated through hole conductor in the same hole by a thin vacuum
deposited polymer film, said plated through hole conductors
providing windings of said magnetic device, wherein said magnetic
member has a substantially E-shaped configuration.
2. A miniature magnetic device having a base member, a cavity
formed in said base, a magnetic member located in said cavity, said
member providing a magnetic core of said magnetic device, a
plurality of openings in said base, a plurality of plated through
hole conductors formed in said through hole openings, each of said
conductors being respectively electrically insulated from another
plated through hole conductor in the same hole by a thin vacuum
deposited polymer film, said plated through hole conductors
providing windings of said magnetic device, wherein said magnetic
member has substantially the shape of an oblong toroid.
3. A miniature magnetic device having a base member, a cavity
formed in said base, a magnetic member located in said cavity, said
member providing a magnetic core of said magnetic device, a
plurality of openings in said base, a plurality of plated through
hole conductors formed in said through hole openings, each of said
conductors being respectively electrically insulated from another
plated through hole conductor in the same hole by a thin vacuum
deposited polymer film, said plated through hole conductors
providing windings of said magnetic device, wherein said magnetic
member has an asymmetric configuration.
Description
REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser.
No. 12/233,553 filed Sep. 18, 2008 which is a divisional of U.S.
application Ser. No. 11/774,180 filed Jul. 6, 2007 which is a
continuation-in-part of U.S. application Ser. No. 11/296,579 filed
Dec. 7, 2005 which claims priority from U.S. Provisional
Application No. 60/633,742 filed Dec. 7, 2004, the entirety of each
of which is hereby incorporated by reference.
FIELD OF THE INVENTION
[0002] The present invention relates to improvements in miniature
electrical circuits and inductors and transformers and methods of
manufacturing these devices.
SUMMARY OF THE INVENTION
[0003] One aspect of the invention is a high yield process for
manufacturing improved miniature circuits which include an embedded
magnetic device such as an inductor or transformer having high
functional reliability. In particular, the process fabricates two
or more independent and isolated conductors in the same via holes.
Aspects of this embodiment include closely spacing while
maintaining a high voltage barrier between the conductors and
providing interconnect reliability.
[0004] For inductive embodiments, the two or more independent
conductors are advantageously fabricated on the wall of a hole
either in or proximate to a magnetic material embedded in a cavity
in a printed circuit board or flexible circuit. Embodiments include
holes located in a magnetic material and holes located around a
magnetic member. These conductors function as windings of an
inductor or transformer.
[0005] In another embodiment, the two or more independent
conductors are formed on the wall of vias in circuit board or
flexible circuits to interconnect circuits and circuit elements
located on opposite sides of the printed circuit board or flexible
circuit.
[0006] Extremely miniature devices are constructed by providing an
extremely thin but very high dielectric film between plural plated
through hole conductors in each via. In addition, further
miniaturization is provided by utilizing printed circuits over the
entire surface of the support panel and locating surface mounted
components over the magnetic members embedded within the support
panel.
[0007] The miniaturization achieved by the circuits and processes
enable, for example, very small and lightweight power supplies for
laptop computers, digital cameras, portable audio and T.V. devices,
and cell phones.
[0008] The improved inductor and circuit configurations enable
efficient and repeatable manufacture of miniature circuits and
miniature magnetic devices having high voltage, high current
capabilities, as well as high tolerance to physical stress.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 is a perspective view illustrating a support panel
with a plurality of toroidal cavity openings routed therein;
[0010] FIG. 2A is a perspective view illustrating magnetic members
in each of the routed cavity openings in the support plate;
[0011] FIG. 2B is a cross-sectional view along lines 2B-2B of FIG.
2A;
[0012] FIG. 3 is a cross-sectional view of the support panel having
copper layers on opposite sides;
[0013] FIG. 4 illustrates a cavity and the removal of the top
copper layer from the support panel;
[0014] FIG. 5 is a cross-sectional view illustrating the lay-up
prepreg rings and prepreg copper foil lamination;
[0015] FIG. 6 is a perspective view of the magnetic member;
[0016] FIG. 7 is a cross-sectional view showing the assembly prior
to the lamination of the copper foil;
[0017] FIG. 8 is a cross-sectional view showing the assembly after
lamination of the copper foil;
[0018] FIG. 9 is a top elevational view showing the through via
holes formed around the outer and inner walls of the magnetic
member;
[0019] FIG. 10 is a cross-sectional view of the via holes;
[0020] FIG. 11 is a cross-sectional view illustrating copper
plating of the assembly;
[0021] FIG. 12A is a top elevational view showing the first layer
of printed circuit conductors;
[0022] FIG. 12B is a bottom elevation view showing the second layer
printed circuit conductors;
[0023] FIG. 13 is a cross-sectional view showing application of the
first insulating layer over the first and second layers of printed
circuit and over the first plated through hole;
[0024] FIG. 14 is a cross-sectional view showing the application of
the second insulating layer;
[0025] FIG. 15 is a cross-sectional view showing the application of
the third insulation layer and adhesion promotor;
[0026] FIG. 16 is a cross-sectional view illustrating the lay-up of
predrilled bond ply and copper foils;
[0027] FIG. 17 is a cross-sectional view showing the assembly after
lamination of the copper foils;
[0028] FIG. 18 is a cross-sectional view showing the magnetic
devices via holes etched from the copper foils;
[0029] FIG. 19 is a cross-sectional view showing the copper plating
over the assembly;
[0030] FIG. 20 is a cross-sectional view illustrating the lay-up
prepreg and copper foil before lamination;
[0031] FIG. 21 is a cross-sectional view illustrating the laminated
assembly;
[0032] FIG. 22 is a cross-sectional view illustrating the
application of a cover layer or solder mask to the assembly;
[0033] FIG. 23 is a perspective view of a power supply in which the
magnetic devices are embedded in the printed circuit panel;
[0034] FIG. 24 is a perspective view of another embodiment having a
support panel having a plurality of rectangular openings;
[0035] FIG. 25 is a perspective view illustrating a support panel
having rectangular ferrite plates in each of the openings;
[0036] FIG. 26 is a cross-sectional view of an embodiment utilizing
rectangular ferrite plates;
[0037] FIG. 27 is an elevation view of a subassembly illustrating
the transparency of the parylene insulating layer;
[0038] FIG. 28 is a photomicrographic view of an exemplary
cross-section showing two parylene insulated conductive vias in a
single via hole as formed by this invention;
[0039] FIG. 29 is a photomicrographic view of an exemplary
cross-section showing three parylene insulated conductive vias in a
single via hole as formed by this invention; and
[0040] FIG. 30 is a photomicrographic view of an exemplary
cross-section showing four insulated conductor vias in a single via
hole as formed by this invention.
[0041] FIG. 31A is an elevational view of the first or top printed
circuit level of another embodiment having two toroids embedded
into the support panel;
[0042] FIG. 31B is an elevational view of the second or bottom
printed circuit level of the embodiment of FIG. 31A;
[0043] FIG. 32A is an elevational view of the third printed circuit
level, of the embodiment of FIG. 31A, formed in a plane proximate
to and over the plane of the first printed circuit layer;
[0044] FIG. 32B is the elevational view of fourth printed circuit
level formed in a plane proximate to and over the plane of the
second printed circuit level of FIG. 31B;
[0045] FIG. 33A is an elevational view of the fifth printed circuit
level of the embodiment of FIG. 31A, formed in a plane proximate to
and over the plane of the third printed circuit level of FIG.
32A;
[0046] FIG. 33B is an elevational view of the sixth printed circuit
level of the embodiment of FIG. 31A proximate to and over the plane
of the fourth printed circuit level of FIG. 32B;
[0047] FIGS. 34A and 34B are perspective views of the top and
bottom of a power supply constructed utilizing the printed circuit
level shown in FIGS. 31A, 31B, 32A, 32B, and 33A, 33b;
[0048] FIG. 35 is a cross-sectional view illustrating the use of
the plated through holes for both forming winding turns for
conductors and transformers and for providing electrical
connections between other printed circuitry layers.
[0049] FIG. 36 is a perspective view of an oblong toroid shaped
magnetic member.
[0050] FIG. 37 is a perspective view of a magnetic member having a
non-systematic shape.
[0051] FIGS. 38A and 38B are perspective views of an E shaped
magnetic member.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0052] The process for manufacturing one embodiment of inductive
component devices is illustrated in FIGS. 1-22. As shown in FIG. 1,
a plurality of toroidal openings or cavities 50 are formed,
typically by routing, in a support panel 52. Panel 52 is
advantageously an FR-4 epoxy laminate sheet 54 with copper layers
56, 58 on opposite sides, as shown in FIG. 3, although it will be
apparent that sheets made from other materials including other
types of sheets used for circuit board fabrication and rigid flex
are applicable for use as support panel 52. Using standard
techniques of printed circuitry, the top copper layer 56 is then
eliminated using the dry film to mask the bottom surface of the
support panel. The exposed (unmasked) copper layer 56 is then
etched off from the top surfaces of the panel. The remaining dry
film mask is then stripped from the bottom surface to provide a
support panel having the cross-section shown in FIG. 4.
[0053] FIGS. 1 and 2A illustrate a support panel 52 on which four
cavities are formed to simultaneously manufacture four magnetic
device components after which the support board is cut or mounted
to produce a plurality of individual components such as illustrated
in FIGS. 23, 34A, and 34B. It will be understood that the processes
described below are usually used to simultaneously manufacture a
larger number of components, typically in the range of 16 to 20
components. Also, each component may include a single cavity
embedding a single magnetic member or may include two or more such
cavities and magnetic members to produce two or more embedded
inductive devices for a particular electronic device. See, e.g.,
the embodiment described below and shown in FIGS. 34A and 34B.
[0054] Following the cavity preparation, in one embodiment, one or
more prepreg toroidal rings 60 are seated onto the bottom of each
of the formed toroidal openings 50 as shown in FIG. 5.
[0055] In one embodiment, the magnetic members are shaped as
ferrite toroids 62 (shown in FIG. 6) conforming in shape to the
toroidal openings 50. As described below, the openings or cavities
and the magnetic members can have a plurality of different shapes
for manufacturing devices including inductors and transformers. By
way of specific example, the toroid 62 may have an outside diameter
of 1.25 inches and an opening of 3/8 inches. A copper foil 70, is
then laminated to the top surfaces of the ferrite toroid 62 using
an epoxy prepreg 72 or other suitable adhesive to affix the foil to
the ferrite plate. Depending upon the ultimate application of the
inductive component, the copper foil will typically also cover all
or part of the support panel 52.
[0056] The ferrite toroids 62 are respectively embedded within the
toroidal openings over the prepreg rings 60, as shown in FIGS. 2A
and 5. Each of these ferrite toroids 62 can serve as a
ferromagnetic slab for a fabricated induction component.
[0057] As illustrated in FIG. 7B, panel 52 and assembled ferrite
toroids, prepreg and copper foil are then placed in a holding
fixture of a laminating machine (not shown) that applies pressure
and heat resulting in the top surfaces of the ferrite cores 62
being made substantially flush with the top surfaces of board 52
and prepreg material filling the voids between the walls of
openings 50 and ferrite cores as well as laminating the copper foil
70 over the cores 62 and support panel 52 as shown in FIG. 8. The
resultant flat surface over the embedded toroid ferrite permits
multiple additional circuit layers and mounting of circuit elements
over the entire support panel 56. As described below, extremely
small components such as switching power supplies and battery
chargers for laptops, computers, digital cameras, cell phones,
portable audio and TV's and the like can be constructed.
[0058] In this lamination step and the lamination steps described
below, the materials used are selected to provide the desired
physical properties for the finished circuitry. These properties
are commonly referred to as peel strengths and bond strengths. The
preferred materials for laminating are: Medium or High Tg epoxy
prepregs from LG, Isola, Polyclad or Arisawa.
[0059] Through holes (vias) 80 and 81 are then respectively drilled
through the laminated subassembly panel 85 around the outside and
inside of the magnetic member using conventional drilling
equipment. These via holes are typically 12 to 50 mils in diameter.
As described below, these through holes or vias 80 and 81 (shown in
FIGS. 9 and 10) enable fabrication of plated through hole
conductors which function as electrical windings for the magnetic
device.
[0060] After drilling, the laminated panel 85 is advantageously
plasma etched to clean the drilled holes. This step is
advantageously followed by a glass etch to remove spurious glass
particles from the holes 80, 81 or roughen the glass fibre for
adhesion of the copper plating followed by chemically cleaning the
vias 80, 81 and the top and bottom surfaces of the exposed copper
sheets 58 and 70.
[0061] A conventional process is then used to chemically coat the
inside surface of all of the through holes 80, 81. In one
embodiment, the SHADOW process is utilized. Other processes include
an electroles copper deposition and DMSE/HDI process. An article
describing the process entitled "The Reliability of PTH Printed
Wiring Boards Manufactured With a Graphite-Based Direct
Metallization Process" is included with this application as
Appendix A.
[0062] Following this application of the chemical coating, the
subassembly 85 is copper plated. The plated copper 90 is shown in
FIG. 11 and covers both the copper foil laminate 58, the copper
foil laminate 70 and the internal walls of the through holes (vias)
80, 81 (shown at 95) so as to electrically connect the top and
bottom copper foils 58, 70 via the plated through holes 95.
[0063] Printed circuits 100, 101 (shown in FIGS. 12A and 12B) are
then fabricated using the top and bottom layers of the copper
laminate 58, 70 and plated copper 90. These circuits 100, 101 are
advantageously formed by vacuum laminating a dry photographically
developable film over the surfaces of the plated copper on the top
and bottom of the subassembly. Using standard, well known
techniques of printed circuitry, first layer 100 and second layer
101 of circuitry are fabricated by using the dry film to mask the
desired circuitry. The exposed, i.e., unmasked copper is then
etched from both top and bottom surfaces of the component assembly.
The remaining dry film mask is then stripped from those top and
bottom surfaces. The remaining copper forms a first layer of
circuitry 100 on the top surface (shown in FIG. 12A), and a second
layer of circuitry 101 (shown in FIG. 12B) on the bottom surface,
interconnected by the copper plated via holes 95. As described
below, these formed printed circuits respectively include circuits
100, 101 which are respectively connected at each end to a plated
through hole 80, 81 to provide a continuous, electrical winding
around the ferrite core encased in the support member. These
windings and magnetic core form a miniature magnetic device.
[0064] The top and bottom surfaces are then chemically cleaned. The
component assembly is then vacuum baked to remove any remaining
moisture.
[0065] The component assembly is then prepared for an additional
copper layer and an additional plated via insulated from but
fabricated over the first copper layers. An insulating coating is
used to separate the multiple layers of circuitry and plated vias.
Epoxy, polymer, liquid polyamide and other materials may be used.
However, parylene coating has been discovered to be particularly
advantageous for forming these insulating layers. Parylene is an
organic coating with an inert surface. In one embodiment, in
preparation for the parylene coating, an adhesive promotor such as
a very thin Silane, Carboxyl or Silane and Carboxyl layer 110
(shown in FIG. 13) is deposited on the subassembly including the
top and bottom surfaces and walls of the plated through holes using
a PECVD process (Plasma Enhanced Chemical Vapor Deposition) or
other suitable process. In another embodiment, this very thin layer
110 may be formed by dipping the subassembly in a Silane or other
adhesive before deposition of the parylene.
[0066] The parylene is then vacuum deposited over the entire
subassembly to leave, as illustrated in FIG. 14, a thin coating 115
over the first (top) layer of circuitry 100, a thin coating 116
over the second (bottom) layer of circuitry 101 and a thin coating
117 over (inside) the copper plated through hole 95.
[0067] The parylene coating process is further described in the
publication entitled "Parylene Conformal Coatings Specifications
and Properties," published by Specialty Coating Systems,
Indianapolis, Ind. and attached as Appendix B to this application.
This parylene coating is pinhole free and has a high dielectric
strength with very thin coatings providing very high voltage
breakdown values. By way of specific example, parylene coatings
formed of Parylene C with thicknesses of 0.0005 mil to 0.001 mil
provide a voltage breakdown guard band of about 5600 volts per mil
of thickness. Parylene C has a dielectric constant of about
2.28.
[0068] Nova HT Parylene described in Appendix C to this application
provides an even higher dielectric constant of about 3.15 and
provides a voltage breakdown of about 5600 volts per 0.001 mil of
thickness.
[0069] A parylene coated subassembly is shown in FIG. 27. This and
other parylene coatings shown in other photographs were coated at
the SCS Coating Center at Ontario, Calif., as described in Appendix
D to this application.
[0070] The thickness of the deposited parylene layers 115, 116 and
117 is determined by several factors including physical size of the
manufactured magnetic device or physical size of the through hole
openings 80, 81, the number of insulated plated through hole
conductors to be formed in a through hole, and the power rating of
the manufactured product. For the magnetic device described below,
the thickness of the parylene layer will be in the range of about
0.5 mil to 3 mils. (0.0005 to 0.003 inches), and the breakdown
guard band will be in the range of about 5600 to 15,000 volts per
mil of thickness of the parylene layers.
[0071] The extremely thin parylene provides a high dielectric
coating between the copper plated through holes and enables plural
such through hole conductors to be formed in a very small through
hole opening. A further aspect of the these coatings that enables
multiple conductors through a single very small via is that the
vacuum deposited parylene provides a substantially uniform
thickness coating that closely follows the contour of the
underlying copper plate. As a result, the parylene does not, of
itself, cause an unpredictable build up of thickness in the plated
through hole. The diameter of the through holes will typically be
determined by the thickness of the support panel 56 and the number
of plated, through holes to be formed in each through hole. The
panel thickness is typically in the range of about 62 mil to 15
mil. Typically the hole size will range from about 12 mil to 50
mil. For a panel 90 mil thick, a hole size of about 22 mil diameter
will typically be used to form two plated through holes within this
through hole and a hole size of about 40 mil diameter will be
selected to form four plated through holes. For a thicker panel
0.125 mil thick, a hole size of about 28 mil would typically be
used to form two plated through holes and a hole size of about 40
to 60 mil will typically be used to form four plated through
holes.
[0072] While having excellent dielectric insulative properties, the
surface of the deposited parylene will not bond or adhere to plated
copper. It has been discovered, however, that a suitable adhesive
promoter is accomplished by adding a positively charged moiety to
the backbone of the parylene compound. This is advantageously
accomplished by using the plasma enhanced chemical vapor deposition
(PECVD) process. In one embodiment, the process is a Carboxl or
Silane gas phase chemical reactions at low pressures (10 to 500
mT), voltages typically in the range of about 200 to 700 volts,
currents typically in the range of about 3 to 7 amp and power in
the range of about 6V to 2000 watts. The resulting surface
(indicated at 120 in FIG. 15) populated with reactive sites, ready
to receive an adhesive or coating. The mechanism is believed to be
primarily due to hydrogen bonding and covalent bonding due to this
adhesive or coating reacting to the changed moiety.
[0073] Formation of third and fourth layers of circuitry begins
with drilling hole openings 122, 123 in adhesive sheets 125, 126
before these sheets are positioned onto the assembly. These
openings 122, 123 are drilled to register over the first and second
layer circuitry openings 80, 81. As shown in FIG. 16, the
pre-drilled adhesive sheets 125 and 126 are then respectively
positioned over the top and bottom surfaces of the subassembly. A
low temperature lamination process is then used to partially
laminate the pre-drilled adhesive sheet 125, to the surface of the
parylene coated top surface of this top circuitry layer 100 and
adhesive sheet 126 to the surface of the parylene coated bottom
circuitry layer 101, as shown in FIG. 12B. Copper foil 130, is then
attached to the top side of the adhesive coated panel and copper
foil 131 is attached to the bottom side of the adhesive coated
panel.
[0074] Copper foils 130, 131 are then laminated to the subassembly
at high temperature and pressure to form a four copper layer
assembly shown in FIG. 17 with the third layer 130 and the fourth
layer 131, respectively, insulated from the circuitry layers 100,
101 by the insulating layers 110, 115, 116, 120.
[0075] Using the well known techniques of printed circuitry, via
holes 135, 136, 137, and 138 (shown in FIG. 18) are formed in the
copper foils 130, 131 by using the dry film to mask the copper. The
unmasked copper is then etched from both top and bottom surfaces of
the component assembly to form these vias 135-138. The remaining
dry film mask is then stripped from those top and bottom
surfaces.
[0076] The surfaces of copper foils 130, 131 are now chemically
coated using the SHADOW process. Following the application of a
chemical coating using the SHADOW process, the subassembly is again
copper plated. The plated copper 145 is shown in FIG. 19 and covers
both the copper foil laminate 130, copper foil laminate 131 and the
parylene coated walls of the plated through holes 95 so as to form
second conductive through holes 140 in the same through hole and
thereby electrically connect the third and fourth copper plated
foils 130, 131.
[0077] Third and fourth printed circuits 150, 151 are then
fabricated using the top and bottom layers of plated copper foils
130, 131. These circuits are advantageously formed by vacuum
laminating a dry photographically developable film over the top and
bottom surfaces of the plated copper. Using standard well known
techniques of printed circuitry, these third and fourth layers of
circuitry are fabricated by using the dry film to mask the desired
circuitry. The exposed (unmasked) copper is then etched from both
top and bottom surfaces of the component assembly. The remaining
dry film mask is then stripped from those top and bottom surfaces.
The remaining copper forms the desired third layer of circuitry 150
on the top surface, the fourth layer of circuitry 151 on the bottom
surface, and the circuitry connections between layers 150, 151
provided by the copper plated via holes 140.
[0078] The top and bottom surfaces are then chemically cleaned. The
component assembly is then vacuum baked to remove any remaining
surface chemicals.
[0079] Additional fifth and sixth layers of circuitry 160, 161 are
fabricated over the third and fourth layers. In the embodiment
shown in FIG. 20, these circuit layers are insulated from the
adjacent third and fourth layers by two layers of prepreg 165. By
way of example, the Isola medium Tg epoxy prepreg has a voltage
breakdown rating of 1100 to 1200 volts per mil thickness. By way of
specific example, a 4 mil thickness of this prepreg was used to
provide a voltage breakdown of over 4000 volts. These fifth and
sixth circuit layers are formed following the cleaning and baking
steps as follows: [0080] 1) Drill the fifth layer 160 and sixth
layer 161 copper foils with tooling holes [0081] 2) Drill tooling
holes in two sheets of adhesive, or prepreg [0082] 3) Lay up two
additional adhesive coated copper foils 160, 161, or copper foil
and prepreg on to the assembly shown in FIG. 19 containing four
layers of circuits [0083] 4) Laminate all the material together at
high temperature and pressure using a vacuum lamination process so
the result at this stage of manufacture is an assembly shown in
FIG. 21 having six copper foil layers 58, 70, 130, 131, 160 and 161
with circuit layers 58 and 70 interconnected via the plated holes
95 and circuit layers 130 and 131 interconnected by plated holes
140 which are isolated from the plated holes 95 but using the same
via holes [0084] 5) As shown in FIG. 35, additional through holes
153 may now be selectively drilled through the respective plated
copper sheets and support panel 56 to enable, for example, through
hole connectors for surface mounted circuit elements, e.g.,
semiconductors, capacitors, resistors located over the cavity 50
and embedded toroid 62 as shown in FIGS. 34A and 34B. [0085] 6)
Plasma etch [0086] 7) Glass etch [0087] 8) Chemical clean the
surfaces of layers 160 and 161 [0088] 9) Shadow Process the
surfaces of the interconnecting holes [0089] 10) Copper plate the
surfaces and the holes [0090] 11) Chemical clean [0091] 12) Vacuum
laminate dry film [0092] 13) Expose the fifth and sixth circuit
layers 160, 161 for etching [0093] 14) Etch the fifth and sixth
circuitry layers 160, 161 to form printed circuits from the plated
foils 160, 161 [0094] 15) Strip dry film from surface of the fifth
and sixth layers of printed circuitry [0095] 16) Chemical Clean
[0096] 17) Vacuum bake [0097] 18) Laminate two covercoats or apply
cover layers or solder masks 170, 171 over the fifth and sixth
printed circuit layers (as shown in FIG. 22) while including
appropriate openings to accommodate components to be assembled
there-on [0098] 19) Bright tin/lead plate or apply protective
coating onto the exposed copper circuitry underneath the covercoat
openings [0099] 20) Separate each individual assembly by routing or
cutting apart the individual rectangular circuits each containing
an embedded individual magnetic device and six circuitry layers
[0100] 21) Test [0101] 22) Assemble electrical circuit elements
onto the individual miniature inductor or transformer components as
shown in FIGS. 23 and 34A, 34B [0102] 23) Test the final
assembly
[0103] The assembly described above and shown in FIG. 23 has six
layers of printed circuitry and two plated through holes 95 and 120
through each hole (via) 80, 81 formed in the support panel 56
around the outside and inside of the embedded magnetic member. In
the assembly shown, the first, second, third and fourth printed
circuitry layers and plated through holes 95 and 120 form circuitry
and the windings of the magnetic device
[0104] By way of specific example, FIG. 23 illustrates an
embodiment of a miniature power supply 195 constructed in
accordance with this invention. As shown, the magnetic components
of the power supply are entirely encapsulated within the printed
circuit board. By way of specific example, the support panel for
this embodiment has a length of 2 3/16 inches and a width of 1
13/16 inches.
[0105] In the foregoing embodiment, ferrite toroids are used to
form inductors and transformers in the plane of the circuit board
or flexible circuit. It will be understood that many other
configurations of easily magnetized material may be utilized.
Examples include, but are not limited to ferrites such as
polycrystalline ceramic soft ferrites and various metal alloys
having magnetic properties including, but not limited to,
crystalline nickel-iron amorphous cobalt based alloys such as the
VITROVAC.RTM. manufactured and sold by VACUUMSCHMELZE Gimbh &
Co., Hanau, Germany. Various geometric configurations may be
utilized, including toroids 62 shown in FIG. 6, the rectangular
plates 210, shown in FIG. 25, thin VITROVAC foils and tapes, an
oblong toroid 400 shown in FIG. 36 and e-core configurations 405
and 410 shown in FIGS. 38A and 38B. Numerous other shapes can be
utilized, e.g., an asymmetric toroid shape 415 shown in FIG. 37 to
fit inside the case or housing of a miniature cell phone or other
hand held device.
[0106] The through hole conductors can also be formed by processes
other than the above described copper plating, utilizing, for
example, conductive pastes. In addition, the plural plated through
holes insulated from each other may be formed directly through the
magnetic material. Construction of such another embodiment of the
invention is shown in FIGS. 24-26. In this embodiment, the
manufacture of a multiple through hole assembly utilizes a slab of
ferrite material and vias drilled are formed through the ferrite
slab. Plural conductive through holes are formed in each via.
[0107] As shown in FIG. 24, a plurality of rectangular openings 200
are formed typically by routing, in a support panel 205. Panel 205
is advantageously an FR-4 epoxy laminate sheet although it will be
apparent that sheets made from other materials including other
types of sheets used for circuit board fabrication are applicable
for use as support panel 205. In this embodiment, the openings are
formed completely through the support panel.
[0108] Ferrite plates 210 are respectively embedded within the
openings 200, as shown in FIG. 25. Each of these ferrite plates 210
serve as a ferromagnetic slab on which is fabricated inductive
components. As described below, these plates 210 may be formed as
shown in FIG. 25 without through holes which are subsequently
drilled during construction of the component. In other embodiments
a plurality of through holes, as seen in FIG. 27, may be pre-formed
during molding of ferrite slabs.
[0109] The ferrite plate 210 is shown in cross-section in FIG. 26.
This figure shows the surface of the ferrite plate 210 including
the walls of its through hole openings 215 covered with an
insulating layer 220. Advantageously, this layer is formed by a
vacuum deposited parylene coating as described in detail above.
Layer 220 insulates the ferrite material from the copper circuitry
to be fabricated over the ferrite surface and on the walls of the
through holes in the ferrites. This coating is advisable or
necessary for low resistivity ferrites, e.g., high permeability
ferrites of the order of 2300 PERM. Coating 220 will often not be
utilized for lower permeability ferrites, such as 350 PERM ferrites
having a higher resistivity.
[0110] Copper foils 225, 226 are then respectively laminated to the
top and bottom surfaces of the ferrite plate 210 using an epoxy
prepreg 230 or other suitable adhesive to affix the foil to the
ferrite plate. Depending upon the ultimate application of the
inductive component, the copper foil will typically also cover all
or part of the support panel 205. In this lamination step and the
lamination steps described below, the materials used are selected
to provide the desired physical properties for the finished
circuitry. These properties are commonly referred to as peel
strengths and bond strengths. The preferred materials for
laminating are: Crystal, B-1000, R1500 from Rogers Corp., Pyralux
FB from Dupont, Calif. 338, CA 333, E33 from Shin-Etsu, AY50KA,
CY2535KA, CVK2,530130, SAU, SPC, SPA from Arisawa, and Medium or
High Tg epoxy prepregs from Isola.
[0111] Through holes or vias 215 in the ferrite plates 210 (shown
in FIGS. 26 and 27) enable fabrication of plated through
conductors. These plated through vias function as electrical
windings for the inductor or transformer device. These holes are
typically 12 to 50 mil in diameter but can be larger or smaller,
(e.g., as small as 4 mil in diameter) depending upon the
specifications of the inductor or transformer being manufactured.
In some embodiments, the ferrite plates are molded or otherwise
pre-formed with the desired through holes 215. In such embodiments,
through holes using conventional drilling equipment are drilled
through the copper foil after the foil is laminated to the ferrite
plate 210. These holes are drilled so as to register with the
preformed holes in the ferrite plates. In other embodiments, such
as the ferrite plates 210 shown as FIG. 215, the ferrite plates are
not pre-formed with holes. In these embodiments, the holes are
formed in the ferrite plates 210 after lamination of the copper
foils 225, 226. Drilling holes through the ferrite plates and
copper foil is advantageously performed using laser drilling
equipment.
[0112] After drilling, the laminated panels are advantageously
plasma etched to clean the drilled holes. This step is
advantageously followed by a glass etch to remove spurious glass
particles from the holes 215 followed by chemically cleaning the
top and bottom surfaces of the exposed copper.
[0113] A conventional process is then used to chemically coat
(shown at 245) the top and bottom surfaces of the copper foil in
preparation of copper plating these top and bottom surfaces as well
as the inside surface of all of the through holes 215. This process
is commonly referred to as the SHADOW process. An article
describing the process entitled "The Reliability of PTH Printed
Wiring Boards Manufactured With a Graphite-Based Direct
Metallization Process" is included with this application as
Appendix A.
[0114] Following the application of the chemical coating 245 using
the SHADOW process, the subassembly is copper plated. The plated
copper is shown in FIG. 26 and covers both the copper foil laminate
225, the copper foil laminate 226 and the internal walls of the
through holes (vias) 215 (shown at 230) so as to electrically
connect the top and bottom copper foils 225, 226 via the plated
through holes 230.
[0115] Printed circuits are then fabricated using the top and
bottom layers of copper laminate and plated copper. These circuits
are advantageously formed by vacuum laminating a dry
photographically developable film over the surfaces of the plated
copper on the top and bottom of the subassembly.
[0116] Using standard techniques of printed circuitry, first and
second layers of circuitry are fabricated by using the dry film to
mask the desired circuitry. The unmasked copper is then etched from
both top and bottom surfaces of the component assembly. The
remaining dry film mask is then stripped from those top and bottom
surfaces. The remaining copper forms a first layer of circuitry 250
on the top surface, as shown in FIG. 26, and a second layer of
circuitry 251 on the bottom surface, interconnected by the copper
plate via holes 230.
[0117] The top and bottom surfaces are then chemically cleaned. The
component assembly is then vacuum baked to remove any remaining
surface chemicals or moisture.
[0118] The component assembly is then prepared for an additional
copper layer and an additional plated via insulated from but
fabricated over the first copper layers. An insulating coating is
used to separate the multiple layers of circuitry and plated vias.
Epoxy, parylene, liquid polymide and other materials may be used.
However, as described above, parylene coating has been discovered
to be particularly advantageous for forming these insulating
layers. In this process, the parylene is vacuum deposited over the
entire subassembly to leave, as illustrated in FIG. 26, a thin
coating 270 over the top layer of circuitry 250, a thin coating 271
over the bottom layer of circuitry 251 and a thin coating 272
inside the copper plated through hole 230.
[0119] In preparation for parylene coating, a very thin Silane
and/or Carboxyl layer is deposited on the subassembly using a PECVD
process (Plasma Enhanced Chemical Vapor Deposition).
[0120] The parylene coating process is further described in the
publication entitled "Parylene Conformal Coatings Specifications
and Properties," published by Specialty Coating Systems,
Indianapolis, Ind. and attached as Appendix B to this application.
This parylene coating is pinhole free and has a high dielectric
strength with very thin coatings providing very high voltage
breakdown values. By way of specific example, parylene coatings
formed of Parylene C with thicknesses of 0.0005 mil to 0.001 mil
provide a voltage breakdown guard band of about 5600 volts per mil
of thickness. Parylene C has a dielectric constant of about
2.28.
[0121] Nova HT Parylene described in Appendix C to this application
provides an even higher dielectric constant of about 3.15 and
provides a voltage breakdown of about 750 volts per micron of
thickness. As a result, very thin coatings, e.g., 10 to 15 microns
provides a breakdown voltage barrier in the range of 7500 volts or
higher.
[0122] One embodiment of the parylene coated subassembly is shown
in FIG. 27. This and other parylene coatings shown in other
photographs were coated at the SCS Coating Center at Ontario,
Calif., as described in Appendix D to this application.
[0123] Following application of the parylene coating, this
subassembly is plasma burned in preparation for additional layers
of circuitry over in the top circuit layers and bottom layer 250,
251.
[0124] Formation of third and fourth layers of circuitry begins
with drilling hole openings in copper foil sheets 280, 281 that
will register over the circuitry openings shown in FIG. 26. Similar
openings registering with these through hole openings are drilled
in two sheets of adhesive 285, 286. A low temperature lamination
process is then used to partially laminate the pre-drilled copper
foils 80, 81 to the pre-drilled adhesives so that the respective
openings are aligned as shown in FIG. 26. The adhesive coated
copper foil 280 is then attached to the surface of the parylene
coated top surface of this first circuitry layer 250 and the
adhesive coated copper foil 281 is attached to the surface of the
parylene coated second circuitry layer 261.
[0125] Copper foils 280, 281 are then laminated to the subassembly
at high temperature and pressure to form a four copper layer
assembly with the third layer 280 and the fourth layer 281,
respectively, insulated from the circuitry layers 2 by the
respective parylene coating layers 270, 271.
[0126] The surfaces of copper foils 280, 281 are now chemically
coated using the SHADOW process. Following the application of a
chemical coating using the SHADOW process, the subassembly is again
copper plated. The plated copper is shown in FIG. 26 and covers
both the copper foil laminate 280 (as shown at 290), copper foil
laminate 281 (as shown at 291) and the parylene coated walls of the
plated through holes (vies) 230 (shown at 300) so as to
electrically connect the third and fourth copper plated foils 280,
281 via plated through holes 300.
[0127] Third and fourth printed circuits are then fabricated using
the top and bottom layers of plated copper foils 280, 281. These
circuits are advantageously formed by vacuum laminating a dry
photographically developable film over the top and bottom surfaces
280, 281 of the plated copper.
[0128] Using the well known conventional techniques of printed
circuitry, these third and fourth layers of circuitry are
fabricated by using the dry film to mask the desired circuitry. The
exposed, i.e., unmasked copper is then etched from both top and
bottom surfaces of the component assembly. The remaining dry film
mask is then stripped from those top and bottom surfaces. The
remaining copper forms the desired third layer of circuitry on the
top surface, the fourth layer of circuitry on the bottom surface,
and the circuitry connections between the third and fourth layers
connected to the copper plated via holes 300.
[0129] The top and bottom surfaces are then chemically cleaned. The
component assembly is then vacuum baked to remove any remaining
surface chemicals.
[0130] Additional through hole connection holes may now be
selectively drilled through the respective copper sheets and panel
205 to enable, for example, through hole connections for the
circuit elements located over the ferrite plate 210.
[0131] Additional fifth and sixth layers of circuitry 305, 306 are
fabricated over the third and fourth layers. In the embodiment
shown in FIG. 7, these circuit layers are insulated from the
adjacent third and fourth layers by a relatively thick single or
two or more layers of prepreg 310. By way of example, the Isola
medium Tg epoxy prepreg has a voltage breakdown rating of 1100 to
1200 volts per mil thickness. By way of specific example, a 4 mil
thickness of this prepreg was used to provide a voltage breakdown
of over 4000 volts. These fifth and sixth layers are formed
following the cleaning and baking steps as follows: [0132] 1) Drill
the fifth and sixth layer copper foils with tooling holes [0133] 2)
Drill tooling holes in two sheets of adhesive, or prepreg [0134] 3)
Kiss laminate predrilled two copper foils with predrilled adhesive
[0135] 4) Lay up adhesive coated copper foil and prepreg with
panels containing layers 1, 2, 3, and 4 [0136] 5) Laminate all the
material together at high temperature and pressure using ordinary
(vacuum) lamination process so the result is a six copper layer
assembly with layers 1 and 2 interconnected via the plated holes
and layers 3 and 4 interconnected but isolated from layers 1 and 2
using the same holes [0137] 6) Drill additional connection holes on
the six layer assembly [0138] 7) Plasma etch [0139] 8) Glass etch
[0140] 9) Chemical clean the surfaces of layers 5 and 6 [0141] 10)
Shadow Process the surfaces of layers 5 and 6 and the
interconnecting holes [0142] 11) Copper plate the surfaces and the
holes [0143] 12) Chemical clean [0144] 13) Vacuum laminate dry film
[0145] 14) Expose layers 5 and 6 circuitry for etching [0146] 15)
Etch layers 5 and 6 circuitry [0147] 16) Strip dry film from
surface of layers 5 and 6 [0148] 17) Chemical Clean [0149] 18)
Vacuum bake [0150] 19) Laminate two covercoats or (apply cover
layers-new) over layers 5 and 6 with appropriate openings to
accommodate components to be assembled there-on [0151] 20) Bright
tin/lead plate or (apply protective coating-new) onto the exposed
copper circuitry underneath the covercoat openings [0152] 21)
Separate each individual assembly by routing the individual
rectangular circuits each containing individual ferrite towards
with 6 circuit layers [0153] 22) Test [0154] 23) Assemble
components onto the individual rectangular circuits [0155] 24) Test
the final assembly
[0156] The assembly described above and shown in FIG. 26 has six
layers of circuitry and two plated through holes 230 and 300
through each hole (via) 215 formed in the ferrite plate 210. In the
assembly shown, the first, second, third and fourth circuit layers
225, 226, 280 and 281 and plated through holes advantageously form
the windings of a "virtual toroid" inductor or transformer
constructed in accordance with pending U.S. patent application
entitled Electronic Transformer Inductor Devices and Methods for
Making Same, Ser. No. 10/659,797, Publication No. 2004/0135662-A1,
a copy of which is attached as Appendix E.
[0157] The plated through holes and printed circuitry may also be
used to construct other embodiments of inductors and transformers.
Examples are Cell Core transformers also described in the pending
application, Appendix E.
[0158] The processes described above can be used to produce
multiple independent through holes in ferrite and other materials
such as printed circuit board and flex. Thus, additional layers of
copper foil and copper plate advantageously insulated by a parylene
coating allows additional independent plated conductors in a single
via.
[0159] In other embodiments, a third or fourth plated conductive
through hole each insulated by a layer of parylene, are constructed
in the manner described above to provide, for example, additional
turns around the ferrite core or additional through hole connectors
for circuitry on the support panel. FIGS. 29, 30, and 31 are
photomicrographic views of cross-sections of printed circuit board
in which plural plated through hole circuits are formed in vias of
the board. FIG. 29 illustrates two conductors constructed in a
single via as described above. FIG. 30 illustrates three plated
through hole conductors in a single via and FIG. 31 illustrates
four plated through hole conductors in a single via.
[0160] Another embodiment is shown in FIGS. 31A, 31B, 32A, 32B,
33A, 33B, 34A, 34B, and 35. In this embodiment, each electrical
component incorporates two inductors of different sizes embedded
into the support panel. The component shown is an extremely small
power supply constructed on a panel 250 which is only 2.000 inch
long by 1.500 inch wide. In this panel are formed two toroidal
cavities. Toroidal ferrites having different outside diameters are
situated in these cavities. Using the process described above and
illustrated in FIGS. 1-22, a first printed circuit is etched in the
top layer of the panel and a second printed circuit is etched in
the bottom layer of its panel. The first printed circuit layer
includes respective primary windings 255 and 260 shown in FIG. 31A.
The second printed circuit layer includes primary windings 265 and
270 shown in FIG. 31B. Also shown are the plated through holes 275,
276, 277, and 278, drilled outside and inside the respective
toroidal ferrites, and plated in the manner described above.
Printed circuits 255, 265 and plated through holes 275, 276 form
the windings of an inductor. Printed circuits 260, 270 and plated
through holes 277, 278 form the primary windings of a
transformer.
[0161] Following a parylene coating as described above, a third
printed circuit is formed in its top surface and a fourth printed
circuit is formed on its bottom surface of the sub-assembly as
shown in FIGS. 32A and 32B. In addition second plated through holes
295, 296, 297 and 298 are respectively formed in this same through
holes as plated through holes 275, 276, 277 and 278 but insulated
therefrom by the parylene coating. The third printed circuit layer
includes additional windings 300 and 305. The fourth printed
circuit layer includes additional windings 310, 315.
[0162] Printed circuits 300, 310 and plated through holes 295, 296
from another set of windings for the inductor. Printed circuits
305, 315 and plated through holes 297, 298 form the secondary
winding of the transformer. In this example show, the transformer
is a step-down transformer having 32 primary windings and 4
secondary windings to provide an 8 to 1 turns ratio
transformer.
[0163] A fifth printed circuit 325 is formed over the top surface
of the top subassembly the third printed circuit layer as shown in
FIG. 33A. A sixth printed circuit 330 is formed in the bottom
surface of the subassembly as shown in FIG. 33B. The circuitry
elements for completing the power supply are attached as the
respective surface of the subassembly. An aspect of the
construction shown that contributes to the miniaturization of the
electronic component is that the fifth and sixth printed circuitry
325, 330 and attached circuit elements can utilize the entire
surface of the support panel including the surface space over the
embedded ferrite toroids. As such, the resulting power supplies and
other components utilizing inductors and transformers can be
constructed considerably smaller than conventional surface mounted
transformers and inductors.
[0164] The above presents a description of the best mode
contemplated for the components and methods of manufacturing said
in such full, clear, concise and exact terms as to enable any
person skilled in the art to which it pertains to produce these
components and practice these methods. These components and methods
are, however, susceptible to modifications that are fully
equivalent to the embodiment discussed above. Consequently, these
components and methods are not limited to the particular embodiment
disclosed. On the contrary, these apparatuses and methods cover all
modifications coming within the spirit and scope of the present
invention.
* * * * *