U.S. patent application number 12/684257 was filed with the patent office on 2010-05-06 for cpu power delivery system.
Invention is credited to Nitin Borkar, Shekhar Y. Borkar, Vivek K. De, Donald S. Gardner, Peter Hazucha, Tanay Karnik, Siva G. Narendra, Gerhard Schrom, Howard A. Wilson.
Application Number | 20100115301 12/684257 |
Document ID | / |
Family ID | 35559487 |
Filed Date | 2010-05-06 |
United States Patent
Application |
20100115301 |
Kind Code |
A1 |
Narendra; Siva G. ; et
al. |
May 6, 2010 |
CPU POWER DELIVERY SYSTEM
Abstract
A central processing unit (CPU) is disclosed. The CPU includes a
CPU die; and a voltage regulator die bonded to the CPU die in a
three dimensional packaging layout.
Inventors: |
Narendra; Siva G.;
(Portland, OR) ; Wilson; Howard A.; (Beaverton,
OR) ; Gardner; Donald S.; (Mountain View, CA)
; Hazucha; Peter; (Beaverton, OR) ; Schrom;
Gerhard; (Hillsboro, OR) ; Karnik; Tanay;
(Portland, OR) ; Borkar; Nitin; (Portland, OR)
; De; Vivek K.; (Beaverton, OR) ; Borkar; Shekhar
Y.; (Beaverton, OR) |
Correspondence
Address: |
BLAKELY SOKOLOFF TAYLOR & ZAFMAN LLP
1279 OAKMEAD PARKWAY
SUNNYVALE
CA
94085-4040
US
|
Family ID: |
35559487 |
Appl. No.: |
12/684257 |
Filed: |
January 8, 2010 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10955746 |
Sep 30, 2004 |
|
|
|
12684257 |
|
|
|
|
Current U.S.
Class: |
713/300 |
Current CPC
Class: |
H01L 2924/00011
20130101; G06F 1/26 20130101; H01L 2924/3011 20130101; H01L 25/0657
20130101; H01L 2225/06527 20130101; H01L 2225/06513 20130101; H01L
25/18 20130101; H01L 2924/00014 20130101; H01L 2924/00011 20130101;
H01L 2224/0401 20130101; H01L 2224/0401 20130101; H01L 2924/00014
20130101; G06F 1/189 20130101; H01L 2224/16 20130101 |
Class at
Publication: |
713/300 |
International
Class: |
G06F 1/26 20060101
G06F001/26 |
Claims
1. A central processing unit (CPU) comprising: a CPU die,
including; a first processing core; a second processing core; and a
voltage regulator die bonded to the CPU die in a three dimensional
packaging configuration, including: a first voltage regulator
module (VRM) to supply a first voltage to the first processing
core; and a second VRM to supply a second voltage to the second
processing core.
2. The CPU of claim 1 wherein the first voltage is equal to the
second voltage.
3. The CPU of claim 1 wherein the voltage regulator die further
comprises: a third VRM to supply a third voltage to a cache at the
CPU die; and a fourth VRM to supply a fourth voltage to an
input/output (I/O) circuitry at the CPU die.
4. The CPU of claim 3 further comprising I/O connections coupled
between the voltage regulator die and the CPU die.
5. The CPU of claim 1 further comprising a package substrate bonded
to the voltage regulator die.
6. The CPU of claim 5 wherein the voltage regulator die is pad
matched to the CPU die and the package substrate.
7. The CPU of claim 1 wherein the voltage regulator die is flipped
and bonded to the CPU die metal side to metal side.
8. A method comprising bonding a voltage regulator die to a central
processing unit (CPU) die in a three-dimensional packaging
configuration.
9. The method of claim 8 further comprising bonding a package
substrate to the voltage regulator die.
10. The method of claim 9 wherein the voltage regulator die is pad
matched to the CPU die and the package substrate.
11. The method of claim 8 further comprising coupling I/O
connections between the voltage regulator die and the CPU die.
12. The method of claim 8 further comprising: supplying a first
voltage to a first processing core on the CPU die with a first
voltage regulator module (VRM) on the voltage regulator die; and
supplying a second voltage to a second processing core on the CPU
die with a second VRM on the voltage regulator die
13. A system comprising: a central processing unit (CPU) having: a
CPU die, including; a first processing core; a second processing
core; and a voltage regulator die bonded to the CPU die in a three
dimensional packaging configuration, including: a first voltage
regulator module (VRM) to supply a first voltage to the first
processing core; a second VRM to supply a second voltage to the
second processing core; a chipset coupled to the CPU; and a main
memory device coupled to the chipset.
14. The system of claim 13 wherein the voltage regulator die
further comprises: a third VRM to supply a third voltage to a cache
at the CPU die; and a fourth VRM to supply a fourth voltage to an
input/output (I/O) circuitry at the CPU die.
15. The system of claim 14 further comprising I/O connections
coupled between the voltage regulator die and the CPU die.
16. The system of claim 13 wherein the CPU further comprises a
package substrate bonded to the voltage regulator die.
17. The system of claim 65 wherein the voltage regulator die is pad
matched to the CPU die and the package substrate.
18. The system of claim 13 wherein the voltage regulator die is
flipped and bonded to the CPU die metal side to metal side.
Description
PRIORITY
[0001] This application is a continuation of application Ser. No.
10/955,746, entitled CPU Power Delivery System, and claims priority
therefrom.
FIELD OF THE INVENTION
[0002] The present invention relates to computer systems; more
particularly, the present invention relates to delivering power to
a central processing unit (CPU).
BACKGROUND
[0003] Integrated circuit components, such as central processing
units (CPUs), are typically powered by a voltage regulator module
(VRM) located at a remote location, such as on the CPU motherboard.
The motherboard voltage regulator module (VRM) typically supplies a
single supply voltage (Vcc) to multiple CPU cores, a cache and
input/output (I/O) components. This is due to the fact that power
delivery systems do not have sufficient area on the board, socket
and package to route separate supply voltages to multiple cores,
cache and I/O components.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] The invention is illustrated by way of example and not
limitation in the figures of the accompanying drawings, in which
like references indicate similar elements, and in which:
[0005] FIG. 1 is a block diagram of one embodiment of a computer
system;
[0006] FIG. 2 illustrates one embodiment of a CPU die;
[0007] FIG. 3 illustrates one embodiment of a voltage regulator
die; and
[0008] FIG. 4 illustrates one embodiment of a CPU.
DETAILED DESCRIPTION
[0009] According to one embodiment, a power delivery system for a
CPU is described. In the following detailed description of the
present invention, numerous specific details are set forth in order
to provide a thorough understanding of the present invention.
However, it will be apparent to one skilled in the art that the
present invention may be practiced without these specific details.
In other instances, well-known structures and devices are shown in
block diagram form, rather than in detail, in order to avoid
obscuring the present invention.
[0010] Reference in the specification to "one embodiment" or "an
embodiment" means that a particular feature, structure, or
characteristic described in connection with the embodiment is
included in at least one embodiment of the invention. The
appearances of the phrase "in one embodiment" in various places in
the specification are not necessarily all referring to the same
embodiment.
[0011] FIG. 1 is a block diagram of one embodiment of a computer
system 100. Computer system 100 includes a central processing unit
(CPU) 102 coupled to bus 105. In one embodiment, CPU 102 is a
processor in the Pentium.RTM. family of processors including the
Pentium.RTM. II processor family, Pentium.RTM. III processors, and
Pentium.RTM. IV processors available from Intel Corporation of
Santa Clara, Calif. Alternatively, other CPUs may be used.
[0012] A chipset 107 is also coupled to bus 105. Chipset 107
includes a memory control hub (MCH) 110. MCH 110 may include a
memory controller 112 that is coupled to a main system memory 115.
Main system memory 115 stores data and sequences of instructions
that are executed by CPU 102 or any other device included in system
100. In one embodiment, main system memory 115 includes dynamic
random access memory (DRAM); however, main system memory 115 may be
implemented using other memory types. Additional devices may also
be coupled to bus 105, such as multiple CPUs and/or multiple system
memories.
[0013] Chipset 107 also includes an input/output control hub (ICH)
140 coupled to MCH 110 to via a hub interface. ICH 140 provides an
interface to input/output (I/O) devices within computer system 100.
For instance, ICH 140 may be coupled to a Peripheral Component
Interconnect bus adhering to a Specification Revision 2.1 bus
developed by the PCI Special Interest Group of Portland,
Oregon.
[0014] FIG. 2 illustrates one embodiment of a CPU 102 die 200. Die
200 includes four CPU processing cores (core 1-core 4) 210. In
addition, die 200 includes cache 220 and I/O circuitry 230. In one
embodiment, cache 220 is a L2/L3 cache. I/O circuitry 230 is placed
on the periphery (e.g., north, south, east, and west boundaries) to
enable efficient vertical current delivery to cores 210.
[0015] As discussed above, a motherboard voltage regulator module
typically supplies a single Vcc to the cores, cache and I/O
circuitry since power delivery systems do not have sufficient area
on the board, socket and package to route separate supply voltages
to multiple cores, cache and I/O components.
[0016] Various architectural studies have shown that there is a
tremendous power saving if all cores are not active and performing
at the same Vcc at the same time. Thus, variable core-level Vcc
provides significant power saving. Moreover, components within a
single core can be shut down or put on lower Vcc to save active
power. For example, a core may include performance-critical and
non-critical components. The core would operate more efficiently if
the non-critical component could be supplied by a separate, lower
Vcc to save active and leakage power. However, as discussed above,
an external VRM on a motherboard is insufficient to enable a
multi-Vcc solution.
[0017] According to one embodiment, a multiple Vcc VRM die is
bonded to CPU die 200. FIG. 3 illustrates one embodiment of a VRM
die 300. In one embodiment, VRM die 300 includes seven VRMs (VRM
1-VRM 7) that provide a regulated voltage supply to each component
within CPU die 200. For instance VRM 1-VRM 4 supply a Vcc voltages
to Core 1-Core 4, respectively.
[0018] In addition, VRM 5 supplies a Vcc to cache 220, while VRM 6
and VRM 7 provide voltages to I/O circuitry 230, respectively. Note
that in other embodiments, other quantities of VRMs may be included
in die 300, depending on the number of components within die 200
that are to have separate voltage supplies. Also, the voltages
supplied by each VRM may be the same or different from voltages
supplied by the other VRMs.
[0019] According to one embodiment, die 300 is flipped and bonded
(metal-side to metal-side) to supply appropriate cores, thus
bringing the VRMs as close to the CPU die 200 as possible. In a
further embodiment, VRM die 300 is in a three dimensional (3D)
packaging configuration with die 200.
[0020] FIG. 4 illustrates one embodiment of CPU 102. CPU 102
includes the multi-Vcc VRM die 300 sandwiched between CPU die 200
and a package substrate 400. According to one embodiment, VRM die
300 is pad matched to CPU die 200 and package substrate 400 so that
die 300 can be an option sandwiched die. Thus, package 400 and CPU
200 design does not need any changes.
[0021] In addition, FIG. 4 shows the I/O connections between die
200 and 300, as well as the die/die bonding. Note that only two
regulators are shown on die 200 for simplicity. Further, a heat
spreader and heat sink (not shown) may be coupled to CPU die
200.
[0022] The above-described integrated 3D VRM avoids the
discontinuities and impedances in the VRM to die power delivery
path, which give rise to amplitude/phase degradation and response
time delay.
[0023] Whereas many alterations and modifications of the present
invention will no doubt become apparent to a person of ordinary
skill in the art after having read the foregoing description, it is
to be understood that any particular embodiment shown and described
by way of illustration is in no way intended to be considered
limiting. Therefore, references to details of various embodiments
are not intended to limit the scope of the claims, which in
themselves recite only those features regarded as essential to the
invention.
* * * * *