U.S. patent application number 12/388771 was filed with the patent office on 2010-05-06 for chip package and manufacturing method thereof.
This patent application is currently assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC.. Invention is credited to Jaesun An, Dongkyun Ko, Jung Lee.
Application Number | 20100110656 12/388771 |
Document ID | / |
Family ID | 42130376 |
Filed Date | 2010-05-06 |
United States Patent
Application |
20100110656 |
Kind Code |
A1 |
Ko; Dongkyun ; et
al. |
May 6, 2010 |
CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
Abstract
A chip package including a plurality of conductive bodies and a
shielding layer for better electromagnetic interferences shielding
is provided. The shielding layer over the molding compound contacts
with the conductive bodies disposed on the substrate, and the
shielding layer and the conductive bodies function as EMI shield.
The shielding layer is electrically grounded through the conductive
bodies connected to the laminate substrate and the ground plane of
the substrate.
Inventors: |
Ko; Dongkyun; (Kyunggi-Do,
KR) ; Lee; Jung; (Kyunggi-Do, KR) ; An;
Jaesun; (Kyunggi-Do, KR) |
Correspondence
Address: |
J C PATENTS
4 VENTURE, SUITE 250
IRVINE
CA
92618
US
|
Assignee: |
ADVANCED SEMICONDUCTOR ENGINEERING,
INC.
Kaohsiung
TW
|
Family ID: |
42130376 |
Appl. No.: |
12/388771 |
Filed: |
February 19, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61109937 |
Oct 31, 2008 |
|
|
|
Current U.S.
Class: |
361/818 ;
156/242 |
Current CPC
Class: |
H01L 2224/97 20130101;
H01L 2924/3025 20130101; H01L 2924/00011 20130101; H05K 2203/0415
20130101; H01L 2924/01047 20130101; H01L 2924/014 20130101; H01L
2924/181 20130101; H05K 3/0032 20130101; H01L 2924/01024 20130101;
H01L 2924/15311 20130101; H01L 24/97 20130101; H01L 23/3121
20130101; H05K 3/0052 20130101; H01L 2924/01079 20130101; H01L
2924/14 20130101; H01L 2924/14 20130101; H01L 21/561 20130101; H01L
21/78 20130101; H05K 1/0218 20130101; H01L 2924/01033 20130101;
H01L 2924/01078 20130101; H01L 2224/97 20130101; H01L 2224/16225
20130101; H01L 2924/15313 20130101; H01L 23/552 20130101; H01L
2924/00014 20130101; H01L 2924/01006 20130101; H01L 2924/00014
20130101; H01L 2924/01029 20130101; H01L 2924/00011 20130101; H01L
2224/81 20130101; H01L 2924/00 20130101; H01L 2224/0401 20130101;
H01L 2924/00 20130101; H01L 2224/0401 20130101; H01L 2924/01013
20130101; H01L 2924/181 20130101; H01L 2924/1815 20130101; H05K
3/284 20130101 |
Class at
Publication: |
361/818 ;
156/242 |
International
Class: |
H05K 9/00 20060101
H05K009/00; B29D 31/00 20060101 B29D031/00 |
Claims
1. A chip package, comprising: a laminate substrate; at least a
chip disposed on the laminate substrate; a plurality of conductive
bodies disposed on the laminate substrate and around the chip; a
molding compound, at least encapsulating the chip, a portion of the
laminate substrate and the plurality of the conductive bodies; and
a shielding layer, disposed over the molding compound, covering the
molding compound and partially covering at least a top surface of
each conductive body exposed by the molding compound.
2. The chip package as claimed in claim 1, wherein at least a
sidewall of each conductive body is exposed and is aligned with an
edge of the shielding layer.
3. The chip package as claimed in claim 1, wherein sidewalls of the
conductive bodies are covered by the molding compound and an edge
of the molding compound is aligned with an edge of the shielding
layer.
4. The chip package as claimed in claim 1, wherein the chip is
electrically connected to the contacts through a plurality of bumps
arranged underneath the chip.
5. The chip package as claimed in claim 1, wherein the conductive
bodies are arranged around the chip as a ring, and the chip is
separated from the conductive bodies.
6. The chip package as claimed in claim 1, wherein the chip is a
radio frequency chip.
7. The chip package as claimed in claim 1, wherein the shielding
layer is electrically connected to the laminate substrate via the
conductive body and at least a ground via of the laminate
substrate.
8. The chip package as claimed in claim 1, wherein the conductive
body is made of a solder material and the conductive body is a
solder block.
9. The chip package as claimed in claim 1, wherein the conductive
body is a part of a printed circuit board.
10. The chip package as claimed in claim 1, wherein the conductive
body is a part of a leadframe.
11. The chip package as claimed in claim 1, wherein a material of
the shielding layer is a metal material.
12. A manufacturing method of a chip package, comprising: providing
a matrix substrate having a plurality of substrate units, wherein
each substrate unit is defined by a plurality of sawing lines and
has a die attaching region thereon; forming a plurality of
conductive bodies on each substrate unit and arranged around the
die attaching region; disposing at least a chip on the die
attaching region of the substrate unit, wherein the chip is
electrically connected to the substrate unit, and the plurality of
conductive bodies is separated from the chip; forming a molding
compound over the matrix substrate to encapsulate the chip,
portions of the substrate units and the conductive bodies;
performing a marking process to remove a portion of the molding
compound until a top surface of each conductive body is exposed;
forming a shielding layer over the molding compound to cover the
molding compound and the exposed top surface of each conductive
body; and performing a singulation process to obtain a plurality of
chip packages.
13. The method as claimed in claim 12, wherein the conductive
bodies are arranged on sawing lines of the matrix substrate and on
boundary lines of each substrate unit.
14. The method as claimed in claim 12, wherein the conductive
bodies are arranged around boundary lines of each substrate unit
with a distance apart.
15. The method as claimed in claim 12, wherein the conductive
bodies are formed from a metallic material by a spraying process, a
sputtering process or a plating process.
16. The method as claimed in claim 12, wherein the conductive
bodies are formed from a solder material by a spraying process or a
printing process.
17. The method as claimed in claim 12, wherein the marking process
comprises a laser digging process or a laser drilling process.
18. The method as claimed in claim 12, wherein the chip is
electrically connected to the substrate through flip chip bonding.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the priority benefit of U.S.
provisional application Ser. No. 61/109,937, filed on Oct. 31,
2008. The entirety of the above-mentioned patent application is
hereby incorporated by reference herein and made a part of
specification.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor device, and
more particularly to a chip package.
[0004] 2. Description of Related Art
[0005] Electro-magnetic interference (EMI) is a serious and
challenging problem for most electronic devices or systems. As EMI
disturbances commonly interrupt, degrade or limit the effective
performance of the electronic device or the whole circuit of the
electronic system, it is necessary for the electronic devices or
systems to have efficient EMI protection to ensure the effective
and safe operation.
[0006] EMI protection is particularly important in small-sized,
densely packaged or sensitive electronic applications operating at
high frequencies. Conventionally, EMI shielding solutions typically
involve the use of metal plates and/or conductive gaskets, which
are later attached or affixed at higher manufacturing costs.
SUMMARY OF THE INVENTION
[0007] In view of the foregoing, the present invention provides a
manufacturing method of a chip package, which offers better design
flexibility with less effort.
[0008] The present invention is further directed to a chip package
with enhanced effectiveness of EMI shielding.
[0009] The present invention provides a chip package including a
laminate substrate, at least a chip disposed on the laminate
substrate, a plurality of conductive bodies, a molding compound and
a shielding layer. The conductive bodies disposed on the laminate
substrate are arranged around the chip. The molding compound at
least encapsulates the chip, a portion of the laminate substrate
and the conductive bodies, but partially exposes top surfaces of
the conductive bodies. The shielding layer disposed over the
molding compound covers not only the molding compound but also the
exposed top surface of each conductive body.
[0010] According to embodiments of the present invention, either
solder materials or parts of the leadframe or printed circuit board
can be used to form the conductive bodies.
[0011] According to embodiments of the present invention, the
conductive bodies can be arranged at the boundary lines of the
laminate substrate and at least a side surface of each conductive
body is exposed.
[0012] According to embodiments of the present invention, the
conductive bodies can be arranged along the boundary lines of the
laminate substrate and the side surfaces of each conductive body
are not exposed.
[0013] According to embodiments of the present invention, the chip
is electrically connected to the laminate substrate of the chip
package though a plurality of bumps.
[0014] The invention further provides a manufacturing method of a
chip package. A plurality of conductive bodies are formed on each
substrate unit of the provided matrix substrate and arranged around
the die attaching region of the substrate unit. At least a chip is
disposed on the die attaching region of the substrate unit, and the
chip is electrically connected to the substrate unit. After forming
a molding compound over the matrix substrate to encapsulate the
chip, portions of the substrate units and the conductive bodies, a
marking process is performed to remove a portion of the molding
compound until a top surface of each conductive body is exposed.
Later, a shielding layer is formed over the molding compound to
cover the molding compound and the exposed top surface of each
conductive body. Then a singulation process is performed to obtain
a plurality of chip packages.
[0015] According to one embodiment of the present invention, the
conductive bodies can be arranged on sawing lines of the matrix
substrate and on boundary lines of each substrate unit, or arranged
around boundary lines of each substrate unit with a distance
apart.
[0016] According to one embodiment of the present invention, the
conductive bodies are formed from a metallic material by a spraying
process, a sputtering process or a plating process, or formed from
a solder material by a spraying process or a printing process.
[0017] According to one embodiment of the present invention, the
marking process comprises a laser digging process or a laser
drilling process.
[0018] Based on the above, the shielding layer and the connected
conductive bodies disposed on the substrate functions as an EMI
shield of the chip package for the surrounding EMI radiation.
According to the present invention, a complete EMI shielding is
achieved through the shielding layer and the conductive bodies with
flexible and variable designs. Therefore, the chip package of the
present invention has better EMI shielding effectiveness and
improved process windows.
[0019] In order to the make the aforementioned and other objects,
features and advantages of the present invention comprehensible,
several embodiments accompanied with figures are described in
detail below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIGS. 1A through 1G are schematic views showing a
manufacturing method of the chip package according to one preferred
embodiment of the present invention.
[0021] FIG. 2 is a cross-sectional view of a chip package according
to an embodiment of the present invention.
[0022] FIG. 3 is a cross-sectional view of a chip package according
to another embodiment of the present invention.
DESCRIPTION OF EMBODIMENTS
[0023] Reference will now be made in detail to the present
preferred embodiments of the invention, examples of which are
illustrated in the accompanying drawings. Wherever possible, the
same reference numbers are used in the drawings and the description
to refer to the same or like parts.
[0024] The manufacturing methods as described in the present
invention can be used for fabricating various package structures
and are more suitable for fabricating stacked type packages,
multiple-chip packages, or high frequency device packages
(including radio frequency device packages). Moreover, the
manufacturing methods as described in the present invention are
compatible with packaging processes utilizing build-up substrate
manufacturing process or array substrate manufacturing process.
[0025] FIGS. 1A through 1G are schematic views showing a
manufacturing method of the chip package according to the preferred
embodiment of the present invention. FIGS. 1A, 1B, 1B' and 1C are
shown in three-dimensional schematic views, while FIGS. 1D-1G are
shown in cross-sectional schematic views.
[0026] Referring to FIG. 1A, a matrix substrate 100 having a
plurality of substrate 102 (defined by the subsequent sawing lines
shown as dotted lines) is provided, while each substrate 102
includes a plurality of contacts 104 thereon. The contacts 104 are
arranged within the die attaching area 103 of each substrate 102.
The contacts 104 function as bump pads for flip chip connecting
technology. The substrate 100 can be a laminate substrate, for
example, a printed circuit board (PCB).
[0027] Referring to FIG. 1B, a plurality of conductive bodies 110
is disposed over the top surface 102a of the substrate 102, outside
the die attaching area 103. Preferably, the conductive bodies 110
are arranged around the boundary or perimeter of each substrate
102. As shown in FIG. 1B, the individual conductive bodies 110 are
arranged right on the boundary lines of the substrate 102 (the
dotted lines). In this case, the subsequent sawing process will cut
through the conductive bodies 110 arranged along the sawing
lines.
[0028] On the other hand, the individual conductive bodies 110 may
be arranged along the boundary lines of the substrate 102 but are
not exactly located on the boundary lines of the substrate 102 (the
dotted lines), as shown in FIG. 1B'. The conductive bodies 110 may
be arranged close to the boundary lines of the substrate 102,
separate by a small distance d, and d can be varied according to
product requirements. However, the subsequent sawing process will
not cut through the conductive bodies 110 arranged along the sawing
lines.
[0029] The conductive body 110 can be made of a solder material,
for example. Alternatively, the conductive body 110 can be made
from a conductive carrier, such as, a leadframe or a laminate
printed circuit board. The shape of the conductive body 110 can be
polygonal blocks (shown as rectangular blocks in FIG. 1B or 1B').
However, the conductive body 110 can be shaped as blocks, strips or
even connected with one another as a ring structure, for example.
In general, the sizes or the shape of conductive body 110 can be
varied depending on the shielding requisites or other electrical
properties of the package or even varied in accordance with the
processing parameters.
[0030] If a multi-layered substrate, such as a multi-layered PCB,
is employed, it is possible to form the conductive bodies 110 from
the routing manufacturing step of the build-up substrate
manufacturing process. That is, during the routing process to form
the traces of the substrate, the conductive bodies can be formed by
the same process as patterned metallic blocks, other than the
traces.
[0031] Referring to FIG. 1C, at least a chip 120 is disposed on
each substrate 102 and within attaching area 103. Although a chip
is provided herein, other surface mount components can be employed,
and encompassed within the scope of this invention. The chip 120 is
electrically connected to the contacts 104 of the substrate 102
through a plurality of bumps 106 (shown in FIG. 1D) there-between.
Although flip chip connecting technology is described herein, it is
well encompassed within the scope of this invention to employ wire
bonding technology (i.e. through wire connections). The chip 120
should be completely separated from the conductive bodies 110.
[0032] Referring to FIG. 1D, a molding process is carried out to
form a molding compound 130 on the matrix substrate 100 to
encapsulate the conductive bodies 110, the chips 120, the bumps 106
and at least a portion of the substrate 102. The molding process
can be an over-molding process, for example. Although the
conductive body 110 is depicted as higher than the total height of
the chip 120 and the bumps 106, it is optional to form the
conductive body 110 with a height smaller or larger than the total
height of the chip 120 and the bumps 106.
[0033] Referring to FIG. 1E, a marking process is performed to
remove portions of the molding compound 130 over the conductive
bodies 110, so that the top surface 110a of each conductive body
110 is at least partially exposed. The top surface 110a of the
conductive body can be partially exposed or completely exposed. The
marking process may include a laser drilling process or a laser
digging process, for example. Taking the conductive bodies arranged
around the boundary of each substrate 102 as an example, the
marking process may removes portions of the molding compound 130 by
forming a ring-like trench within the molding compound 130 over the
conductive bodies 110, around the boundary of each substrate
102.
[0034] Referring to FIG. 1F, a shielding layer 140 is formed over
the molding compound 130 to cover the molding compound 130 and the
exposed top surfaces 110a of the conductive bodies 110. The
shielding layer 140 can be formed by a spray coating method, a
plating method, or a sputtering method, for example.
[0035] Finally, referring to FIG. 1G, a singulation process is
performed to obtain the individual chip packages 10. The
singulation process may be a blade sawing process, for example.
[0036] FIG. 2 is a cross-sectional view of a chip package according
to a preferred embodiment of the present invention. Referring to
FIG. 2, the chip package 20 of the present embodiment includes a
substrate 102, a plurality of bumps 106, a plurality of conductive
bodies 110, at least a chip 120, a molding compound 130 and a
shielding layer 140. The substrate 102 can be a laminated
substrate, for example, a two-layered or a four-layered laminated
PCB substrate. The chip 120 can be a semiconductor chip, for
example, a radio-frequency (RF) chip. The material of the shielding
layer 140 may be copper, aluminum or alloys thereof or even a
solder material, for example. The chips 120 are electrically
connected to the substrates 102 through bumps 106. The molding
compound 130 encapsulates portions of the substrates 102, the
conductive bodies 110, and the chips 120. Besides, the shielding
layer 140 is disposed over the molding compound 130, covering the
top surface of the molding compound 130 and the exposed top
surfaces 110a of the conductive bodies 110. The shielding layer 140
is electrically connected to the substrate 102 through the
conductive bodies 110.
[0037] For example, the conductive body 110 can be made from a
laminated PCB or a leadframe (i.e. be a chunk or a piece of a
laminated PCB or a leadframe), for example. If the conductive body
110 is a piece of a laminated PCB, the shielding layer 140 can be
electrically connected to the substrate 102 through vias or plated
through-holes of the conductive bodies 110, for example. If the
conductive body 110 is a piece of a leadframe, the shielding layer
140 can be electrically connected to the substrate 102 through the
conductive bodies 110 and the conductive bodies 110 can be fixed to
the substrate 102 through conductive adhesives, such as anisotropy
conductive films (ACF), for example. Alternatively, the conductive
body 110 can be made of a solder material; i.e. be a solder lump,
strip or a solder ring structure, for example.
[0038] In addition, the conductive body 110 is connected to a
ground vias 108 of the substrate 102, and the shielding layer 140
is electrically grounded through the conductive body 110 and the
ground via 108. Hence, taking advantage of the metal wirings or
traces of the substrate surface, the shielding layer of the present
invention can be grounded within the package structure using the
ground plane of the substrate. It should be noted that at least a
sidewall 110b of each conductive body 110 is aligned with the edge
of the shielding layer 140, as the sawing process cuts through the
conductive bodies arranged on the sawing street lines. That is, the
sidewall 110b of each conductive body 110 is exposed.
[0039] According to another embodiment, as shown in FIG. 3, the
sidewall 110b of each conductive body 110 is not exposed and is
covered by the molding compound 130. Instead, the conductive bodies
110 are fully encapsulated by the molding compound 130, except the
exposed top surface 110a. The sidewall 130b of the molding compound
is aligned with an edge of the shielding layer, through the cutting
of the singulation process. Basically, the package structure 30
follows the manufacturing step shown in FIG. 1B' (rather than FIG.
1B), and the sawing process does not cut through the conductive
bodies arranged around the sawing street lines.
[0040] In the chip package structures of the present embodiment,
the shielding layer and the conductive bodies disposed on the
substrate together function as an EMI shield, protecting the
package from the EMI radiation from the surrounding radiation
sources.
[0041] Furthermore, as the shielding layer is formed over the whole
matrix substrate and the molding compound before the singulation
process, no half-cutting process is required and the process window
is increased and the reliability is improved.
[0042] In summary, the shielding layer and the conductive bodies
can efficiently shelter the chip package of the present invention
from the outside EMI radiation, thus boosting the EMI shielding.
Following the manufacturing processes disclosed in the present
invention, it is possible to establish an electrical ground path
within the package structure, devoid of using an extra ground
plane. Accordingly, such design is compatible with the packaging of
high frequency devices, particularly, radio frequency devices.
[0043] Although the present invention has been disclosed above by
the embodiments, they are not intended to limit the present
invention. Anybody skilled in the art can make some modifications
and alteration without departing from the spirit and scope of the
present invention. Therefore, the protecting range of the present
invention falls in the appended claims.
* * * * *