U.S. patent application number 12/264522 was filed with the patent office on 2010-05-06 for high bandwidth package.
This patent application is currently assigned to SEAGATE TECHNOLOGY LLC. Invention is credited to Patrick Ryan, Dadi Setiadi.
Application Number | 20100109153 12/264522 |
Document ID | / |
Family ID | 42130391 |
Filed Date | 2010-05-06 |
United States Patent
Application |
20100109153 |
Kind Code |
A1 |
Setiadi; Dadi ; et
al. |
May 6, 2010 |
HIGH BANDWIDTH PACKAGE
Abstract
Method and apparatus for constructing and operating a high
bandwidth package in an electronic device, such as a data storage
device. In some embodiments, a high bandwidth package comprises a
first known good die that has channel functions, a second known
good die that has a controller function, and a third known good die
that has a buffer function. Further in some embodiments, the high
bandwidth package has pins that connect to each of the first,
second, and third dies.
Inventors: |
Setiadi; Dadi; (Edina,
MN) ; Ryan; Patrick; (St. Paul, MN) |
Correspondence
Address: |
Fellers, Snider, Blankenship, Bailey & Tippens, PC;(Seagate Technology
LLC)
100 North Broadway, Suite 1700
Oklahoma City
OK
73102-8820
US
|
Assignee: |
SEAGATE TECHNOLOGY LLC
Scotts Valley
CA
|
Family ID: |
42130391 |
Appl. No.: |
12/264522 |
Filed: |
November 4, 2008 |
Current U.S.
Class: |
257/713 ;
257/723; 257/E23.08 |
Current CPC
Class: |
H01L 2225/06596
20130101; H01L 2924/00014 20130101; H01L 2924/00014 20130101; H01L
23/3128 20130101; H01L 2224/48091 20130101; H01L 2225/0651
20130101; H01L 2924/181 20130101; H01L 25/18 20130101; H01L
2924/181 20130101; H01L 24/48 20130101; H01L 2924/00014 20130101;
H01L 2924/14 20130101; H01L 2224/48091 20130101; H01L 2224/48227
20130101; H01L 2224/32145 20130101; H01L 2924/14 20130101; H01L
2225/06572 20130101; H01L 2225/0652 20130101; H01L 2924/15311
20130101; H01L 25/0657 20130101; H01L 23/367 20130101; H01L
2924/00012 20130101; H01L 2224/45015 20130101; H01L 2224/45099
20130101; H01L 2924/207 20130101; H01L 2924/00014 20130101; H01L
2924/00 20130101 |
Class at
Publication: |
257/713 ;
257/723; 257/E23.08 |
International
Class: |
H01L 23/34 20060101
H01L023/34 |
Claims
1. An apparatus comprising a first known good die having channel
functions, a second known good die having controller functions, and
a third known good die having a buffer function, wherein the first,
second, and third dies are packaged together in a single package
and interconnects of the single package connect to the first,
second, and third dies.
2. The apparatus of claim 1, further comprising a fourth known good
die having servo motor control logic function connected to the
first, second, and third dies with interconnects and packaged in a
single package.
3. The apparatus of claim 1, further comprising a heat sink being
packaged with the first, second, and third dies in a single
package.
4. The apparatus of claim 3, wherein a plurality of heat sinks are
enclosed in the package, the plurality of heat sinks including heat
sink fins.
5. The apparatus of claim 3, wherein the first, second, and third
dies are arranged so that the die that emits the most heat during
operation is packaged closest to the heat sink
6. The apparatus of claim 1, wherein the package is installed on a
printed circuit board.
7. The apparatus of claim 6, wherein the printed circuit board has
a thermal interface material that is configured to draw heat away
from the adjacently installed package.
8. The apparatus of claim 1, wherein the interconnects are
pins.
9. The apparatus of claim 1, wherein the known good dies have
standardized interfaces.
10. The apparatus of claim 1, wherein at least one known good die
comprises a previously defective die that has been repaired prior
to packaging in the single package.
11. A method comprising: connecting a first known good die having
channel functions to a second known good die having controller
functions with interconnects; connecting a third known good die
having buffer functions to the first and second known good dies
with interconnects; and integrating the first, second, and third
known good dies into a single package.
12. The method of claim 11, further comprising the step of
connecting a fourth known good die having servo motor control logic
function to the first, second, and third dies with interconnects
and packaged in a single package.
13. The method of claim 11, further comprising the step of
packaging a heat sink with the first, second, and third dies in a
single package.
14. The method of claim 13, wherein a plurality of heat sinks are
enclosed in the package, the plurality of heat sinks including heat
sink fins.
15. The method of claim 13, wherein the first, second, and third
dies are arranged so that the die that emits the most heat during
operation is packaged closest to the heat sink.
16. The method of claim 11, further comprising the step of
installing the single package on a printed circuit board.
17. The method of claim 16, wherein the printed circuit board has a
thermal interface material that is configured to draw heat away
from the adjacently installed package.
18. The method of claim 11, wherein the interconnects are pins.
19. The method of claim 11, further comprising the steps of testing
each die prior to the connecting steps and testing the single
package after the integrating step.
20. The method of claim 19, further comprising the step of
repairing a defective die.
Description
BACKGROUND
[0001] Electronic devices generally operate to store and retrieve
data in a fast and efficient manner. Some storage devices utilize
numerous chips on a circuit board to facilitate the various
functions of the device. The chips occasionally are stacked
vertically and packaged to save space on a circuit board.
[0002] As will be appreciated, individual chips in a package often
are plagued by errors that are inherent with manufacturing variance
that cannot be corrected once packaged. The reliability of the
circuit board is hindered when multiple functions are connected in
a single package. Thus, errors can affect the functionality of
packaged chips so that considerable loss in efficiency and accuracy
is noticeable.
[0003] In these and other types of electronic devices, it is often
desirable to increase simplicity and accuracy, particularly with
regard to reliability of components of a chip package once
packaged.
SUMMARY
[0004] Various embodiments of the present invention are generally
directed to a method and apparatus for constructing and operating a
high bandwidth package in an electronic device such as, but not
limited to, a data storage device.
[0005] In accordance with various embodiments, a first known good
die that has channel functions is utilized in the high bandwidth
package. Further, a second known good die that has a controller
function and a third known good die that has a buffer function are
incorporated into a single package with the first known good die.
The first, second, and third known good dies are each connected
with pins of the high bandwidth package.
[0006] In other embodiments, a first, second, and third known good
dies are enclosed to form a high bandwidth package. Where the first
known good die has channel functions, the second known good dies
has controller functions, and the third known good die has buffer
functions.
[0007] These and various other features and advantages which
characterize the various embodiments of the present invention can
be understood in view of the following detailed discussion and the
accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1 is a generalized functional representation of an
exemplary electronic device constructed and operated in accordance
with various embodiments of the present invention.
[0009] FIG. 2 generally illustrates a conventional printed circuit
board.
[0010] FIG. 3 is a generalized block diagram of a controller.
[0011] FIG. 4 displays a block diagram of a package constructed and
operated in accordance with the various embodiments of the present
invention.
[0012] FIG. 5 shows a cross-sectional view of a package constructed
and operated in accordance with the various embodiments of the
present invention.
[0013] FIG. 6 displays a cross-sectional view of an alternative
package structure capable of being constructed and operated in
accordance with the various embodiments of the present
invention.
[0014] FIG. 7 generally illustrates a printed circuit board
utilizing a high bandwidth package constructed in accordance with
the various embodiments of the present invention.
[0015] FIG. 8 shows a flow diagram of a package operation carried
out in accordance with the various embodiments of the present
invention.
DETAILED DESCRIPTION
[0016] FIG. 1 provides a functional block representation of an
electrical device 100, such as a data storage device constructed
and operated in accordance with various embodiments of the present
invention. The electrical device is contemplated as comprising a
non-volatile memory storage device. It will be appreciated,
however, that such characterization of the device 100 is merely for
purposes of illustrating a particular embodiment and is not
limiting to the claimed subject matter.
[0017] Top level control of the device 100 is carried out by a
suitable controller 102, which may be a programmable or hardware
based microcontroller. The controller 102 communicates with a host
device via a controller interface (I/F) circuit 104 and a host I/F
circuit 106. Local storage of requisite commands, programming,
operational data, etc. is provided via random access memory (RAM)
108 and read-only memory (ROM) 110. A buffer 112 serves to
temporarily store input write data from the host device and
readback data pending transfer to the host device.
[0018] A memory space is shown at 114 to comprise a number of
memory arrays 116 (denoted Array 0-N), although it will be
appreciated that a single array can be utilized as desired. Each
array 116 comprises a block of semiconductor memory of selected
storage capacity. Further in the memory space 114, a hard disk
interface 117 can be included to allow a magnetic data storage
device to be implemented. The hard disk interface 117 can be
accessed by the memory interface 118 either individually or in
combination with other data storage memory arrays 116.
[0019] Communications between the controller 102 and the memory
space 114 are coordinated via a memory (MEM) I/F 118. As desired,
on-the-fly error detection and correction (EDC) encoding and
decoding operations are carried out during data transfers by way of
an EDC block 120.
[0020] While not limiting, in some embodiments the various circuits
depicted in FIG. 1 are arranged as a single chip set formed on one
or more semiconductor dies with suitable encapsulation, housing and
interconnection features (not separately shown for purposes of
clarity). Input power to operate the device is handled by a
suitable power management circuit 122 and is supplied from a
suitable source such as from a battery, AC power input, etc. Power
can also be supplied to the device 100 directly from the host such
as through the use of a USB-style interface, etc.
[0021] Any number of data storage and transfer protocols can be
utilized, such as logical block addressing (LBAs) whereby data are
arranged and stored in fixed-size blocks (such as 512 bytes of user
data plus overhead bytes for ECC, sparing, header information,
etc). Host commands can be issued in terms of LBAs, and the device
100 can carry out a corresponding LBA-to-PBA (physical block
address) conversion to identify and service the associated
locations at which the data are to be stored or retrieved.
[0022] FIG. 2 provides an exemplary printed circuit board 124. A
printed circuit board 124 is often utilized in various electronic
devices 100 including, but not limited to, data storage devices.
The functions of an electronic device 100 are controlled by the
hardware installed on, and connected by, the printed circuit board
124. Hardware on a printed circuit board 124 can include an
application specific integrated circuit (ASIC) controller 126, a
memory buffer 128, a servo motor control logic 130, and a read
channel signal processor 132. It should be noted that the printed
circuit board 124 can employ numerous individual chips with
independent functions, individual chips with multiple functions, or
a single package having multiple functions either alone or in
combination with one another. For example the memory buffer 128 can
consist of two dies: a non-volatile memory such as, but not limited
to NOR flash, and a volatile memory such as, but not limited to
dynamic RAM (DRAM).
[0023] A block diagram of a general electronic device control
structure 134 is displayed in FIG. 3. The electronic control
structure 134 has a main controller 136 that sends and receives
signals to various components of the electrical device 100. In some
embodiments, the controller 136 is an ASIC controller that manages
a read channel processor 138, a servo motor control logic 140, and
a memory buffer 142. While the servo motor control logic 140 is
utilized for electronic devices 100 with rotating data storage
mechanisms, the control logic is not required for electronic
devices 100 that store data in solid state memory.
[0024] FIG. 4 shows a block diagram of a high bandwidth package 144
constructed and operated in accordance with the various embodiments
of the present invention. The high bandwidth package 144 has a
memory buffer 142 attached to a controller 136 that is attached to
a read channel processor 138. The position of the controller 136
between the memory buffer 142 and the read channel processor 138
allows for optimal efficiency of the package 144 due to shortened
interconnect pathways from the controller 136 to the respective
components. In some embodiments, the controller 136 is an ASIC
controller that controls a servo motor control logic either on the
same chip or as a layer adjacent to either the memory buffer 142 or
read channel processor 138.
[0025] In FIG. 5, a cross-section of a high bandwidth package 144
is generally illustrated. The high bandwidth package 144 employs a
package on package structure that allows vertical stacking of
individual chips to create an integrated circuit. The circuitry of
the chip that functions to operate the electronic device, such as
the controller 136, read channel processor 138, or memory buffer
142 of FIG. 4 are each integrated onto a die 146 that are connected
with interconnects 148. In some embodiments, each die 146 is a
known good die (KGD) that has been environmentally tested at wafer
level before being manufactured into a chip. The wafer level
testing of a KGD includes laser repair of bad cells, followed by
retesting as necessary. The use of KGD for each chip greatly
increases the performance and reliability of the high bandwidth
package 144 due to the thorough testing and repair of each die
before implementation into the package.
[0026] Further in the high bandwidth package 144, each KGD has
circuitry for a single function such as controller 138 or memory
buffer 142. The packaging of the dies 146 into a single high
bandwidth package 144 greatly reduces the number of interconnects
148 that must be used to properly transmit signals and power
between the dies 146. The reduced number of interconnects 148 also
decreases the noise and radiated emissions of the package 144. It
should be noted that another KGD can be stacked onto the die 146
housing the read channel processor 138 circuitry that functions as
a servo motor control logic 140. The structure and benefits of the
package 144 will not be hindered by the addition of a fourth
die.
[0027] An alternative structure for a high bandwidth package 146 is
displayed in FIG. 6. A heat sink 150 has been connected to the die
146 containing the read channel 138 circuitry. The controller 136
and memory buffer 142 are attached adjacently vertical from the
channel 138. The heat sink 150 has a number of fins 152 that
provide added surface area to dissipate heat. In other embodiments,
the heat sink 150 is placed above the die 146 containing the read
channel 138 circuitry. Further, numerous heat sinks 150 can be
placed in the package to more efficiently dissipate heat that could
damage or decrease performance of the high bandwidth package
146.
[0028] It can be appreciated that heat can be alternatively
dissipated by placing a thermal interface material on the printed
circuit board adjacent to the package. In addition, the position of
the known good dies 146 can be configured so that the die emitting
the most heat during operation is placed on the bottom of the
package so that two die 146 are vertically above the selected die.
Alternatively, the position of the known good die 146 that emits
the most heat during operation can be packaged at the top of the
package so that two die 146 are vertically below the selected
die.
[0029] FIG. 7 generally illustrates a printed circuit board 154
employing a high bandwidth package 144. The increased bandwidth of
vertically stacked chips eliminates numerous connections between
the various die placed on the circuit board 154 as shown in FIG. 2.
The blank area 156 surrounds the primary area of circuit board
interconnect savings that leads to greater electrical device 100
performance due in part to reduced noise.
[0030] FIG. 8 displays a flow diagram of a package operation 160
performed in accordance with the various embodiments of the present
invention. The package operation 156 initially tests each die 146
for compliance as a known good die at step 162. Step 164 packages
the function circuitry, such as controller 136, with the known good
die 146. The first package is placed on a carrier that allows for
interconnection with other packages in step 166. The first package
is connected with a second package containing a function circuitry
in step 168 and subsequently step 170 connects a third package
comprising function circuitry and a known good die to the first and
second packages. The first, second, and third packages are tested
at step 172 and enclosed into a single package if the test is
passed. Finally, the package 144 is installed into an electrical
device 100, such as into a printed circuit board of FIG. 7.
[0031] As can be appreciated by one skilled in the art, the various
embodiments illustrated herein provide advantages in both
electronic device efficiency and complexity. The use of tested and
repaired known good die in conjunction with single function chips
in a package increases the performance of the electrical device
while reducing the noise associated with conventional chip
integration. However, it will be appreciated that the various
embodiments discussed herein have numerous potential applications
and are not limited to a certain field of electronic media or type
of data storage devices.
[0032] It is to be understood that even though numerous
characteristics and advantages of various embodiments of the
present invention have been set forth in the foregoing description,
together with details of the structure and function of various
embodiments of the invention, this detailed description is
illustrative only, and changes may be made in detail, especially in
matters of structure and arrangements of parts within the
principles of the present invention to the full extent indicated by
the broad general meaning of the terms in which the appended claims
are expressed.
* * * * *