U.S. patent application number 12/650406 was filed with the patent office on 2010-04-29 for multi-configuration processor-memory substrate device.
This patent application is currently assigned to NVIDIA CORPORATION. Invention is credited to Behdad Jafari, George Sorensen.
Application Number | 20100103604 12/650406 |
Document ID | / |
Family ID | 30115136 |
Filed Date | 2010-04-29 |
United States Patent
Application |
20100103604 |
Kind Code |
A1 |
Jafari; Behdad ; et
al. |
April 29, 2010 |
MULTI-CONFIGURATION PROCESSOR-MEMORY SUBSTRATE DEVICE
Abstract
A Multi-configuration Processor-Memory device for coupling to a
PCB (printed circuit board) interface. The device comprises a
substrate that supports multiple configurations of memory
components and a processor while having a single, common interface
with a PCB interface of a printed circuit board. In a first
configuration, the substrate supports a processor and a first
number of memory components. In a second configuration, the
substrate supports a processor and an additional number of memory
components. The memory components can be pre-tested, packaged
memory components mounted on the substrate. The processor can be a
surface mounted processor die. Additionally, the processor can be
mounted in a flip chip configuration, side-opposite the memory
components. In the first configuration, a heat spreader can be
mounted on the memory components and the processor to dissipate
heat. In the second, flip chip, configuration, the processor face
can be soldered onto a non-electrically functional area of the PCB
interface of the printed circuit board to dissipate heat.
Inventors: |
Jafari; Behdad; (Saratoga,
CA) ; Sorensen; George; (Fremont, CA) |
Correspondence
Address: |
NVIDIA C/O MURABITO, HAO & BARNES LLP
TWO NORTH MARKET STREET, THIRD FLOOR
SAN JOSE
CA
95113
US
|
Assignee: |
NVIDIA CORPORATION
Santa Clara
CA
|
Family ID: |
30115136 |
Appl. No.: |
12/650406 |
Filed: |
December 30, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12005818 |
Dec 28, 2007 |
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12650406 |
|
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|
10197385 |
Jul 16, 2002 |
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12005818 |
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Current U.S.
Class: |
361/679.31 ;
361/679.46 |
Current CPC
Class: |
H01L 25/18 20130101;
H01L 2224/73253 20130101; H05K 2201/10159 20130101; H05K 1/141
20130101; H05K 1/0204 20130101; H05K 1/0206 20130101; H01L
2224/16225 20130101; H05K 2201/09954 20130101; H01L 2224/16227
20130101; H01L 2924/15311 20130101; H05K 3/3436 20130101; H05K
2203/1572 20130101; G06F 1/183 20130101; H01L 2924/15321 20130101;
H05K 2201/10674 20130101 |
Class at
Publication: |
361/679.31 ;
361/679.46 |
International
Class: |
H05K 7/06 20060101
H05K007/06; H05K 7/20 20060101 H05K007/20 |
Claims
1. A Multi-configuration Processor-Memory device for coupling to a
PCB (printed circuit board) interface of a printed circuit board
comprising: a substrate having a first configuration and a second
configuration, wherein the substrate is configured for mounting a
processor and a first number of memory components in the first
configuration, and mounting the processor and an additional number
of memory components in the second configuration; an interface
built into the substrate for coupling to a PCB interface of a
printed circuit board; and wherein the processor is mounted on the
substrate in a flip chip configuration near the interface of the
substrate, and wherein the memory components and the processor are
surface mounted on the substrate, and wherein the processor has a
ball grid array for mounting on the substrate.
2. The device of claim 1 wherein the processor is mounted on the
substrate on an opposite side of the substrate mounting the memory
components.
3. The device of claim 1 wherein the processor is a GPU (graphics
processor unit).
4. The device of claim 1 wherein the memory components are DDR
(double data rate) memory components.
5. The device of claim 4 wherein the memory components are packaged
memory components.
6. The device of claim 1 wherein the processor is mounted near the
interface of the substrate.
7. The device of claim 6 wherein a surface of the processor is
configured for an attachment to an area of the PCB interface of the
print circuit board to conduct heat from the processor through the
attachment.
8. The device of claim 7 wherein the attachment is a solder
attachment.
9. The device of claim 1 wherein the memory components are
configured to receive a heat spreader to conduct heat from the
memory components.
10. The device of claim 1 wherein the first number of memory
components of the first configuration is 2 memory components and
the second number of memory components of the second configuration
is at least four memory components.
11. A Multi-configuration GPU (graphics processor unit) package for
coupling to a PCB (printed circuit board) interface of a printed
circuit board comprising: a substrate having a first configuration
and a second configuration, wherein the substrate is configured for
mounting a GPU and a first number of memory components in the first
configuration, and mounting the GPU and an additional number of
memory components in the second configuration; a common interface
built into the substrate for coupling to a PCB interface of a
printed circuit board, wherein the common interface is configured
to provide a standardized interconnection to the PCB interface for
both the first configuration and the second configuration; and.
wherein the GPU is mounted on the substrate in a flip chip
configuration on a side of the substrate opposite the memory
components, and wherein the GPU includes a heat conduction surface
configured for an attachment to the PCB interface of the printed
circuit board for conducting heat from the GPU through the
attachment, and wherein the GPU has a ball grid array for mounting
on the substrate.
12. The package of claim 11 wherein the GPU is mounted on the
substrate coplanar with a solder ball plane of the common interface
to implement the attachment to the PCB interface of the printed
circuit court.
13. The package of claim 11 wherein the attachment is implemented
using solder.
14. The device of claim 11 wherein the memory components are
surface mounted on the substrate.
15. The device of claim 11 wherein the memory components are
configured to receive a heat spreader to conduct heat from the
memory components.
Description
[0001] This application is a Divisional Application of U.S. patent
application Ser. No. 12/005,818 filed on Dec. 28, 2007, which is
incorporated herein in its entirety.
FIELD OF THE INVENTION
[0002] The field of the present invention pertains to electronic
integrated circuits. More particularly, the present invention
relates to printed circuit board devices.
BACKGROUND OF THE INVENTION
[0003] Digital computer systems are being used today to perform a
wide variety of tasks. Many different areas of business, industry,
government, education, entertainment, and most recently, the home,
are tapping into the enormous and rapidly growing list of
applications developed for today's increasingly powerful computer
devices.
[0004] Modern computer systems usually feature powerful digital
processor integrated circuit devices. The processors are used to
execute software instructions to implement complex functions, such
as, for example, 3-D graphics applications, voice recognition, data
visualization, and the like. The performance of many these
applications is directly benefited by more powerful, more capable
processors. Additionally, powerful modern computer systems have
decreased in cost such that they are more available to an average
user than ever before.
[0005] A primary characteristic of the increasing power of modern
computer systems and their decreasing cost is the steady progress
of integrated circuit device manufacturing technologies. Modern
semiconductor manufacturing technologies lead to increasing levels
of integration, increasing power, and decreasing cost of the
computer devices (e.g., laptop computer systems, desktop computer
systems, workstations, servers, etc.).
[0006] Computer system device manufacturers have discovered that
compact size is a desirable market trait. Typically, the more
compact a device is, the lower its costs of manufacture.
Additionally, compact size (e.g., increasing integration) yields a
number of other benefits, such as decreased power consumption and
increased portability. Accordingly, a primary objective of many
computer system device manufacturers is to reduce the form factor
of a given device while maintaining, or even increasing, the
performance of the device.
[0007] The objective of reducing computer system device form factor
has led to several prior art integrated circuit packaging schemes.
One prior art packaging scheme involves the implementation of
multichip modules. A multichip module, or MCM, refers to a chip
package that contains two or more "raw" chips closely connected
with high-density lines, or signal traces embedded within, or on,
the package. A raw chip generally refers to a semiconductor
integrated circuit die without its associated packaging. The raw
chips are typically mounted directly on or embedded within a base.
A prior art MCM implementation saves space and can, in some cases,
speed processing due to short leads between chips (e.g., in
comparison to several discrete chips mounted conventionally on a
printed circuit board). A ceramic base is typically used with chips
wire bonded together (MCM-C) or with deposited thin film
interconnects (MCM-D). MCMs have been mounted onto silicon
substrates (MCM-S) and resin-based, laminated printed circuit
boards (MCM-L), the latter, less-costly version evolving into the
multichip package (MCP).
[0008] Another prior art packaging scheme involves the
implementation of multichip packages. A multichip package, or MCP,
refers to a chip package that contains two or more packaged chips,
as opposed to raw chips. It is essentially an MCM that uses a
laminated, printed circuit board-like substrate (MCM-L) rather than
ceramic (MCM-C).
[0009] However, there are a number of problems with the above prior
art packaging implementations. With both MCMs and MCPs, it is very
difficult to route signal traces through the base or the substrate.
For example, modern processor integrated circuit dies can have 500
or more interconnects which need to be coupled and routed through
the substrate. In an MCM or MCP having a number of such dies, the
routing problem can be very substantial.
[0010] Other problems arise from the increasing complexity forced
upon the design of the substrate. The routing problem causes the
design of the substrate to be much more complex. For example, to
route thousands of different traces, many substrates are
implemented in multiple layers and implement signal traces in a
tightly packed manner, which can, in turn, cause another set of
problems (e.g., crosstalk, uneven path delay, etc.). Additionally,
highly complex substrates are difficult to manufacture. For
example, high-performance MCMs mounting multiple chips have very
tight manufacturing tolerances. The tight tolerances decrease the
yield and reliability of the MCM. This increases the cost of the
resulting computer system device. Another factor that increases
cost is the use of raw chips. The raw chips must typically be
mounted on the substrate and the device essentially finished prior
to testing. Thus, it is difficult to detect defective dies prior to
device completion. This reduces the overall yield of the device
fabrication process.
[0011] Another problem with prior art MCM and MCP packaging
implementations is the fact that with compactly packaged MCM/MCP
devices, it becomes very difficult to manage heat dissipation. It
is more difficult to effectively remove heat from the multiple
chips. Additionally, the device can be thermally unbalanced wherein
heat can spread from "hot" components to "cool" components,
affecting their performance and reliability. Also, substrates and
ceramic bases of devices are not a very good heat conductors.
Consequently, prior art MCM/MCP devices can require complex heat
sink apparatuses to maintain high performance levels. Most of the
waste heat is required to transfer into the ambient air (e.g.,
requiring heat pipes, high air flow, noisy fans, etc.). As
component packaging density increases and clock speed increases,
the thermal energy that must be dissipated also increases. To
maintain high-performance, a stable operating temperature must
maintained. Accordingly, high performance prior art MCM/MCP devices
must be configured for use with elaborate heat dissipation devices
(e.g., heat sink fans, liquid cooling, heat spreaders, etc.). This
increases the size of the overall package and can counteract a
primary benefit of using an MCM/MCP design.
[0012] Thus, what is required is a solution that efficiently
packages multiple integrated circuit components while maintaining
cost effective packaging specifications. What is required is a
solution that evidences favorable yield and performance
characteristics along with a small package footprint.
SUMMARY OF THE INVENTION
[0013] Embodiments of the present invention provide a
multi-configuration processor-memory device having a standardized
interface for coupling to a printed circuit board. Embodiments of
the present invention provide a solution that efficiently packages
multiple integrated circuit components while maintaining cost
effective packaging specifications. Additionally, embodiments of
the present invention provide favorable yield and performance
characteristics along with a small package footprint.
[0014] In one embodiment, the present invention is implemented as a
Multi-configuration Processor-Memory device for coupling to a PCB
interface of a printed circuit board. The device comprises a
substrate that supports multiple configurations of memory
components and a processor while having a single, common interface
for connecting to an interface area of a printed circuit board
(e.g., in one embodiment, a solder pad array disposed on the
surface of the printed circuit board). In a first configuration,
the substrate supports a processor and a first number of memory
components. In a second configuration, the substrate supports a
processor and an additional number of memory components (e.g., four
or more memory chips). The memory components can be pre-tested,
packaged memory components mounted on the substrate. The processor
can be a surface mounted (or wire bonded) processor die.
Additionally, the processor can be mounted in a flip chip
configuration, side-opposite the memory components. In the first
configuration (processor and memory components on the same side of
the substrate), a heat spreader can be mounted on the memory
components and the processor to dissipate heat. In the second, flip
chip, configuration (processor and memory components on opposite
sides of the substrate), the processor face can be soldered onto a
non-electrically functional area of the PCB interface of the
printed circuit board to dissipate heat and on the opposite side a
heat spreader would simply dissipate heat for the memory components
only.
[0015] In one embodiment, depending upon the specific
configuration, the processor can be a GPU (graphics processing
unit) and the memory components can be DDR (double data rate)
memory components. The GPU can be a bare die mounted on the
substrate, while the memory components are pretested, packaged
memory components mounted on the substrate.
[0016] In another embodiment, the multi-configuration
processor-memory device includes a heat spreader coupled to the
memory components to conduct heat from the memory components
independent of heat from a GPU. The GPU is mounted on the substrate
in a flip chip configuration on a side of the substrate opposite
the memory components. In this embodiment, the GPU includes a heat
conduction surface configured for attaching to a heat sink, wherein
the heat sink is configured to protrude through an opening of the
printed circuit board and conduct heat from the GPU through the
opening to a side of the printed circuit board opposite the GPU
device, thereby providing a robust heat conduction path for the GPU
that is independent of the heat spreader of the memory
components.
[0017] In this manner, embodiments of the present invention
implement a processor-memory device having a compact size and small
form factor, resulting in lower manufacturing cost and much smaller
application footprint. High-performance can be maintained since
thermal dissipation from the memory components and the processor is
decoupled, allowing higher clock speeds and more uniform heat
dissipation. Additionally, the use of pre-tested, prepackaged
memory components increases yield of the device fabrication
process.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The present invention is illustrated by way of example, and
not by way of limitation, in the figures of the accompanying
drawings and in which like reference numerals refer to similar
elements and in which:
[0019] FIG. 1 shows a first configuration and a second
configuration of a processor-memory device in accordance with one
embodiment of the present invention.
[0020] FIG. 2 shows a side view of the first configuration
(configuration A) and the second configuration (configuration B) of
the multi-configuration processor-memory device in accordance with
one embodiment of the present invention.
[0021] FIG. 3A shows a side view of the substrate of configuration
B with respect to the common PCB interface of a PCB (printed
circuit board) in accordance with one embodiment of the present
invention.
[0022] FIG. 3B shows a top down view of the common PCB interface in
accordance with one embodiment of the present invention.
[0023] FIG. 4 shows a close-up side view of the solder
interconnections between substrate and the common PCB interface in
accordance with one embodiment of the present invention.
[0024] FIG. 5A shows a first side view of the solder interactions
between the substrate, the flip-chip mounted processor, and the
common PCB interface in accordance with one embodiment of the
present invention.
[0025] FIG. 5B shows a second side view of a PCB showing the
relationship between a plurality of solder paste depositions and a
plurality of solder balls in accordance with one embodiment of the
present invention.
[0026] FIG. 6 shows a side view of an alternative embodiment
wherein the solder balls are used for electrical interconnections
and wherein an adhesive layer is used to attach the processor to
the nonfunctional area of the common PCB interface.
[0027] FIG. 7 shows the solder pads of the nonfunctional area of
the common PCB interface disposed in a grid-like fashion in
accordance with one embodiment of the present invention.
[0028] FIG. 8 shows a side view of the grid on the surface of the
nonfunctional area in accordance with one embodiment of the present
invention.
[0029] FIG. 9 shows a side view of the solder balls and the grid on
the surface of the nonfunctional area in accordance with one
embodiment of the present invention.
[0030] FIG. 10 shows a processor-memory device implementation in
accordance with an alternative embodiment of the present invention,
wherein a flip-chip configuration of the processor-memory device is
mounted to a heat sink that is designed to attach to the processor
through an opening within a PCB.
DETAILED DESCRIPTION OF THE INVENTION
[0031] Reference will now be made in detail to the preferred
embodiments of the present invention, examples of which are
illustrated in the accompanying drawings. While the invention will
be described in conjunction with the preferred embodiments, it will
be understood that they are not intended to limit the invention to
these embodiments. On the contrary, the invention is intended to
cover alternatives, modifications and equivalents, which may be
included within the spirit and scope of the invention as defined by
the appended claims. Furthermore, in the following detailed
description of embodiments of the present invention, numerous
specific details are set forth in order to provide a thorough
understanding of the present invention. However, it will be
recognized by one of ordinary skill in the art that the present
invention may be practiced without these specific details. In other
instances, well-known methods, procedures, components, and circuits
have not been described in detail as not to unnecessarily obscure
aspects of the embodiments of the present invention.
[0032] Embodiments of the present invention provided a
multi-configuration processor-memory device having a standardized
interface for coupling to a printed circuit board. Embodiments of
the present invention provide a solution that efficiently packages
multiple integrated circuit components while maintaining cost
effective packaging specifications. Additionally, embodiments of
the present invention provide favorable yield and performance
characteristics along with a small package footprint.
[0033] FIG. 1 shows a first configuration and a second
configuration of a processor-memory device in accordance with one
embodiment of the present invention. As shown in FIG. 1, the first
configuration, configuration A, includes a processor 130 and a
plurality of memory components 121-124 mounted on a substrate 110.
The second configuration, configuration B, includes a processor 150
and a plurality of memory components 141-142 mounted on a substrate
120. Configuration A and configuration B are both designed to mount
on a common PCB interface 160.
[0034] Referring still FIG. 1, embodiments of the present invention
are designed to utilize a configurable substrate that is adapted to
support multiple combinations and mounting configurations of
processors and memory components while still maintaining a common
interface to, for example, an interface area of a printed circuit
board (e.g., motherboard, etc.). As shown in FIG. 1, configuration
A has four memory components 121-124 and a single processor 130.
Configuration B has 2 memory components 141-142 and a single
processor 150. Both configurations utilize a common substrate
interface that is designed to couple to the common PCB interface
160. It should be noted that embodiments can be configured to
support other combinations of memory components and processor
(e.g., one processor and one memory component, eight memory
components, 16 memory components, etc.).
[0035] In one embodiment, the memory components 121-124 and 141-142
are prepackaged memory components. As used herein, prepackaged
memory components refer to memory components that are not bare
dies, or raw chips. The memory components are packaged in the
conventional fashion and are tested prior to being mounted on the
substrate 110 or the substrate 120. The use of prepackaged
pre-tested memory components increases the yield of the overall
device fabrication process in comparison to prior art MCM or MCP
devices, which utilize raw chips. Additionally, the use of
prepackaged memory components simplifies their acquisition process.
For example: prepackaged memory components can be purchased from a
greater number of vendors, providing better flexibility with
respect to price and/or quality.
[0036] In the configuration A and B embodiments shown in FIG. 1,
the memory components are surface mounted on the substrate 110 or
120. In configuration B, the processor 150 is surface mounted on
the substrate 120 along with the memory components. In
configuration A, the processor 130 is mounted on the substrate 110
in a flip-chip configuration, as shown by the dotted lines showing
the outline of the processor 130.
[0037] In one embodiment, the processors 130 and 140 are GPUs
(graphics processor units). In other embodiments, the processors
130 and 140 are other types of processors, such as, for example,
DSPs (digital signal processors), CPUs (central processing units),
or the like. Similarly, in one embodiment, the memory components
121-124 and 141-142 are DDR memory components. In other
embodiments, the memory components 121-124 and 141-142 are other
types of memory components, such as, for example, RDRAM memory
components, SDRAM memory components, or the like.
[0038] FIG. 2 shows a side view of configuration A and B of the
multi-configuration processor-memory device in accordance with one
embodiment of the present invention. As shown in FIG. 2, in
configuration B, the processor 150 is surface mounted on the same
side of the substrate 120. In configuration A, the processor 130 is
mounted on the substrate 110 in a flip-chip configuration. In
configuration A, the memory components 121-124 are surface mounted
on the substrate while the processor 130 is flip-chip mounted on
the side of the substrate opposite the memory components.
[0039] The flip-chip mounting of the processor 130 in configuration
A provides an increased component density and smaller form factor.
By flip-chip mounting the processor 130 on the side opposite the
memory components, an additional number of memory components can be
included within the same form factor. Similarly, for a given number
of components, a smaller form factor can be implemented, having a
smaller application footprint. The smaller form factor and
increased component density leads to reduced manufacturing costs.
Additionally, the flip chip configuration of the processor 130
simplifies the signal trace routing implementation for the
substrate.
[0040] The flip-chip mounting of the processor 130 in configuration
A allows the processor 130 to be cooled independently of the memory
components 121-124. For example, the memory components 121-124 can
be coupled to their own respective heat spreader or heat sink
device. The processor 130 on the opposite side of the substrate 110
can utilize its own heat dissipation mechanism. This feature
described in greater detail in FIG. 5A below.
[0041] FIG. 3A shows a side view of the substrate 120 of
configuration B with respect to the common PCB interface 160 of a
PCB (printed circuit board) 170. As described above, both
configurations of the processor-memory device of the present
embodiment include an interface designed to couple to the common
PCB interface 160. The common PCB interface 160 functions by
providing the electrical interconnection to the PCB 170. The
attachment between the interface of substrate 120 and the common
PCB interface 160 is typically implemented using solder. The common
PCB interface can comprise a solder pad array for accepting solder
interconnections with the substrate 120.
[0042] It should be noted that in this embodiment, the common PCB
interface 160 is shown being generally flush with, or the same
height as, the surface of the PCB 170. In other embodiments, the
common PCB interface 160 can be at a different height than the
surface of the PCB 170, for example, slightly raised with respect
to the surface of the PCB 170 as shown in FIG. 5A and FIG. 6
below.
[0043] FIG. 3B shows a top down view of the common PCB interface
160 in accordance with one embodiment of the present invention. As
shown in FIG. 3B, the common PCB interface 160 includes a solder
pad array for accepting a plurality of solder interconnections
(e.g., hundreds of interconnections) of the processor-memory
device. In this embodiment, the common PCB interface 160 includes a
nonfunctional area 165 located at the center of the solder pad
array. The nonfunctional area 165 refers to the fact that there are
no solder pad interconnections in this area which are electrically
active or used by components on the PCB 170.
[0044] FIG. 4 shows a close-up side view of the solder
interconnections between substrate 120 and the common PCB interface
160 of the PCB 170 in accordance with one embodiment of the present
invention. As known by those skilled in the art, a plurality of
solder interconnections 401 (e.g., solder balls 401) are used to
couple the interface of substrate 120 to the solder pads of the
common PCB interface 160. Once the solder interconnections are
made, there remains a discrete distance 410 between the substrate
120 and the common PCB interface 160. In a typical implementation,
the distance 410 is approximately 500 microns. This distance is
sufficient to accommodate a flip chip mounted processor
configuration as shown below in FIG. 5A.
[0045] FIG. 5A shows a side view of the solder interactions between
the substrate 110, the flip-chip mounted processor 130, and the
common PCB interface 160 in accordance with one embodiment of the
present invention. FIG. 5A shows the solder interconnection of a
configuration A embodiment of the processor-memory device.
[0046] In this embodiment, the plurality of solder balls 401 are
used to connect the interface of the substrate 110 to the common
PCB interface 160 in a manner similar to the connection between
substrate 120 and common PCB interface 160 described above in FIG.
4. However, in addition to the solder balls 401 implementing
electrical interconnections between the interface and the common
PCB interface 160, a solder paste deposition (e.g., shown in
greater detail in FIG. 5B below) also attaches the surface of the
processor 130 to the nonfunctional area 165 of the common PCB
interface 160. In this embodiment, the surface of the processor 130
is soldered directly to the nonfunctional area 165 to provide a
heat conduction path, thereby enabling heat to be conducted
directly away from the processor 130 into the common PCB interface
160 and the PCB 170.
[0047] In this manner, a surface of the processor 130 is configured
for an attachment to the PCB interface 160 of the print circuit
board in order to conduct heat from the processor through the
attachment. In this embodiment, the attachment is a solder
attachment. The distance 410 (e.g., approximately 500 microns)
provides more than sufficient room between the interface of the
substrate 110 and the PCB interface 160 for the flip-chip mounted
processor 130, since the processor typically protrudes from the
surface of the substrate 110 by approximately 350 microns.
[0048] The solder attachment shown in FIG. 5A allows the re-flowed
solder paste to conduct most of the heat from the processor 130
directly into the PCB 170. This provides a heat conduction path for
the processor 130 independent of the memory components. The
independent heat conduction paths thermally decouple the memory
components from processor allowing separate heat dissipation paths,
therefore resulting in more uniformly controlled low junction
temperatures in all the mounted integrated circuit devices.
Additionally, the PCB interface 160 is shown in FIG. 5A and FIG. 6
as being slightly raised above the surface of the PCB 170, in
comparison to the flush, co-planar arrangement depicted in FIG.
3A.
[0049] FIG. 5B shows a side view of the PCB 170 showing the
relationship between a plurality of solder paste depositions 502
and the solder balls 401 in accordance with one embodiment of the
present invention. In the embodiment depicted in FIG. 5B, solder
paste depositions 502 are used to implement the attachment to the
processor 130. Upon re-flow, the solder attachment shown in FIG. 5A
is created from the solder paste depositions 502. In one
embodiment, the solder balls 401 are typically standard size 0.63
mm solder balls. The FIG. 5B embodiment also shows a plurality of
thermal vias 501 embedded within the PCB 501 to conduct heat away
from the attachment to the processor 130.
[0050] FIG. 6 shows a side view of an alternative embodiment
wherein the solder balls 401 are used for electrical
interconnections and wherein an adhesive layer 601 is used to
attach the processor 130 to the nonfunctional area 165 of the
common PCB interface 160. The embodiment depicted in FIG. 6 is
substantially similar to the embodiment shown in FIG. 5A, except a
thermal adhesive layer 601 is used to attach a surface of the
processor 130 and thereby implement a heat conduction path, as
opposed to solder. As with the embodiment shown in FIG. 5A, the
thermal adhesive layer 601 provides the independent heat conduction
path for the processor 130.
[0051] FIG. 7, FIG. 8, and FIG. 9 show more detailed views of the
nonfunctional area 165 of the common PCB interface 160 in
accordance with one embodiment of the present invention. As
depicted in FIG. 7, the solder pads of the nonfunctional area 165
are disposed in a grid-like fashion. In this embodiment, the grid
is implemented to prevent the solder balls 401, used to connect the
surface of the processor 130, from spreading and possibly detaching
from the surface of the processor 401.
[0052] Referring to FIG. 8, a side view of the grid on the surface
of the nonfunctional area 165 is shown. FIG. 8 also shows a surface
131 of the processor 130 that is configured to attach to the
nonfunctional area 165. In one embodiment, the surface 131 is a
metalized surface (e.g., copper, etc.), or heat conduction surface,
adapted to facilitate the conduction of heat away from the
processor 130. Alternatively, the surface 131 can be a bare die
surface.
[0053] Referring to FIG. 9, a side view of the solder balls 401 and
the grid on the surface of the nonfunctional area 165 is shown. As
described above, the grid is implemented to prevent solder balls
401 from spreading and possibly detaching from the surface 131 of
the processor 130. The "ridges" of the grid extend upwards
approximately 20 to 30 microns from the surface of the area
165.
[0054] In one embodiment, the grid is implemented using a
"solder-mask" material. The solder mask material can be applied to
the surface of the nonfunctional area 165, and thereby implement
the grid pattern, during the same manufacturing step as other
solder mask features are implemented on the surface of the PCB 170.
The material comprising the grid can be a polymer material as used
in a typical SMOBC (solder mask over bare copper) process.
Alternatively, in another embodiment, the grid can be implemented
by etching the surface (e.g., copper) of the nonfunctional area
165.
[0055] FIG. 10 shows a processor-memory device implementation in
accordance with an alternative embodiment of the present invention.
In this embodiment, a flip-chip configuration (e.g., configuration
A) of the processor-memory device is mounted to a heat sink 1025
that is designed to attach to the processor 130 through an opening
(e.g., hole) within a PCB 1070.
[0056] In this embodiment, the multi-configuration processor-memory
device includes a heat spreader 1020 coupled to the memory
components to conduct heat from the memory components independent
of heat from the processor 130. The processor 130 is mounted on the
substrate in a flip-chip configuration on a side of the substrate
opposite the memory components. In this embodiment, the processor
130 includes a heat conduction surface configured for attaching to
the heat sink 1025. The heat sink 1025 is configured to protrude
through an opening of the 1070 and conduct heat from the processor
130 through the opening to a side of the PCB 1070 opposite the
processor 130 device, thereby conducting heat away from the
processor 130 in a manner independent of the memory components
(which use the heat spreader 1020). The surface of the processor is
mounted to the heat sink 1025 as opposed to the nonfunctional area
165 of the common PCB interface 160. The electrical
interconnections of the common PCB interface 160 would be disposed
along the periphery of the opening within the PCB 1070.
[0057] This embodiment provides the advantage of a very robust heat
transfer device (e.g., heat sink 1025) coupled to the processor
130. This allows the processor 130 to generate a much greater
amount heat than otherwise possible, thereby allowing higher clock
speeds, greater performance, and the like. The heat sink 1025 can
optionally include a fan to increase airflow, thereby dissipating
an even greater amount heat from the processor 130.
[0058] Thus, embodiments of the present invention provide a
multi-configuration processor-memory device having a standardized
interface for coupling to a printed circuit board. Embodiments of
the present invention provide a solution that efficiently packages
multiple integrated circuit components while maintaining cost
effective packaging specifications. Additionally, embodiments of
the present invention provide favorable yield and performance
characteristics along with a small package footprint. High
performance can be maintained since thermal dissipation from the
memory components and the processor is decoupled, allowing higher
clock speeds and more uniform heat dissipation. Additionally, the
use of pre-tested prepackaged memory components increases yield of
the device fabrication process.
[0059] The foregoing descriptions of specific embodiments of the
present invention have been presented for purposes of illustration
and description. They are not intended to be exhaustive or to limit
the invention to the precise forms disclosed, and obviously many
modifications and variations are possible in light of the above
teaching. The embodiments were chosen and described in order to
best explain the principles of the invention and its practical
application, to thereby enable others skilled in the art to best
utilize the invention and various embodiments with various
modifications as are suited to the particular use contemplated. It
is intended that the scope of the invention be defined by the
claims appended hereto and their equivalents.
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