U.S. patent application number 12/247378 was filed with the patent office on 2010-04-08 for systems and methods for memory efficient signal and noise estimation.
This patent application is currently assigned to LSI Corporation. Invention is credited to Scott M. Dziak, Yuan Xing Lee, George Mathew, David L. Parker, Hongwei Song.
Application Number | 20100088357 12/247378 |
Document ID | / |
Family ID | 42076638 |
Filed Date | 2010-04-08 |
United States Patent
Application |
20100088357 |
Kind Code |
A1 |
Mathew; George ; et
al. |
April 8, 2010 |
Systems and Methods for Memory Efficient Signal and Noise
Estimation
Abstract
Various embodiments of the present invention provide systems and
methods for estimating signal and noise powers in a received signal
set. For example, one embodiment of the present invention provides
a method for determining signal power and noise power. The method
uses a storage medium that includes a N.sub.a.times.N.sub.w data
pattern. The N.sub.a.times.N.sub.w data pattern includes N.sub.a
bits repeated N.sub.w times. Both N.sub.a and N.sub.w are each
greater than one. The methods further include performing an initial
read of the N.sub.a.times.N.sub.w data pattern, which is stored to
a first register. N.sub.r subsequent reads of the
N.sub.a.times.N.sub.w data pattern are each processed by:
performing a subsequent read of the N.sub.a.times.N.sub.w data
pattern, and performing a difference calculation using the initial
read of the N.sub.a.times.N.sub.w data pattern and the subsequent
read of the N.sub.a.times.N.sub.w data pattern and resulting in the
calculation of a difference vector that is stored to a second
register; and performing a difference accumulation calculation to
generate an accumulation vector which is stored to a third
register. Based at least in part on the stored
N.sub.a.times.N.sub.w data pattern and the stored difference
vector, an electronics noise power is calculated.
Inventors: |
Mathew; George; (San Jose,
CA) ; Lee; Yuan Xing; (San Jose, CA) ; Song;
Hongwei; (Longmont, CO) ; Parker; David L.;
(Firestone, CO) ; Dziak; Scott M.; (Fort Collins,
CO) |
Correspondence
Address: |
Hamilton,DeSanctis & Cha (LSI)
8601 W. CROSS DRIVE, F5-301
LITTLETON
CO
80123
US
|
Assignee: |
LSI Corporation
|
Family ID: |
42076638 |
Appl. No.: |
12/247378 |
Filed: |
October 8, 2008 |
Current U.S.
Class: |
708/445 ;
708/620; 708/670 |
Current CPC
Class: |
H04B 17/26 20150115;
H04B 17/327 20150115 |
Class at
Publication: |
708/445 ;
708/670; 708/620 |
International
Class: |
G06F 7/38 20060101
G06F007/38 |
Claims
1. A storage device, the storage device comprising: a storage
medium, wherein the storage medium includes a N.sub.a.times.N.sub.w
data pattern, wherein the N.sub.a.times.N.sub.w data pattern
includes N.sub.a bits repeated N.sub.w times, and wherein N.sub.a
and N.sub.w are each greater than one; a signal and noise
estimation circuit, wherein the signal and noise estimation circuit
includes: a first register, wherein the first register has a
capacity less than N.sub.a*N.sub.w; a second register, wherein the
second register uses a capacity less than N.sub.a*N.sub.w+1, and
wherein data included in the second register is derived from data
from the first register; a noise power calculation circuit, wherein
the noise power calculation circuit calculates a noise power based
on data from the second register; and a signal power calculation
circuit, wherein the signal power calculation circuit calculates a
signal power based on data from the first register.
2. The storage device of claim 1, wherein the signal and noise
estimation circuit further includes: a third register, wherein data
included in the third register is derived from data from the second
register; and wherein the noise power calculation circuit
calculates the noise power based on data from the second register
and the third register.
3. The storage device of claim 2, wherein the N.sub.a.times.N.sub.w
data pattern is read N.sub.r times, and wherein the third register
has a capacity of less than N.sub.a*N.sub.w*N.sub.r.
4. The storage device of claim 2, wherein the signal and noise
estimation circuit further includes: a fourth register, wherein the
fourth register includes data derived from the third register, and
wherein the fourth register has a capacity less than
N.sub.a*N.sub.w; wherein the noise power includes an electronics
noise power and a media noise power, wherein the electronics noise
power is calculated based on data from the second register and the
third register, and wherein the media noise power is calculated
based on data from the third register and the fourth register.
5. The storage device of claim 2, wherein the first register holds
a first read samples, wherein the second register holds an
accumulated read difference, and wherein the third register holds a
read average.
6. The storage device of claim 1, wherein the signal and noise
estimation circuit further includes: a signal to noise ratio
calculation circuit, wherein the signal to noise calculation
circuit provides a signal to noise ratio output calculated based on
the noise power and the signal power.
7. A method for determining signal power and noise power, the
method comprising: (a) providing a storage medium, wherein the
storage medium includes a N.sub.a.times.N.sub.w data pattern,
wherein the N.sub.a.times.N.sub.w data pattern includes N.sub.a
bits repeated N.sub.w times, and wherein N.sub.a and N.sub.w are
each greater than one; (b) performing an initial read of the
N.sub.a.times.N.sub.w data pattern; (c) storing the first N.sub.a
samples of the N.sub.a.times.N.sub.w data pattern to a first
register; (d) performing a subsequent read of the
N.sub.a.times.N.sub.w data pattern; (e) performing a difference
calculation using the initial read of the N.sub.a.times.N.sub.w
data pattern and the subsequent read of the N.sub.a.times.N.sub.w
data pattern, wherein a difference vector is generated; (f) storing
the resulting difference vector to a second register; (g)
performing a difference accumulation calculation, wherein an
accumulation vector is generated; (h) storing the resulting
accumulation vector to a third register; (i) repeating elements (d)
through (h ) for N.sub.r reads; and (j) calculating an electronics
noise power using the stored N.sub.a.times.N.sub.w accumulation
vector and the stored difference vector.
8. The method of claim 7, wherein the first register has a capacity
of less than N.sub.a*N.sub.w, and wherein the second register and
the third register each have a capacity of approximately
N.sub.a*N.sub.w.
9. The method of claim 7, wherein performing the difference
calculation is done in accordance with the following equation:
e[k,l,m]=x[k,l,m]-x[k,1,1], for k1, 2, . . . , N.sub.a and l=1, 2,
. . . , N.sub.w; and wherein x[k,1,1] indicates the stored
N.sub.a.times.1 vector of samples.
10. The method of claim 9, wherein the difference accumulation
calculation is done in accordance with the following equation:
F.sub.m[k,l]=F.sub.m-1[k,l]+e[k,l,m], for k1, 2, . . . , N.sub.a
and l=1, 2, . . . , N.sub.w; wherein m indicates a particular read
instance, and wherein F.sub.m-1[k,l] is a previously calculated
accumulation vector corresponding to another read instance.
11. The method of claim 10, wherein the electronics noise power is
calculated in accordance with the following equation: P ele = 1 N a
N w N r 2 k = 1 Na l = 1 Nw ( N r * e [ k , l , N r ] - F Nr [ k ,
l ] ) 2 , ##EQU00035## and wherein e[k,l,N.sub.r] indicates the
difference vector and F.sub.Nr[k,l] indicates the accumulation
vector.
12. The method of claim 9, wherein the difference accumulation
calculation is done in accordance with the following equation: E m
[ k , l ] = e [ k , l , m ] + m - 1 m ( E m - 1 [ k , l ] - e [ k ,
l , m ] ) , for k = 1 , 2 , , N a and l = 1 , 2 , , N w . ;
##EQU00036## wherein m indicates a particular read instance, and
wherein E.sub.m-1[k,l] is a previously calculated accumulation
vector corresponding to another read instance.
13. The method of claim 12, wherein the electronics noise power is
calculated in accordance with the following equation: P ele = 1 N a
N w k = 1 Na l = 1 Nw ( e [ k , l , N r ] - E Nr [ k , l ] ) 2 ,
##EQU00037## and wherein e[k,l,N.sub.r] indicates the difference
vector and E.sub.Nr[k,l] indicates the accumulation vector.
14. The method of claim 7, the method further comprising:
calculating an interim value vector based on the accumulation
vector.
15. The method of claim 14, wherein the method further comprises:
calculating a media noise power based at least in part on the
stored accumulation vector and the interim value vector.
16. The method of claim 15, wherein the method further comprises:
calculating a signal power based at least in part on the interim
value vector and N.sub.a samples from the first read.
17. The method of claim 14, wherein the interim value vector is
calculated in accordance with the following equation: I [ k ] = 1 N
w l 1 = 1 Nw A Nr [ k , l 1 ] , for k = 1 , 2 , , N a ;
##EQU00038## and wherein A.sub.Nr[k,l.sub.1] indicates the stored
accumulation vector.
18. The method of claim 17, wherein the media power is calculated
in accordance with the following equation: P med = 1 N a N w k = 1
Na ( E Nr [ k , l ] - I [ k ] ) 2 , ##EQU00039## and wherein I[k]
indicates the interim value vector and E.sub.Nr[k,l] indicates the
accumulation vector.
19. The method of claim 17, wherein the media power is calculated
in accordance with the following equation: P med = 1 N a N w 3 N r
2 k = 1 Na l = 1 Nw ( N w * F Nr [ k , l ] - I [ k ] ) 2 ,
##EQU00040## and wherein I[k] indicates the interim value vector
and F.sub.Nr[k,l] indicates the accumulation vector.
20. The method of claim 17, wherein the method further comprises:
calculating a signal power based at least in part on the interim
value vector and the Na samples, wherein the signal power is
calculated in accordance with the following equation: P sig = 1 N a
k = 1 Na ( [ k ] + x [ k , 1 , 1 ] ) 2 , ##EQU00041## and wherein
I[k] indicates the interim value vector and x[k,1,1] indicates the
stored N.sub.a.times.1 vector of samples.
21. A system for computing signal power and noise power, the system
comprising: a storage medium, wherein the storage medium includes a
N.sub.a.times.N.sub.w data pattern, wherein the
N.sub.a.times.N.sub.w data pattern includes N.sub.a bits repeated
N.sub.w times, and wherein N.sub.a and N.sub.w are each greater
than one; a processor and a computer readable medium, wherein the
computer readable medium includes instructions executable by the
processor to: read the N.sub.a.times.N.sub.w data pattern from the
storage medium; calculate a signal power by summing the values of
the N.sub.a.times.N.sub.w data pattern for each N.sub.w to generate
a signal vector, and aggregating the square of the elements of the
signal vector; calculate a noise power based at least in part by
summing the square of each element of the N.sub.a.times.N.sub.w
data pattern; and calculate a signal to noise ratio by dividing the
signal power by the noise power.
Description
BACKGROUND OF THE INVENTION
[0001] The present inventions are related to systems and methods
for determining either or both signal power and noise power derived
from a received signal set.
[0002] Receiving information in a data transmission system is
effected by various noise factors and is often expressed as a ratio
of signal power to noise power. Such transmission systems may
include, for example, wireless or wired data transmission systems
where data is transferred from a transmission device to a receiving
device, and data storage systems where data is transferred to a
storage medium in a write operation and retrieved from the same
storage medium in a read operation. Knowledge of signal power and
noise power may be used in a number of aspects of such systems.
[0003] As an example, in a data storage system signal power and
noise power can be determined by writing a pattern that is x bits
long y times. The written data is then read back z times. This read
back data is stored to a memory structure where it may be later
accessed and used to perform a signal to noise ratio calculation.
Such an approach yields a reasonable estimate of signal to noise
ratio, however, it demands a large memory structure. In particular,
the memory structure would be of a size x*y*z. In many situations,
a large memory structure is impractical. To alleviate this memory
requirement, one or more of x, y and z may be reduced. As the
accuracy of the signal to noise estimate is reduced where the
number of bits used to perform the estimate, the aforementioned
approach results in a potential reduction in the accuracy of the
signal to noise estimate.
[0004] Hence, for at least the aforementioned reasons, there exists
a need in the art for advanced systems and methods for estimating
signal power, noise power and/or a combination thereof.
BRIEF SUMMARY OF THE INVENTION
[0005] The present inventions are related to systems and methods
for determining either or both signal power and noise power derived
from a received signal set.
[0006] Various embodiments of the present inventions provide
storage devices that include a storage medium with an
N.sub.a.times.N.sub.w data pattern. The N.sub.a.times.N.sub.w data
pattern includes N.sub.a bits repeated N.sub.w times. Both N.sub.a
and N.sub.w are each greater than one. The storage devices further
include a signal and noise estimation circuit with a first register
and a second register. The first register has a capacity less than
N.sub.a*N.sub.w. The second register uses a capacity less than
N.sub.a*N.sub.w+1, and data included in the second register is
derived from data from the first register. The signal to noise
estimation circuit further includes a noise power calculation
circuit that calculates a noise power based on data from the second
register, and a signal power calculation circuit that calculates a
signal power based on data from the first register.
[0007] Other embodiments of the present invention provide methods
for determining signal power and noise power. Such methods include
providing a storage medium that includes a N.sub.a.times.N.sub.w
data pattern. The N.sub.a.times.N.sub.w data pattern includes
N.sub.a bits repeated N.sub.w times. Both N.sub.a and N.sub.w are
each greater than one. The methods further include performing an
initial read of the N.sub.a.times.N.sub.w data pattern, which is
stored to a first register. N.sub.r subsequent reads of the
N.sub.a.times.N.sub.w data pattern are each processed by:
performing a subsequent read of the N.sub.a.times.N.sub.w data
pattern, and performing a difference calculation using the initial
read of the N.sub.a.times.N.sub.w data pattern and the subsequent
read of the N.sub.a.times.N.sub.w data pattern and resulting in the
calculation of a difference vector that is stored to a second
register; and performing a difference accumulation calculation to
generate an accumulation vector which is stored to a third
register. Based at least in part on the stored
N.sub.a.times.N.sub.w data pattern and the stored difference
vector, an electronics noise power is calculated.
[0008] Yet other embodiments of the present invention provide
systems for computing signal power an noise power. Such systems
include a storage medium that includes a N.sub.a.times.N.sub.w data
pattern. The N.sub.a.times.N.sub.w data pattern includes N.sub.a
bits repeated N.sub.w times. Both N.sub.a and N.sub.w are each
greater than one. The systems further include a processor and a
computer readable medium that includes instructions executable by
the processor to read the N.sub.a.times.N.sub.w data pattern from
the storage medium; calculate a signal power by summing the values
of the N.sub.a.times.N.sub.w data pattern for each N.sub.w to
generate a signal vector, and aggregating the square of the
elements of the signal vector; calculate a noise power based at
least in part by summing the square of each element of the
N.sub.a.times.N.sub.w data pattern; and calculate a signal to noise
ratio by dividing the signal power by the noise power.
[0009] This summary provides only a general outline of some
embodiments of the invention. Many other objects, features,
advantages and other embodiments of the invention will become more
fully apparent from the following detailed description, the
appended claims and the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] A further understanding of the various embodiments of the
present invention may be realized by reference to the figures which
are described in remaining portions of the specification. In the
figures, like reference numerals are used throughout several
figures to refer to similar components. In some instances, a
sub-label consisting of a lower case letter is associated with a
reference numeral to denote one of multiple similar components.
When reference is made to a reference numeral without specification
to an existing sub-label, it is intended to refer to all such
multiple similar components.
[0011] FIG. 1 depicts a storage system with a read channel
including an noise estimation capability in accordance with various
embodiments of the present invention;
[0012] FIG. 2 depicts a memory efficient signal and noise
estimation circuit in accordance with various embodiments of the
present invention;
[0013] FIG. 3 depicts a method in accordance with some embodiments
of the present invention for performing both signal and noise
estimation;
[0014] FIG. 4 depicts another memory efficient signal and noise
estimation circuit in accordance with other embodiments of the
present invention;
[0015] FIG. 5 depicts a method in accordance with various
embodiments of the present invention for performing both signal and
noise estimation;
[0016] FIG. 6 depicts a signal and noise estimation circuit in
accordance with one or more embodiments of the present invention;
and
[0017] FIG. 7 depicts a method in accordance with various
embodiments of the present invention for performing both signal and
noise estimation.
DETAILED DESCRIPTION OF THE INVENTION
[0018] The present inventions are related to systems and methods
for determining either or both signal power and noise power derived
from a received signal set.
[0019] Various embodiments of the present invention provide memory
efficient circuits capable of estimating noise power and/or signal
power in a received signal set. Where applied to a storage system,
some embodiments of the present invention are further capable of
decomposing the noise power into a media noise and electronics
noise components. In some cases, knowledge of drive level signal to
noise ratio in a storage system may be used to assess the quality
of the replay signal, to assess the quality of the recording
channel, and/or to tune one or more read channel detector
parameters.
[0020] Turning to FIG. 1, a storage system 100 is depicted
including a read channel 110 with a memory efficient noise and
signal estimation module in accordance with various embodiments of
the present invention. Storage system 100 may be, for example, a
hard disk drive. Read channel 110 may include any adaptive
pre-compensation circuitry capable of efficiently determining
pre-compensation values to be used in one or more write operations.
As an example, the memory efficient noise and signal estimation
module may be, but is not limited to, that described below in
relation to FIG. 2, FIG. 4 or FIG. 6 below. In addition, storage
system 100 includes an interface controller 120, a hard disk
controller 166, a motor controller 168, a spindle motor 172, a disk
platter 178, and a read/write head 176. Interface controller 120
controls addressing and timing of data transfer to/from disk
platter 178. Disk platter 178 may be any magnetic storage medium
known in the art including, but not limited to, a longitudinal
magnetic storage medium or a perpendicular magnetic storage medium.
The data on disk platter 178 consists of groups of magnetic signals
that may be detected by read/write head assembly 176 when the
assembly is properly positioned over disk platter 178. In a typical
read operation, read/write head assembly 176 is accurately
positioned by motor controller 168 over a desired data track on
disk platter 178. Motor controller 168 both positions read/write
head assembly 176 in relation to disk platter 178 and drives
spindle motor 172 by moving read/write head assembly to the proper
data track on disk platter 178 under the direction of hard disk
controller 166. Spindle motor 172 spins disk platter 178 at a
determined spin rate (RPMs).
[0021] Once read/write head assembly 178 is positioned adjacent the
proper data track, magnetic signals representing data on disk
platter 178 are sensed by read/write head assembly 176 as disk
platter 178 is rotated by spindle motor 172. The sensed magnetic
signals are provided as a continuous, minute analog signal
representative of the magnetic data on disk platter 178. This
minute analog signal is transferred from read/write head assembly
176 to read channel module 110. In turn, read channel module 110
decodes and digitizes the received analog signal to recreate the
information originally written to disk platter 178. This data is
provided as read data 103 to a receiving circuit. A write operation
is substantially the opposite of the preceding read operation with
write data 101 being provided to read channel module 110. This data
is then encoded and written to disk platter 178. Of note, read
channel module 110 is capable of writing information to disk
platter 178 and subsequently reading the data back. The read back
data is used to perform signal and noise estimation.
[0022] To provide a memory efficient implementation of signal and
noise estimation, the following expression for estimating the
electronics noise is utilized:
P ele = 1 N a N w k = 1 Na l = 1 Nw ( x [ k , l , N r ] - Y Nr [ k
, l ] ) 2 , and ##EQU00001## Y Nr [ k , l ] = 1 N r m = 1 Nw x [ k
, l , m ] . ##EQU00001.2##
This expression uses the electronics noise present in samples from
only one read rather than that present in all available reads.
While this substantially reduces the memory requirement, it does
not reduce the number of samples that are used in estimating
electronics noise power. As Y.sub.Nr[k,l] involves the accumulation
of analog to digital samples over all reads, the bit width needed
for the accumulation will increase as the number of reads, N.sub.r,
increases. To eliminate this dependency, the dynamic range of the
signal is reduced by calculating an error signal in accordance with
the following equation:
e[k,l,m]=x[k,l,m]-x[k,1,1].
Since the noiseless signal in x[k,l,m] is the same as that in
x[k,1,1] for all k,l and m, the difference signal, e[k,l,m],
corresponds to the noise components. Consequently, the dynamic
range of e[k,l,m] should be less than x[k,l,m]. From this, the
signal power, media noise power and electronics noise power can be
expressed as:
P ele = 1 N a N w k = 1 Na l = 1 Nw ( e [ k , l , N r ] - E Nr [ k
, l ] ) 2 , ( 1 a ) P med = 1 N a N w k = 1 Na l = 1 Nw ( E Nr [ k
, l ] - b [ k ] ) 2 , and ( 2 a ) P sig = 1 N a k = 1 Na ( b [ k ]
+ x [ k , 1 , 1 ] ) 2 , ( 3 a ) ##EQU00002##
where b[k] and E.sub.Nr[k,l] are calculated as follows:
E Nr [ k , l ] = 1 N r m = 1 Nr e [ k , l , m ] , and b [ k ] = 1 N
w l 1 = 1 Nw E Nr [ k , l 1 ] . ( 4 a ) ##EQU00003##
Of note, the electronic noise is random, and thus averages out
where a large samples set is utilized.
[0023] In one embodiment of the present invention, E.sub.Nr[k,l] is
re-written as:
E Nr [ k , l ] = 1 N r F Nr [ k , l ] , where F Nr [ k , l ] = m =
1 Nr e [ k , l , m ] . ( 5 a ) ##EQU00004##
The quantity F.sub.Nr[k,l] can be computed recursively as:
F.sub.m[k,l]=F.sub.m-1[k,l]+e[k,l,m], for m=1, 2, . . . ,
N.sub.r,
With F.sub.0[k,l]=0, for k=1, 2, . . . , N.sub.a and 1=1, 2, . . .
, N.sub.w. Based on this, the electronic noise power, the media
noise power and the signal power may be estimated by first
computing E.sub.Nr[k,l] using equation (5a) above by processing the
samples derived from N.sub.r reads. At the N.sub.r.sup.th read,
b[k] is computed from E.sub.Nr[k,l] using equation (4a) above.
Next, P.sub.ele, P.sub.med and P.sub.sig are calculated using
equations (1a-3a), respectively. The amount of memory used to
implement this approach is 2N.sub.wN.sub.a+N.sub.a. In particular,
2N.sub.wN.sub.a memory cells are used for holding F.sub.m[k,l] and
the samples from the m.sup.th read for all k and l, and N.sub.a
memory cells are used to hold x[k,1,1] (i.e., the first read). The
memory used for holding the samples from the N.sub.r.sup.th read
can be reused for holding b[k] for all k. Thus, by implementing the
aforementioned memory efficiency modification, the total memory
required is independent of the number of reads, N.sub.r.
[0024] Various modifications may be implemented to increase the
accuracy of the calculations set forth above in relation to the
currently discussed embodiment. In particular, various accumulated
quantities involve a division to achieve the average quantities
E.sub.Nr[k,l] and b[k]. For the sake of ease of implementation and
minimizing any errors due to fixed point mathematics, the algorithm
may be modified to avoid the use of division until the conclusion
of the algorithm. To do this, the quantity F.sub.Nr[k,l] is used in
place of E.sub.Nr[k,l] and b[k]. This is done by exploiting the
relationship between {E.sub.Nr[k,l],b[k]} and F.sub.Nr[k,l] as set
forth above. From this relationship, the following noise and signal
power equations are possible from modifying equations (1a-3a)
above:
P ele = 1 N a N w N r 2 k = 1 Na l = 1 Nw ( N r * e [ k , l , N r ]
- F Nr [ k , l ] ) 2 , ( 6 a ) P med = 1 N a N w 3 N r 2 k = 1 Na l
= 1 Nw ( N w * F Nr [ k , l ] - G [ k ] ) 2 , and ( 7 a ) P sig = 1
N a N w 2 N r 2 k = 1 Na ( G [ k ] + N w N r * x [ k , 1 , 1 ] ) 2
, where G [ k ] = l 1 = 1 Nw F Nr [ k , l 1 ] . ( 8 a )
##EQU00005##
[0025] Further, quantization noise (i.e., noise introduced due to
the step size of an upstream analog to digital converter) may be
compensated in some cases. Such quantization noise may become
particularly acute at higher signal to noise ratios. Compensation
for quantization noise may be accomplished by assuming noise is
stochastically independent from sample to sample. From this, it is
possible to get approximate relationship between the powers
estimated using fixed-point computations and the corresponding
powers estimated using floating-point computations. These
relationships are set forth in the following equations:
P ele .apprxeq. P _ ele + N r - 1 N r * .sigma. 0 2 , ( 9 a ) P med
.apprxeq. P _ med + N w - 1 N w N r * .sigma. 0 2 , ( 10 a ) P sig
.apprxeq. P _ sig + 1 N w N r * .sigma. 0 2 . ( 11 a )
##EQU00006##
In these, {P.sub.ele,P.sub.med,P.sub.sig} correspond to powers
estimated using fixed-point computations, and
{P.sub.ele,P.sub.med,P.sub.sig} correspond to powers estimated
using floating-point calculations. Further, .sigma..sub.0.sup.2
denotes the quantization noise power associated with quantizing
x[k,l,m]. Assuming uniform quantization,
.sigma..sub.0.sup.2=.DELTA..sub.0.sup.2/12 where .DELTA..sub.0 is
the quantization step-size. In situations where N.sub.a, N.sub.w
and N.sub.r are all reasonably large (e.g., greater than one
hundred), the estimated powers that are most affected will be
P.sub.ele. Where the analog to digital conversion range and number
of bits are known, it is possible to account for an estimate of
quantization noise.
[0026] Turning to FIG. 2, a memory efficient signal and noise
estimation module 200 is depicted. Signal and noise estimation
module 200 includes an analog to digital converter 210 that
receives an analog input 205, and provides a series of digital
samples 215 corresponding to analog input 205. Analog input 205
includes a series of bits representing the written bit patterns
(i.e., N.sub.a.times.N.sub.w) repeated by the number of times it is
re-read (i.e., N.sub.r). Digital samples 215 are generally referred
to as x[k,l,m] where k indicates the given bit in the original
pattern, l indicates the given write, and m indicates the given
read. The first read samples 217 of digital samples 215 (i.e.,
x[k,1,1]) are stored to a first read sample register 220 for use
during the calculation processes. The size of first read sample
register 220 is 1.times.N.sub.a.
[0027] Digital samples 215 and first read samples 217 are provided
to a read difference calculator circuit 230. Read difference
calculator circuit 230 calculates a sample by sample difference
between digital samples 215 and first read samples 217 for each
read set included in analog input 205 in accordance with the
following equation:
e[k,l,m]=x[k,l,m]-x[k,1,1], for k=1, 2, . . . , N.sub.a and l=1, 2,
. . . , N.sub.w. (12a)
A resulting difference vector 232, e[k,l,m], is stored to a read
difference register 235 of size 1.times.N.sub.aN.sub.w. Difference
vector 232 is provided to a read difference accumulating circuit
240 that accumulates multiple difference vectors 232 created across
the multiple reads, N.sub.r, into a two dimensional accumulation
vector 242, F.sub.m[k,l], that is stored to a read accumulate
register 245. Accumulation vector 242 is calculated in accordance
with the following equation:
F.sub.m[k,l]=F.sub.m-1[k,l]+e[k,l,m], for k=1, 2, . . . , N.sub.a
and l=1, 2, . . . , N.sub.w. (13a)
Depending upon the number of read processes (i.e., N.sub.r), the
size of read accumulate register 245 may be substantially larger
than read difference register 235 because the number of bits for
each location may increase due to the accumulation process.
Accumulation vector 242 is provided to an interim value calculator
circuit 250 that calculates an interim value vector 252 in
accordance with the following equation:
G [ k ] = l 1 = 1 Nw F Nr [ k , l 1 ] , for k = 1 , 2 , , N a . (
14 a ) ##EQU00007##
Interim value vector 252 is stored to an interim value register
255. In some cases, interim value register 255 can reuse the memory
of read difference register 235. Again, depending upon N.sub.r, the
size of interim value register 255 may be substantially larger than
N.sub.a cells of read difference register 235 because the number of
bits for each location may increase due to the accumulation
process.
[0028] Difference vector 232 and accumulation vector 242 are both
provided to an electronics noise calculator circuit 260 which
calculates electronics noise power in accordance with the following
equation:
P ele = 1 N a N w N r 2 k = 1 Na l = 1 Nw ( N r * e [ k , l , N r ]
- F Nr [ k , l ] ) 2 . ( 15 a ) ##EQU00008##
Electronics noise calculation circuit 260 provides an electronics
noise power estimate 262 to a quantization compensation circuit 265
that compensates for the quantization effect in accordance with the
following equation:
P ele .rarw. P ele - Nr - 1 Nr * .DELTA. 0 2 12 , ( 16 a )
##EQU00009##
where .DELTA..sub.0 denotes the step size used for quantizing
x[k,l,m] (i.e., the step size of analog to digital converter 210).
Quantization compensation circuit 265 provides a electronics noise
power output 267.
[0029] Accumulation vector 242 and interim value vector 252 are
both provided to a media noise calculator circuit 270 which
calculates media noise power in accordance with the following
equation:
P med = 1 N a N w 3 N r 2 k = 1 Na l = 1 Nw ( N w * F Nr [ k , l ]
- G [ k ] ) 2 . ( 17 a ) ##EQU00010##
Media noise calculation circuit 270 provides a media noise power
output 272. First read samples 217 and interim value vector 252 are
provided to a signal power calculation circuit 275 that provides a
signal power output 277 in accordance with the following
equation:
P sig = 1 N a N w 2 N r 2 k = 1 Na ( G [ k ] + N w N r * x [ k , 1
, 1 ] ) 2 . ( 18 a ) ##EQU00011##
Using outputs 267, 272, 277, a signal to noise calculation circuit
280 calculates a signal to noise ratio 282 in accordance with the
following equation:
S N R = P sig P med + P ele . ( 19 a ) ##EQU00012##
Further, signal to noise calculation circuit 280 calculates a noise
source ratio 283 in accordance with the following equation:
.alpha. = P med P med + P ele . ( 20 a ) ##EQU00013##
[0030] It should be noted that while various components of signal
and noise estimation module 200 are described as "circuits" that
they may be implemented either as an electronic circuit or as a
software/firmware circuit. Such software/firmware circuits include
a processor associated with a memory device that includes
instructions executable by the processor to perform the particular
functions described herein. Such processors may be general purpose
processors or processors specifically tailored to perform a given
function depending upon the particular implementation requirements.
In some cases, the processor may be designed to perform functions
related to more than one particular module. In some embodiments of
the present invention, signal and noise estimation module 200 is
implemented entirely as firmware or software being executed by a
processor. In other embodiments of the present invention, signal
and noise estimation module 200 is implemented entirely as a
dedicated electronic circuit. In yet other embodiments of the
present invention, signal and noise estimation module 200 is
implemented as a combination of firmware or software being executed
on a processor, and dedicated electronic circuitry. Based on the
disclosure provided herein, one of ordinary skill in the art will
recognize a variety of combinations of dedicated electronic
circuitry and software/firmware that may be used in accordance with
different embodiments of the present invention.
[0031] Turning to FIG. 3, a flow diagram 300 depicts a method in
accordance with some embodiments of the present invention for
performing both signal and noise estimation. Prior to starting the
process the quantities F.sub.0[k,l] is initialized to zero for k=1,
2, . . . , N.sub.a and l=1, 2, . . . , N.sub.w. Following flow
diagram 300, a pseudo-random bit pattern N.sub.a bits long is
prepared (block 305). The bit pattern may be generated by any
process known in the art for generating a reasonably random
pattern. The pseudo-random bit pattern is written to a storage
medium N.sub.w times (block 310) resulting in a pattern
N.sub.a.times.N.sub.w long. The multiply written bit pattern is
then read back from the storage medium (block 315). The first
N.sub.a of the read samples are stored to a register (block
320).
[0032] The multiply written bit pattern is again read back from the
storage medium (block 325), and a difference calculation is
performed for the given read (block 330). The difference
calculation is performed in accordance with equation (12a) set
forth above. An accumulation calculation is additionally performed
in accordance with equation (13a) set forth above (block 335). This
process is repeated for each read of the multiply written data set.
Thus, it is determined if the maximum number of reads have been
accomplished (block 340). If not, the read counter is incremented
(block 345) and blocks 325-340 are repeated.
[0033] Where the maximum number of reads has been processed (block
340), interim noise values are calculated for the various
accumulations in accordance with equation (14a) above (block 350).
This process is repeated for each write of the data set. Thus, it
is determined if the maximum number of writes have been
accomplished (block 355). If not, the write counter is incremented
(block 360) and blocks 350-355 are repeated.
[0034] Where the maximum number of writes has been processed (block
355), the desired interim noise value have been calculated. At this
point, electronics noise power is calculated (block 370) in
accordance with equation (15a) above, and the effect of analog to
digital quantization is mitigated in the calculated electronics
noise power (block 375) in accordance with equation (16a) above.
Further, the media noise power is calculated (block 380) in
accordance with equation (17a) above, and the signal power is
calculated (block 385) in accordance with equation (18a) above.
Using the noise power values and the signal power value, a signal
to noise ratio is calculated (block 395) in accordance with
equation (19a) above, and a noise source ratio is calculated in
accordance with equation (20a).
[0035] In another embodiment of the present invention, further
memory enhancements may be made and yet still provide reasonable
estimates of the various powers. In particular, even though the
dynamic range of the difference samples, e[k,l,m], is less than
that of the analog to digital samples, x[k,l,m] , in the foregoing
approach, the accumulators holding F.sub.m[k,l] will still overflow
where m becomes sufficiently large. Furthermore, the overflow will
occur for relatively small values of m where the signal to noise
ratio is low. In this embodiment, modifications are made to
eliminate the dependency on the value of m.
[0036] In this embodiment, the value of E.sub.Nr[k,l] is calculated
recursively using the following equation (1b):
E m [ k , l ] = 1 m m 1 = 1 m e [ k , l , m 1 ] , for m = 1 , 2 , ,
N r ; = m - 1 m E m - 1 [ k , l ] + 1 m e [ k , l , m ] ; = e [ k ,
l , m 1 ] + m - 1 m ( E m - 1 [ k , l ] - e [ k , l , m ] , ( 1 b )
##EQU00014##
where E.sub.0[k,l]=0 for k=1, 2, . . . , N.sub.a and l=1, 2, . . .
, N.sub.w. Of note, in this case E.sub.m[k,l] is normalized by m,
and thus the corresponding accumulators will not overflow dependent
upon the size of m. Based on this, the electronic noise power, the
media noise power, and the signal noise may be estimated by first
computing E.sub.Nr[k,l] using equation (1b) above by processing the
samples derived from N.sub.r reads one read at a time. At the
N.sub.r.sup.th read, b[k] is computed from E.sub.Nr[k,l] using
equation (4a) above. Next, P.sub.ele,P.sub.med and P.sub.sig are
calculated using equations (1a-3a), respectively. The amount of
memory used to implement this approach is 2N.sub.wN.sub.a+N.sub.a.
In particular, 2N.sub.wN.sub.a memory cells are used for holding
E.sub.m[k,l] and the samples from the m.sup.th read for all k and
l, and N.sub.a memory cells are used to hold x[k,1,1] (i.e., the
first read). The memory used for holding the samples from the
N.sub.r.sup.th read can be reused for holding b[k] for all k.
Again, by implementing the aforementioned memory efficiency
modification, the total memory required is independent of the
number of reads, N.sub.r. Further, the size of memory is
independent of the size of the variable m.
[0037] In some cases, quantization noise may be compensated. Such
quantization noise may become particularly acute at higher signal
to noise ratios. Compensation for quantization noise may be
accomplished by assuming noise is stochastically independent from
sample to sample. From this, it is possible to get approximate
relationship between the powers estimated using fixed-point
computations and the corresponding powers estimated using
floating-point computations. These relationships are set forth in
the following equations:
P.sub.ele.apprxeq.P.sub.ele+.sigma..sub.0.sup.2+.sigma..sub.1.sup.2,
(2b)
P.sub.med.apprxeq.P.sub.med+.sigma..sub.1.sup.2+.sigma..sub.2.sup.2,
(3b)
P.sub.sig.apprxeq.P.sub.sig+.sigma..sub.2.sup.2. (4b)
In these, {P.sub.ele,P.sub.med,P.sub.sig} correspond to powers
estimated using fixed-point computations, and
{P.sub.ele,P.sub.med,P.sub.sig} correspond to powers estimated
using floating-point calculations. Further,
{.sigma..sub.0.sup.2,.sigma..sub.1.sup.2,.sigma..sub.2.sup.2}
denote the respective quantization noise powers associated with
quantizing x[k,l,m], E.sub.m[k,l] and b[k], respectively. Assuming
uniform quantization, .sigma..sub.k.sup.2=.DELTA..sub.k.sup.2/12
where .DELTA..sub.k is the quantization step-size, for k=0, 1, 2.
In situations where N.sub.a, N.sub.w and N.sub.r are all reasonably
large (e.g., greater than one hundred), the estimated powers that
are most affected will be P.sub.ele. Where the analog to digital
conversion range and number of bits are known, it is possible to
account for an estimate of quantization noise.
[0038] Turning to FIG. 4, another memory efficient signal and noise
estimation module 400 is depicted. Signal and noise estimation
module 400 includes an analog to digital converter 410 that
receives an analog input 405, and provides a series of digital
samples 415 corresponding to analog input 405. Analog input 405
includes a series of bits representing the written bit patterns
(i.e., N.sub.a.times.N.sub.w) repeated by the number of times it is
re-read (i.e., N.sub.r). Digital samples 415 are generally referred
to as x[k,l,m] where k indicates the given bit in the original
pattern, l indicates the given write, and m indicates the given
read. The first read samples 417 of digital samples 415 (i.e.,
x[k,1,1]) are stored to a first read sample register 420 for use
during the calculation processes. The size of first read sample
register 420 is 1.times.N.sub.a.
[0039] Digital samples 415 and first read samples 417 are provided
to a read difference calculator circuit 430. Read difference
calculator circuit 430 calculates a sample by sample difference
between digital samples 415 and first read samples 417 for each
read set included in analog input 405 in accordance with the
following equation:
e[k,l,m]=x[k,l,m]-x[k,1,1], for k=1, 2, . . . , N.sub.a and l=1, 2,
. . . , N.sub.w. (5b)
A resulting difference vector 432, e[k,l,m], is stored to a read
difference register 435 of size 1.times.N.sub.aN.sub.w. Difference
vector 432 is provided to a read difference averaging circuit 440
that averages multiple difference vectors 432 created across the
multiple reads, N.sub.r, into a two dimensional accumulation vector
442, E.sub.m[k,l], that is stored to a read average register 445.
Accumulation vector 442 is calculated in accordance with the
following equation:
E m [ k , l ] = e [ k , l , m ] + m - 1 m ( E m - 1 [ k , l ] - e [
k , l , m ] ) , for k = 1 , 2 , , N a and l = 1 , 2 , , N w . ( 6 b
) ##EQU00015##
In this case, regardless of the number of reads (i.e., N.sub.r),
the size of read average register 445 is the same as read
difference register 435. Accumulation vector 442 is provided to an
interim value calculator circuit 450 that calculates an interim
value vector 452 in accordance with the following equation:
b [ k ] = 1 N w l 1 = 1 Nw E Nr [ k , l 1 ] , for k = 1 , 2 , , N a
. ( 7 b ) ##EQU00016##
Interim value vector 452 is stored to an interim value register
455. In some cases, interim value register 455 can reuse the memory
of read difference register 435. Again, regardless of the size of
m, the size of interim value register 455 is the same as N.sub.a
cells of read difference register 435.
[0040] Difference vector 432 and accumulation vector 442 are both
provided to an electronics noise calculator circuit 460 which
calculates electronics noise power in accordance with the following
equation:
P ele = 1 N a N w k = 1 Na l = 1 Nw ( e [ k , l , N r ] - E Nr [ k
, l ] ) 2 . ( 8 b ) ##EQU00017##
Electronics noise calculation circuit 460 provides an electronics
noise power estimate 462 to a quantization compensation circuit 465
that compensates for the quantization effect in accordance with the
following equation:
P ele .rarw. P ele - .DELTA. 0 2 + .DELTA. 1 2 12 , ( 9 b )
##EQU00018##
where .DELTA..sub.0 and .DELTA..sub.1 denote the step sizes used
for quantizing x[k,l,m] (i.e., the step size of analog to digital
converter 210) and E.sub.m[k,l], respectively. Quantization
compensation circuit 465 provides an electronics noise power output
467.
[0041] Accumulation vector 442 and interim value vector 452 are
both provided to a media noise calculator circuit 470 which
calculates media noise in accordance with the following
equation:
P med = 1 N a N w k = 1 Na ( E Nr [ k , l ] - b [ k ] ) 2 . ( 10 b
) ##EQU00019##
Media noise calculation circuit 470 provides a media noise power
output 472. First read samples 417 and interim value vector 452 are
provided to a signal power calculation circuit 475 that provides a
signal power output 477 in accordance with the following
equation:
P sig = 1 N a k = 1 Na ( b [ k ] + x [ k , 1 , 1 ] ) 2 . ( 11 b )
##EQU00020##
Using outputs 467, 472, 477, a signal to noise calculation circuit
480 calculates a signal to noise ratio 482 in accordance with the
following equation:
S N R = P sig P med + P ele . ( 12 b ) ##EQU00021##
Further, signal to noise calculation circuit 480 that calculates a
noise source ratio 483 in accordance with the following
equation:
.alpha. = P med P med + P ele . ( 13 b ) ##EQU00022##
[0042] It should be noted that while various components of signal
and noise estimation module 400 are described as "circuits" that
they may be implemented either as an electronic circuit or as a
software/firmware circuit. Such software/firmware circuits include
a processor associated with a memory device that includes
instructions executable by the processor to perform the particular
functions described herein. Such processors may be general purpose
processors or processors specifically tailored to perform a given
function depending upon the particular implementation requirements.
In some cases, the processor may be designed to perform functions
related to more than one particular module. In some embodiments of
the present invention, signal and noise estimation module 400 is
implemented entirely as firmware or software being executed by a
processor. In other embodiments of the present invention, signal
and noise estimation module 400 is implemented entirely as a
dedicated electronic circuit. In yet other embodiments of the
present invention, signal and noise estimation module 400 is
implemented as a combination of firmware or software being executed
on a processor, and dedicated electronic circuitry. Based on the
disclosure provided herein, one of ordinary skill in the art will
recognize a variety of combinations of dedicated electronic
circuitry and software/firmware that may be used in accordance with
different embodiments of the present invention.
[0043] Turning to FIG. 5, a flow diagram 500 depicts a method in
accordance with some embodiments of the present invention for
performing both signal and noise estimation. Prior to starting the
process the quantities E.sub.0[k,l] is initialized to zero for k=1,
2, . . . , N.sub.a and l=1, 2, . . . , N.sub.w. Following flow
diagram 500, a pseudo-random bit pattern N.sub.a bits long is
prepared (block 505). The bit pattern may be generated by any
process known in the art for generating a reasonably random
pattern. The pseudo-random bit pattern is written to a storage
medium N.sub.w times (block 510) resulting in a pattern
N.sub.a.times.N.sub.w long. The multiply written bit pattern is
then read back from the storage medium (block 515), and the first
N.sub.a samples are stored to a register (block 520).
[0044] The multiply written data pattern is again read back from
the storage medium (block 525), and a difference calculation is
performed for the given read (block 530). The difference
calculation is performed in accordance with equation (5b) set forth
above. An averaged accumulation calculation is additionally
performed in accordance with equation (6b) set forth above (block
535). This process is repeated for each read of the multiply
written data set. Thus, it is determined if the maximum number of
reads have been accomplished (block 540). If not, the read counter
is incremented (block 545) and blocks 525-540 are repeated.
[0045] Where the maximum number of reads has been processed (block
540), interim noise values are calculated for the various averaged
accumulations in accordance with equation (7b) above (block 550).
This process is repeated for each write of the data set. Thus, it
is determined if the maximum number of writes have been
accomplished (block 555). If not, the write counter is incremented
(block 560) and blocks 550-555 are repeated.
[0046] Where the maximum number of writes has been processed (block
555), the electronics noise power is calculated (block 570) in
accordance with equation (8b) above, and the effect of analog to
digital quantization is mitigated in the calculated electronics
noise power (block 575) in accordance with equation (9b) above.
Further, the media noise power is calculated (block 580) in
accordance with equation (10b) above, and the signal power is
calculated (block 585) in accordance with equation (11b) above.
Using the noise power values and the signal power value, a signal
to noise ratio is calculated (block 595) in accordance with
equation (12b) above, and a noise source ratio is calculated in
accordance with equation (13b).
[0047] In yet other embodiments of the present invention, the media
noise power is not separated from the electronics noise power. In
such cases, the estimation of signal to noise ratio can be further
simplified. To estimate the signal power and total noise power, it
is enough to write the N.sub.a length pattern N.sub.w times, and
read only once. This is because of the effect of averaging over
difference writes gets rid of electronics noise and media noise,
leaving only the signal components in the averaged data.
[0048] Let x[k,l] be the k.sup.th sample at the output of the
analog to digital converter in the l.sup.th repetition of the
sequence, for k=1, 2, . . . ,N.sub.a and l=1, 2, . . . , N.sub.w.
The approach for estimating the signal power and total noise power
includes estimating the total noise power in accordance with the
following equation:
P nse = 1 N a N w k = 1 Na l = 1 Nw ( x [ k , l ] - x ~ [ k ] ) 2 ,
( 1 c ) x ~ [ k ] = 1 N w l = 1 Nw x [ k , l ] . ( 2 c )
##EQU00023##
In this case, {tilde over (x)}[k] is an estimate of the k.sup.th
noiseless signal sample in any repetition, and x[k,l]-{tilde over
(x)}[k] is an estimate of the total noise in x[k,l]. Further, the
signal power is estimated in accordance with the following
equation:
P ~ sig = 1 N a k = 1 Na x ~ 2 [ k ] . ( 3 c ) ##EQU00024##
In this scenario, there are altogether N.sub.wN.sub.a samples from
N.sub.w repetitions of the N.sub.a-length pattern. The total memory
required is N.sub.wN.sub.a+N.sub.a, which increases linearly with
the number of writes, N.sub.w.
[0049] A more memory efficient approach can be achieved by
re-writing equation (1c) using equations (2c) and (3c) above. This
results in the following equation:
P nse = 1 N a N w X ~ Nw - P ~ sig . where X ~ Nw = k = 1 Na l = 1
Nw x 2 [ k , l ] . ( 4 c ) ##EQU00025##
From this, {tilde over (x)}[k] can be re-written as:
x ~ [ k ] = 1 N w W ~ Nw [ k ] , where W ~ Nw [ k ] = l = 1 Nw x [
k , l ] . ( 5 c ) ##EQU00026##
The quantities of {tilde over (X)}.sub.Nw and {tilde over
(W)}.sub.Nw[k] can be recursively computed in accordance with the
following equations:
X ~ l = X ~ t - 1 + k = 1 Na x 2 [ k , l ] , for l = 1 , 2 , , N w
; and ( 6 c ) ##EQU00027## {tilde over (W)}.sub.l[k]={tilde over
(W)}.sub.l-1[k]+x[k,l], for l=1, 2, . . . , N.sub.w, and k=1, 2, .
. . , N.sub.a;
with {tilde over (X)}.sub.0=0 and {tilde over (W)}.sub.0[k]=0, for
k=1, 2, . . . , N.sub.a. Based on this, the electronics noise power
and the signal power can be calculated by first computing {tilde
over (x)}[k] and {tilde over (X)}.sub.Nw using equation (5c) and
equation (6c), by processing the samples collected from N.sub.w
repetitions, one repetition at a time. At the end of the
N.sub.w.sup.th repetition, {tilde over (P)}.sub.sig is calculated
using equation (3c) and P.sub.nse is calculated using equation
(4c). The amount of memory used to implement this approach is
2N.sub.a+1. Of note, the size of the memory is independent of the
number of writes, N.sub.w. In particular, 2N.sub.a memory cells are
used for holding {tilde over (W)}.sub.l[k] and the samples from the
l.sup.th repetition, for all k, and one memory cell is used to hold
{tilde over (X)}.sub.1.
[0050] Various modifications may be implemented to increase the
accuracy of the calculations set forth above in relation to the
currently discussed embodiment. In particular, various accumulated
quantities involve a division to achieve the average quantity
{tilde over (x)}[k]. For the sake of ease of implementation and
minimizing any errors due to fixed point mathematics, the algorithm
may be modified to avoid the use of division until the conclusion
of the algorithm. To do this, the quantity {tilde over
(W)}.sub.Nw[k] is used in place of {tilde over (x)}[k]. This is
done by exploiting the relationship between {tilde over (x)}[k] and
{tilde over (W)}.sub.Nw[k] as set forth above. From this
relationship, the following signal power equation is possible by
modifying equation (3c) above:
P ~ sig = 1 N a N w 2 k = 1 Na W ~ Nw 2 [ k ] . ( 7 c )
##EQU00028##
[0051] Further, in some cases, quantization noise may be
compensated. Such quantization noise may become particularly acute
at higher signal to noise ratios. Compensation for quantization
noise may be accomplished by assuming noise is stochastically
independent from sample to sample. From this, it is possible to get
approximate relationship between the powers estimated using
fixed-point computations and the corresponding powers estimated
using floating-point computations. These relationships are set
forth in the following equations:
P nse .apprxeq. P _ nse + N w - 1 N w * .sigma. 0 2 , ( 8 c ) P ~
sig .apprxeq. P _ ~ sig + 1 N w * .sigma. 0 2 . ( 9 c )
##EQU00029##
In these, {P.sub.nse,{tilde over (P)}.sub.sig} correspond to powers
estimated using fixed-point computations, and {P.sub.nse,{tilde
over (P)}.sub.sig} correspond to powers estimated using
floating-point calculations. Further, .sigma..sub.0.sup.2 denotes
the quantization noise power associated with quantizing x[k,l,m].
Assuming uniform quantization,
.sigma..sub.0.sup.2=.DELTA..sub.0.sup.2/12 where .DELTA..sub.0 is
the quantization step-size. In situations where N.sub.w is
reasonably large (e.g., greater than one hundred), the estimated
power that is most affected will be P.sub.nse. Where the analog to
digital conversion range and number of bits are known, it is
possible to account for an estimate of quantization noise.
[0052] Turning to FIG. 6, a memory efficient signal and noise
estimation module 600 is depicted. Signal and noise estimation
module 600 includes an analog to digital converter 610 that
receives an analog input 605, and provides a series of digital
samples 615 corresponding to analog input 605. Analog input 605
includes a series of bits representing the written bit patterns
(i.e., N.sub.a.times.N.sub.w) that are read N.sub.a samples at a
time. Digital samples 615 are generally referred to as x[k,l] where
k indicates the given bit in the original pattern and l indicates
the given write.
[0053] Digital samples 615 are provided to a write accumulating
module 620. Write accumulating module 620 accumulates samples in
accordance with the following equation:
{tilde over (W)}.sub.l[k]={tilde over (W)}.sub.l-1[k]+x[k,l], for
k=1, 2, . . . , N.sub.a. (10c)
A resulting accumulation vector 622, is stored to a write
accumulating register 625 of size 1.times.N.sub.a. Write
accumulation vector 622 is provided to signal power calculator
circuit 640 that calculates signal power and provides a signal
power output 642 in accordance with the following equation:
P ~ sig = 1 N a N w 2 k = 1 Na W ~ Nw 2 [ k ] . ( 11 c )
##EQU00030##
In addition, a squared signal accumulation module 630 calculates an
accumulation of the squared signal and provides an accumulated
signal output 632 in accordance with the following equation:
X ~ l = X ~ l - 1 + k = 1 Na x 2 [ k , l ] . ( 12 c )
##EQU00031##
Accumulated signal output 632 and signal power output 642 are
provided to an overall noise calculator circuit 650. Overall noise
calculator circuit 650 calculates noise and provides a noise power
output 652 in accordance with the following equation:
P nse = 1 N a N w * X ~ Nw - P ~ sig . ( 13 c ) ##EQU00032##
Noise power output 652 is provided to a quantization compensation
circuit 655 that compensates for any quantization noise in
accordance with the following equation:
P nse P nse - N w - 1 N w * .DELTA. 0 2 12 , ( 14 c )
##EQU00033##
where .DELTA..sub.0 denotes the step-size used for quantizing
x[k,l]. Quantization compensation circuit 655 provides a
compensated noise power output 660. Signal power output 642 and
compensated noise power output 660 are provided to a signal to
noise calculator circuit 670 that calculates a signal to noise
ratio 680 in accordance with the following equation:
S N R = P sig P nse . ( 15 c ) ##EQU00034##
[0054] It should be noted that while various components of signal
and noise estimation module 600 are described as "circuits" that
they may be implemented either as an electronic circuit or as a
software/firmware circuit. Such software/firmware circuits include
a processor associated with a memory device that includes
instructions executable by the processor to perform the particular
functions described herein. Such processors may be general purpose
processors or processors specifically tailored to perform a given
function depending upon the particular implementation requirements.
In some cases, the processor may be designed to perform functions
related to more than one particular module. In some embodiments of
the present invention, signal and noise estimation module 600 is
implemented entirely as firmware or software being executed by a
processor. In other embodiments of the present invention, signal
and noise estimation module 600 is implemented entirely as a
dedicated electronic circuit. In yet other embodiments of the
present invention, signal and noise estimation module 600 is
implemented as a combination of firmware or software being executed
on a processor, and dedicated electronic circuitry. Based on the
disclosure provided herein, one of ordinary skill in the art will
recognize a variety of combinations of dedicated electronic
circuitry and software/firmware that may be used in accordance with
different embodiments of the present invention.
[0055] Turning to FIG. 7, a flow diagram 700 depicts a method in
accordance with some embodiments of the present invention for
performing both signal and noise estimation. Following flow diagram
700, a pseudo-random bit pattern N.sub.a bits long is prepared
(block 705). The bit pattern may be generated by any process known
in the art for generating a reasonably random pattern. The
pseudo-random bit pattern is written to a storage medium N.sub.w
times (block 710) resulting in a pattern N.sub.a.times.N.sub.w
long. The multiply written bit pattern is then read back from the
storage medium (block 715), one repetition at a time. It should be
noted that with a moderate increase in memory size that the
multiply written bit pattern could be read back all at once.
[0056] A signal accumulation is performed for the l.sup.th write
(block 720) in accordance with equation (10c) above. In addition, a
squared signal accumulation is performed for the l.sup.th write
(block 725) in accordance with equation (12c) above. This process
is performed for each write. Thus, it is determined if the maximum
number of writes have been accomplished (block 730). If not, the
write counter is incremented (block 735) and blocks 715-730 are
repeated.
[0057] Where the maximum number of writes has been processed (block
730), the signal power is calculated (block 750) in accordance with
equation (11c). Further, the noise power is calculated (block 740)
in accordance with equation (13c), and the calculated noise power
is compensated for analog to digital converter quantization effect
(block 745) in accordance with equation (14c) above. Using the
signal power and noise power, a signal to noise ratio is calculated
(block 755) in accordance with equation (15c) above.
[0058] In some cases, accuracy may be improved where the data
manipulated is maximally random. In particular cases, the data is
derived from a pseudo-random number generator. Further, accuracy
may be improved where a large number of samples and/or bits are
used. Thus, in some cases, one or more of N.sub.a, N.sub.r and
N.sub.w may be chosen to be large. Further, in some cases signal to
noise calculation may be done when the read channel is not doing
data detection. In such cases, the memory needed for performing the
signal to noise calculation may be that implemented for performing
data detection.
[0059] In conclusion, the invention provides novel systems,
devices, methods and arrangements for performing signal and/or
noise estimation. While detailed descriptions of one or more
embodiments of the invention have been given above, various
alternatives, modifications, and equivalents will be apparent to
those skilled in the art without varying from the spirit of the
invention. Therefore, the above description should not be taken as
limiting the scope of the invention, which is defined by the
appended claims.
* * * * *