U.S. patent application number 12/284195 was filed with the patent office on 2010-03-18 for all-optical balanced detection system.
This patent application is currently assigned to PicoSolve Inc.. Invention is credited to Peter Andrekson, Mats Skold, Henrik Sunnerud, Mathias Westlund.
Application Number | 20100067607 12/284195 |
Document ID | / |
Family ID | 42007187 |
Filed Date | 2010-03-18 |
United States Patent
Application |
20100067607 |
Kind Code |
A1 |
Westlund; Mathias ; et
al. |
March 18, 2010 |
All-optical balanced detection system
Abstract
A two gate sampling system designed to perform sampled balanced
detection of one or more input signal pairs. The present invention
performs simultaneous sampling of both signals in each signal pair
followed by digitization and combination of the sample pairs using
software. By first sampling the signals and then combine the
sampled into the corresponding balanced detected signal it is
possible to avoid the bandwidth limitations and impedance problems
introduced by traditional balanced detectors and electrical
oscilloscopes. In particular for optical sampling gates very high
bandwidth sampling gates can be designed without any impedance
issues and hence almost perfect balanced detection reconstruction
can be performed for very high speed signals. Balanced detection is
becoming more and more important as the new phase modulated optical
data signals are introduced to the market, such as e.g. PSK, DPSK,
QPSK and DQPSK. The present invention is well suited for analysis
of these new type of signals.
Inventors: |
Westlund; Mathias; (Lerum,
SE) ; Andrekson; Peter; (Fogelsville, Lehigh County,
PA) ; Sunnerud; Henrik; (Landvetter, SE) ;
Skold; Mats; (Goteborg, SE) |
Correspondence
Address: |
WENDY W. KOBA
PO BOX 556
SPRINGTOWN
PA
18081
US
|
Assignee: |
PicoSolve Inc.
|
Family ID: |
42007187 |
Appl. No.: |
12/284195 |
Filed: |
September 18, 2008 |
Current U.S.
Class: |
375/283 ;
398/172 |
Current CPC
Class: |
H04B 10/677 20130101;
H04B 10/697 20130101 |
Class at
Publication: |
375/283 ;
398/172 |
International
Class: |
H04L 27/10 20060101
H04L027/10; H04B 10/00 20060101 H04B010/00 |
Claims
1. A sampling arrangement for performing balanced detection of a
pair of input data signals, the sampling arrangement comprising at
least one pair of sampling gates, a first sampling gate of said
pair responsive to a first input signal of the pair of input
signals and a second sampling gate of said pair responsive to a
second input signal of said pair of input signals, each sampling
gate creating a stream of samples representative of the respective
input signal applied thereto; a strobe source for controlling the
at least one pair of sampling gates to open and close at a
predetermined sampling frequency f.sub.s; an adjustable delay line
disposed at the input of one sample gate of said at least one pair
of sampling gates for minimizing differences in path lengths
between each input signal and each sampling gate; and a processor
configured to perform balanced detection of the sampled pair of
input signals to generate as an output a sampled balanced detected
version of said input signal pair.
2. A sampling arrangement as defined in claim 1 wherein the at
least one pair of sampling gates comprises a pair optical sampling
gates.
3. A sampling arrangement as defined in claim 1 wherein the at
least one pair of sampling gates comprises a pair of electrical
sampling gates.
4. A sampling arrangement as defined in claim 1 wherein the strobe
source comprises an optical component.
5. A sampling arrangement as defined in claim 1 wherein the strobe
source comprises an electrical component.
6. A sampling arrangement as defined in claim 1 wherein the strobe
source comprises a pair of strobe elements operating at the same
frequency, each separate strobe element coupled to control a
separate gate of the at least one pair of sampling gates.
7. A sampling arrangement as defined in claim 1 wherein the sampled
pair of signals is represented by optical signals and the balanced
detection of each sampled pair is performed by using a
optical-to-electrical balanced receiver having two optical inputs,
S1 and S2, and an electrical output corresponding to S1-S2; an A/D
converter coupled to the output of the balanced receiver to convert
an analog set samples into a digital representation thereof.
8. A sampling arrangement as defined in claim 1 wherein the sampled
pair of signals is represented by electrical signals and the
balanced detection of each sampled pair is performed by using an
electrical circuit having two electrical inputs, S1 and S2, and an
electrical output corresponding to S1-S2; an A/D converter coupled
to the output of the balanced receiver to convert an analog set
samples into a digital representation thereof.
9. A sampling arrangement as defined in claim 1 wherein the sampled
pair of signals is represented by optical signals and the balanced
detection of each sampled pair is performed by detecting the first
and second component of each sampled pair with separate
optical-to-electrical receivers; each component of the sampled pair
are coupled to an A/D converter to convert the analog sets of
samples into digital representations thereof; the digitally
represented pairs of sampled outputs are then subtracted on a
sample by sample basis to form the reconstructed balanced detected
signal.
10. A sampling arrangement as defined in claim 1 wherein the
adjustable delay line is selected from the group consisting of:
fixed delay, set-and-forget delay or tunable delay.
11. A sampling arrangement as defined in claim 10 wherein the
adjustable delay line is selected from the group consisting of:
optical delay lines and electrical delay lines.
12. A sampling arrangement as defined in claim 1 wherein a single
pair of optical sampling gates is responsive to a single pair of
optical input signals to form a sampled pair of signals; a single
optical strobe source controls the single pair of optical sampling
gates at a predetermined frequency; an adjustable optical delay
line is used to control the input signal pair paths differences to
each sampling gate; and the output sampled signals from the single
pair of optical sampling gates are converted to electrical signals
using separate optical-to-electrical receivers followed by A/D
conversion of each signal, wherein the digitally represented
signals are then subtracted to form the balanced detected version
of the input signal pair.
13. A sampling arrangement as defined in claim 1 wherein two pairs
of optical sampling gates are responsive to two pairs of optical
input signals to form two sampled pairs of signals; a single
optical strobe source controls the two pairs of optical sampling
gates at a predetermined frequency; adjustable optical delay lines
are used to control each input signal pairs paths differences to
each sampling gate; and the output sampled signals after each pair
of sampling gates are converted to electrical signals using
separate optical-to-electrical receivers followed by A/D conversion
of each signal wherein the digitally represented signals are then
subtracted to form balanced detected versions of both input signal
pairs.
14. A sampling arrangement as defined in claim 1 wherein a single
pair of optical sampling gates is responsive to at least two pairs
of optical input signals to form sampled pairs of signals; a single
optical strobe source controls the at least two pairs of optical
sampling gates at a predetermined frequency, the sampling
arrangement further comprising: optical switches disposed in the
input signal path before each sampling gate associated with two or
more inputs and a single output and controlled such that the
optical switches select, in a predetermined order, which pair of
input signals is sent to the sampling gates; and adjustable optical
delays disposed along each input signal pair to control the input
signal pair paths differences to each sampling gate, wherein the
output sampled signals after the two sampling gates are converted
to electrical signals using separate optical-to-electrical
receivers followed by A/D conversion of each signal such that the
digitally represented signals are then subtracted to form the
balanced detected versions of the input signal pairs.
15. A sampling arrangement as defined in claim 1 wherein the
arrangement further comprises at least one additional sampling gate
responsive to at least one input reference clock signals to form
sampled reference clock signals wherein the at least one additional
sampling gate is controlled by the same strobe source as the
sampling gates responsive to the input signal pairs; wherein the
output sampled reference clocks after the sampling gates are
converted to electrical signals using separate
optical-to-electrical receivers followed by A/D conversion of each
clock such that the digitally represented clock signals are used to
create time-bases for the sampled signals to correctly position
each sample in the reconstructed balanced detected versions of the
input signal pairs.
16. A sampling arrangement as defined in claim 1 wherein the
arrangement further comprises a demodulation method for optical
signals containing data encoded in the optical phase coupled to the
input of the sampling arrangement, wherein after demodulation the
input optical signal is split up in a number of input signal pairs
containing the optical phase information converted into the form of
amplitude modulation.
17. A sampling arrangement as defined in claim 16 wherein the
demodulation method is designed to demodulate modulation formats
selected from the group consisting differential phase shift keying
(DPSK), differential quadrature phase shift keying (DQPSK), phase
shift keying (PSK), quadrature phase shift keying (QPSK) or
differential eight level phase shift keying (D8PSK)
Description
TECHNICAL FIELD
[0001] The present invention relates to a sampling arrangement
particularly well-suited for analysis of high speed data signals
and, more particularly, to a sampling arrangement with two or more
coupled sampling gates.
BACKGROUND OF THE INVENTION
[0002] Digital sampling is a technique used to visualize a
time-varying waveform by capturing quasi-instantaneous snapshots of
the waveform via, for example, a sampling gate. The gate is
"opened" and "closed" by narrow pulses (strobes) in a pulse train
that exhibit a well-defined repetitive behavior such that
ultimately all parts of the waveform are sampled. The sampling
implementation can either be real-time or equivalent-time, where
real-time sampling refers to the case where the sampling rate is
higher than twice the highest frequency content of the waveform
under test (Nyquist sampling), while equivalent-time sampling uses
an arbitrarily low sampling rate. However, equivalent-time sampling
requires the measured waveform to be repetitive (in order to
provide accurate signal reconstruction)--a fundamental limitation
when compared to real-time sampling. The present invention is
independent of the sampling rate, and hence, can be either
real-time or equivalent-time sampling.
[0003] The recent advances in the field of optical communication
with new, more complex, data modulation formats as a key technology
has created a need for optical waveform characterization tools
which are capable of extracting more information from the waveform
than simply its power as a function of time.
[0004] In particular, many different modulation formats have been
developed which use modulation of the phase of the optical carrier
to encode the data to be transmitted. A few types of phase
modulated signals have already been employed in commercial systems,
such as differential phase shift keying (DPSK) and differential
quaternary phase shift keying (DQPSK). For these differential
modulation formats the data is encoded as the relative phase shift
between consecutive symbols. In DPSK modulation schemes, for
example, a .pi. phase shift between bits represents a logical "1"
and a zero phase shift represents a logical "0". For DQPSK
modulation, each symbol contains two bits of information by
allowing four different relative phase changes between consecutive
bits (e.g., 0, .pi./2, .pi. and 3.pi./2).
[0005] FIG. 1 is used to further clarify the concept of
phase-encoded modulation formats such as phase-shift keying (PSK),
differential phase-shift keying (DPSK), and QPSK and DQPSK as
defined above. For each type of modulation, the optical phase and
amplitude of the data signal are visualized in constellation
diagrams showing the optical field amplitude as the radial distance
from origin R and the optical field phase as the angle .phi.. In
FIG. 1, the logical marks (ones) and spaces (zeros) are represented
as either absolute phase and amplitude levels (for PSK and QPSK
formats, FIGS. 1(a) and (b), respectively), or as phase and
amplitude transitions for the differentially-coded phase and
amplitude levels (for DPSK and DQPSK formats, FIGS. 1(c) and (d),
respectively). For D/QPSK each symbol contains, as shown, two bits
of information. Therefore, four different logical phase and
amplitude combinations are used to represent the "symbols" in
either of these modulation format types.
[0006] It is to be noted that the amplitude of the data signal is
constant for each of these phase-encoded modulation techniques.
Hence, if only the power of the incoming signal is "detected" using
a conventional photodetector-based o/e conversion device, the phase
information will be lost. To extract the phase information, the
signal needs to be mixed with an optical reference signal which
converts the phase information into amplitude information. For
differentially-modulated signals, delay interferometers (DIs), such
as Mach-Zehnder interferometers (MZIs), Michelson interferometers,
or the like, are commonly used in which the signal itself serves as
reference after being delayed one (or more) bit periods. For
absolute phase encoded signals (e.g. PSK or QPSK), an independent
reference signal is necessary to extract the phase information from
each bit.
[0007] The DI is an interferometric structure where the incoming
optical waveform is equally split up in two paths and one path is
delayed relative to the second path before recombining the two
paths. The relative delay is coarsely set equal to an integer
number of bit slots (most commonly one bit slot) and finely tuned
to match a particular relative phase delay of the optical carrier.
For example, in the DPSK case, the relative delay is a multiple of
.pi. in order to effectively translate the relative phase shifts
between the symbols into a binary amplitude modulated signal. The
DI has two output ports--a constructive interference port and a
deconstructive interference port (the `destructive` port outputting
the complementary data of the `constructive` port). In order to
optimize a DPSK receiver in terms of signal sensitivity, both
outputs from the DI are detected by a balanced detector
structure.
[0008] In order to recover the data embedded in an incoming DQPSK
signal, the signal is first evenly split so as to applied as "equal
power" inputs into two separate DIs with different relative optical
phase delays (+.pi./4+n*.pi. and -.pi./4+m*.pi., where n and m are
integers) and each DI pair of outputs is thereafter detected by a
balanced detector structure. By properly choosing the relative
phase delays, two bits of information per symbol can be separated
and represented as one bit per balanced detector output. The
amplitude modulated output from each balanced detector is
thereafter sampled (for example, digital sampling) in order to
visualize each bit's corresponding eye-diagram.
[0009] A major concern when using balanced detection for optical to
electrical (o/e) conversion followed by electrical digital sampling
is the influence of the measurement system on the measured
waveform, which is known to introduce measurement error. In
particular, balanced detection and electrical sampling suffers from
two major limitations: (1) limited measurement bandwidth (currently
<50 GHz); and (2) significant impedance mismatch, resulting in
distortion in the measured waveform. For high speed signal
characterization (10 GSymbols/s, 40 GSymbols/s or higher), these
effects can influence the measurement results to such an extent
that the measured waveform is dominated by the measurement system
impulse response, which is unacceptable when needing to recover
such high speed data signals.
[0010] Thus, a need remains in the art for an arrangement capable
of characterizing (visualizing) high symbol rate optical signals
without being hampered by the measurement system bandwidth or the
distortion due to o/e conversion and related impedance matching
issues.
SUMMARY OF THE INVENTION
[0011] The needs remaining in the prior art are addressed by the
present invention, which relates to a sampling arrangement
particularly well-suited for analysis of high speed data signals
and, more particularly, to a sampling arrangement comprising two or
more coupled sampling gates for recovering information from
modulated input signals.
[0012] In accordance with the present invention, a sampling
arrangement utilizes two (or more) separate sampling gates
controlled by the same strobe frequency, f.sub.s, to acquire
samples from two (or more) input signals. The lengths of the paths
to the sampling gates are adjusted by tunable (or fixed) delay
lines so as to enable precise, time-overlapped sampling of all
input signals. Examples of suitable delay line arrangements include
a "fixed" delay line, a "set-and-forget" delay line and a "tunable"
delay line.
[0013] In particular, for the application of measuring the output
signal pairs of one or more delay interferometers (DIs), as in the
case of DPSK and DQPSK signals, the delay lines are used to ensure
that the time delay from the output of each DI to the two
corresponding sampling gates are equal to within a fraction of the
temporal resolution of the sampling gates. Hence, every pair of
samples originating from the two outputs of each DI originates from
the same time "slice" of the waveform under test. The acquired
pairs of samples are then, after detection and analog-to-digital
(A/D) conversion, combined in software to samples representing
balanced detection of the sample pairs. With this scheme, the need
to perform balanced detection in hardware is avoided. In
particular, when using optical sampling gates, the sampling gate
bandwidth (temporal resolution) can be extremely high and impedance
mismatch is no longer an issue, since the sampling takes place in
the optical domain.
[0014] In one embodiment of the present invention, the two sampling
gates are used for more than one input signal pair, such as in the
case for a DQPSK signal where after demodulation by two DIs the two
output signal pairs are measured in order to present the
eye-diagram of each bit in the 2 bits/Symbol DQPSK signal. By
including, for example, optical switches before the two sampling
gates, the DI output pairs can be measured by the sampling gates by
switching in a predetermined fashion.
[0015] Another embodiment of the present invention includes a
sampling gate to sample an external reference clock, which can be
used to establish the time base for the acquired samples from the
signal under test.
[0016] Other and further aspects and embodiments of the present
invention will become apparent during the course of the following
discussion and by reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Referring now to the drawings,
[0018] FIG. 1 illustrates the modulation principle of four
different phase encoded modulation formats visualized in
constellation diagrams containing information about both the
amplitude and phase of the optical field;
[0019] FIG. 2 illustrates a prior art arrangement for demodulating
DPSK signals;
[0020] FIG. 3 shows an embodiment of the present invention for
performing sampling in a demodulated DPSK signal, and also
illustrates measured eye-diagrams of a demodulated 40 GSymbol/s
DPSK signal using this embodiment of the present invention;
[0021] FIG. 4 shows the embodiment of the present invention from
FIG. 3 with a typical signal DI demodulation setup in front of the
four input ports of the present invention;
[0022] FIG. 5 illustrates a timing condition associated with the
arrangement of FIG. 4; and
[0023] FIG. 6 illustrates an embodiment of the present invention
using an external reference clock to synchronize the acquired
samples.
DETAILED DESCRIPTION
[0024] Prior to describing the details of the exemplary sampling
arrangement of the present invention, a prior art arrangement for
demodulating DPSK-encoded signals will be reviewed with reference
to FIG. 2. The DPSK signal is demodulated using a delay
interferometer (DI) 10 having a relative delay difference between
the two interferometer arms. DI 10 is shown as comprising a first
signal path 12 and a second path 14. An incoming modulated DPSK
signal passes through a splitter 16 such that an even power level
of signal is directed into paths 12 and 14. Second path 14 includes
a delay element 18, represented as a fixed amount of delay (25 ps
in this example) and a variable amount of delay (shown as
.DELTA..phi.). The phase shift is selected such that a delay of an
integer number of bits (generally a single bit) is obtained. The
original and the phase-shifted versions of the DPSK-encoded signal
are thereafter recombined in a signal combiner 20 and split along
two separate output paths 22 and 24. As with splitter 16, the
output signals along paths 22 and 24 comprise half of the power of
the combined original/phase-shifted signals.
[0025] At the two outputs from DI 10, the phase information in the
DPSK signal is converted into two amplitude modulated signal, a
first "constructive interference" signal with power P.sub.c along a
first output path 22, and a second "destructive interference"
signal (exhibiting the complementary information) at power P.sub.d
along a second output path 24
[0026] With traditional techniques, these two output signals would
be applied as inputs to a balanced opto-electronic detector, which
would subtract the one signal from the other and convert the
difference into the electronic domain, ideally providing an
electrical signal representing P.sub.c-P.sub.d. In the prior art
arrangement of FIG. 2, a pair of photodiodes 21 and 23 are used to
provide this opto-electronic conversion. However, such o/e
conversion techniques are limited in bandwidth and quality of
impulse response. As a result, the electrical signal created after
detection does not represent the ideal case, in particular for high
speed signals.
[0027] In contrast, the present invention utilizes a sampling
technique to individually measure the waveform on each DI output,
in a manner to be described in detail hereinbelow. A
software-embedded algorithm is then used to combine the samples in
a manner which emulates the operation of an ideal balanced
detector, performing the operation P.sub.c-P.sub.d, to create a
sampled output waveform as shown in eye diagram 34 of FIG. 3. For
input signals other than DPSK (such as DQPSK), similar reasoning
applies but instead of having only two output signals after a
single DI, there can be more DI's each having two output signals
which can be taken care of by embodiments of the present invention
to be described below.
[0028] In a preferred embodiment of the present invention, the
sampling of the two DI output signals is performed in the optical
domain, so as to completely remove the influence of the bandwidth
limitations inherent in optical-electronic conversion and provide a
final result which can be very close to the targeted ideal result
P.sub.c-P.sub.d. However, the sampling technique of the present
invention is not limited to the optical domain; electrical sampling
techniques may be used in suitable applications (for example, lower
speed applications).
[0029] FIG. 3 shows an embodiment of the present invention which
utilizes the same incoming DPSK-encoded signal and demodulating
arrangement including DI 10 as described above in association with
FIG. 2. The embodiment of FIG. 3 may also be utilized if only one
bit in a two-bits-per-symbol DQPSK signal is sampled. As will be
described in detail below, a sampling arrangement 40 formed in
accordance with the present invention is used in place of prior art
o/e conversion arrangements to more accurately recover the data
from the phase-encoded incoming signal. The "constructive" signal
propagating along first output path 22 is shown as applied as an
input to first signal port Al of arrangement 40. Similarly, the
"destructive" signal propagating along second output path 24 is
applied as an input to second signal port A2.
[0030] It is to be understood that the technique of the present
invention can be scaled to support a larger number of input ports,
as will be discussed in detail below. Moreover, the input signals
can be either optical or electrical. In its most general form, the
present invention is a combination of performing sampling of pairs
of input signals in hardware and using software algorithms to
combine the created samples into a single output corresponding to
balanced detection of the input signal pairs.
[0031] Referring back to the particular embodiment of FIG. 3, such
a result is shown as the simultaneous sampling of A1 and A2 and
subsequent reconstruction of a sampled version of the power of
A1-A2. At the core of the present invention is a pair of sampling
gates 42 and 44 which are opened and closed by a common strobe
source 46 representing a sampling frequency f.sub.s. The sampling
can be performed either in the electrical domain or in the optical
domain, depending on the domain of the signals arriving at ports A1
and A2. However, to fully take advantage of the capability of the
present invention, optical sampling is the preferred embodiment in
order to eliminate all high speed electronics and o/e conversion.
By digitally sampling the output waveform from the balanced
detector structure, the corresponding electrical eye-diagram,
showing logical binary amplitude levels corresponding to the phase
transitions in the DPSK signal, can be visualized.
[0032] Optical sampling gates 42 and 44 may comprise any one of a
wide variety of implementations using different nonlinear optical
processes to create the gating functionality. Exemplary suitable
components include, but are not limited to, four-wave mixing in
fiber, sum-frequency generation in optical crystals and cross-phase
modulation in fiber or semiconductor optical amplifiers. While
strobe source 46 is illustrated as a single element, it is to be
understood that separate strobe sources, having the same sampling
frequency f.sub.s may also be used, with each separate strobe
source used to control a separate gate.
[0033] A key design parameter for the present invention is to
facilitate alignment of the sampling times of gates 42 and 44 via
strobe source 46 such that the two parts of the signal are
synchronously sampled in order for combination in the software to
be accurate. A delay line 48 is disposed at first input port Al and
is used to adjust the distance (or time delay) from the input A1 to
sampling gate 42, thereby adjusting the sampling time of gate 42
relative to the sampling time of gate 44. FIG. 5 will describe an
example which highlights the condition for adjusting delay line 48.
In general, the operation of delay line 48 can be either adjustable
or fixed, depending on the measurement application.
[0034] The output samples from the sampling gates 42 and 44 are
digitized by analog-to-digital converters (A/D) 50 and 52,
respectively, and subsequently fed into a software processing and
signal visualization system 54. The main functionality of system 54
related to the present invention is to combine the acquired sample
pairs for each measurement in order to provide balanced detection
functionality. Furthermore, the software can be used to visualize
each measured input signal pair as the corresponding balanced
detected signal. Eye diagram 28 of FIG. 3 is the sampled output
associated with the constructive port, eye diagram 30 is the
sampled output associated with the destructive port and, most
importantly, eye diagram 34 is the resultant DPSK sampled
information eye diagram, where each of these diagrams was created
by system 54.
[0035] An alternative embodiment of the present invention allows
for detection of the output samples from the sampling gates 42 and
44 using low bandwidth balanced receivers in order to perform the
balanced detection in the hardware before digitizing the samples in
an A/D converter.
[0036] It is to be understood that the present invention is
independent of the particular method utilized to time stamp each
sample. In particular, the technique of the present invention has
been found to work for both real-time sampling and equivalent-time
sampling, irrespective of the time-base design used for
equivalent-time sampling.
[0037] FIG. 4 illustrates an embodiment suitable for measurement
of, for example, QPSK or DQPSK signals, which requires the
generation of two sample pairs for proper demodulation. As before,
the incoming phase-encoded signal is split along signal paths 12
and 14 by a power splitter 16. In this case, however, the portion
of the signal propagating along signal path 14 is thereafter
applied as an input to a first DI 10-1, and the remaining portion
propagating along signal path 12 is applied as an input to a second
DI 10-2, as shown in FIG. 4. Each DI 10 includes a separate delay
element 18, illustrated as delay element 18-1 (associated with DI
10-1) and delay element 18-2 (associated with DI 10-2). Delay
elements 18-1 and 18-2 are shown as exhibiting the appropriate bit
delays TS and phase relations .DELTA..phi.1 and .DELTA..phi.2 for
demodulation of the input signal. In particular, for the case of
DQPSK the phase relations can be, for example,
.DELTA..phi.1=+.pi./4 and .DELTA..phi.2=-.pi./4, in order to
separate each bit in the 2 bits/Symbol DQPSK data signal. By
flipping the switches 56 and 58 in a predetermined manner, the
outputs from each DI 10-1 and 10-2 can be measured separately, and
with the present invention the corresponding balanced detected
signals to each demodulated bit of the DQPSK signal can be
visualized.
[0038] In this case, a set of four output signals have been
created, a first signal pair A1 and A2 from DI 10-1 (similar to the
embodiment of FIG. 3, as discussed above) and a second signal pair
B1 and B2, from DI 10-2. In order to most efficiently utilize the
elements of sampling arrangement 40, switches 56 and 58 are
positioned at the entrance ports of arrangement 40, in front of
sampling gates 42 and 44, in order to facilitate alternating
sampling of the input signal pairs from DI's 10-1 and 10-2, that
is, first A1, A2 and then B1, B2. As shown, a second delay line
48-2, associated with input B1 is included in the arrangement to
provide the same synchronization activity as delay line 48 defined
above and discussed in detail below.
[0039] FIG. 4 also points out that o/e conversion of the signals
can be performed before the sampling takes place. In this case, a
photodiode or other o/e conversion element is disposed along each
signal path, and is collectively illustrated as conversion
component 70 in FIG. 4. In this case, sampling gates 42 and 44 will
comprise electronic sampling gates. The positioning of o/e
conversion component 70 is flexible and can be either directly
after DIs 10-1 and 10-2, or at any other point in front of sampling
gates 42 and 44. Additionally, delay lines 48-1 and 48-2, as well
as switches 56 and 58 can be either electrical or optical.
[0040] FIG. 5 illustrates the critical timing required between
sampling gates 42 and 44 in order to sample each part of the
generated signal pairs at the correct matching times. FIG. 5 is an
extracted part of the embodiment of FIG. 4. In FIG. 5, the signal
is not split up until point A, corresponding to the output of the
DI 10-1. From this point on, it is critical that the time
difference from point A until each part of the signal is sampled
very close to equal in order to generate samples originating from
the same time in the original signal. This is a condition in order
to be able to combine the two samples in the software and emulate
the balanced detection.
[0041] The timing condition can be expressed using the notations in
FIG. 5 as |(T.sub.c-t.sub.c)-(T.sub.d-t.sub.d)|<.DELTA..tau.,
where T.sub.c is the propagation time for the "constructive" signal
from point A to sampling gate 42, t.sub.c is the propagation time
for the sampling strobe pulse from strobe source 46 to sampling
gate 42, T.sub.d is the propagation time for the "destructive"
signal from point A to sampling gate 44, t.sub.d is the propagation
time for the sampling strobe pulse from strobe source 46 to
sampling gate 44, and .DELTA..tau. represents the temporal
resolution of sampling gates 42 and 44. As alluded to above, delay
line 48-1 plays a critical role to facilitate the fulfillment of
this timing condition, in particular since the lengths of the
conventional output fiber connectors of a delay interferometer is
normally beyond the control of the constructor of the demodulating
system present invention. However, with precise control of every
other component within sampling arrangement 40, delay line 48 may
be omitted, in particular for low bandwidth sampling gate solutions
with high .DELTA..tau.. The timing condition applies to all input
signal pairs within the system of the present invention (e.g., in
the arrangement of FIG. 4, a similar condition applies from point B
to sampling gates 42 and 44).
[0042] It has been pointed out that the present invention is
independent on the time-base design used to synchronize the
acquired samples into a replica of the original signal. However, it
should be noted that the present invention is compatible with U.S.
Pat. No. 7,327,302, issued to M. Westlund et al. on Feb. 5, 2008,
assigned to the assignee of this application and hereby
incorporated by reference. FIG. 6 illustrates an embodiment of the
present invention where an external reference signal source 60 is
used to supply a gating control signal for the system, where the
frequency f.sub.c of reference clock signal C is directly related
to the frequency of the demodulated signals appearing at ports A1,
A2, B1 and B2. As shown, the reference clock output signal C from
source 60 is sampled by a separate sampling gate 62, using the same
strobe source 46. The generated clock samples are then digitized by
an A/ID converter 64 and applied as an input to software processing
system 54. With this input information, the timebase of the
external clock can be determined by the embedded software
algorithms. Since the frequency f.sub.c of the external clock is
directly related to the frequency of the input signal bit rate, the
time-base of the external clock can be directly transferred to the
recovered output signal signal.
[0043] It is to be understood that other advantages and
modifications will readily occur to those skilled in the art.
Therefore, the invention in its broader aspects is not limited to
the specific details and representative embodiments shown and
described herein. Accordingly, various modifications may be made
without departing from the spirit or scope of the general inventive
concept as defined by the claims appended hereto.
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