U.S. patent application number 12/524525 was filed with the patent office on 2010-03-18 for high-speed low-power differential receiver.
This patent application is currently assigned to Rambus Inc.. Invention is credited to Robert E. Palmer, John W. Poulton.
Application Number | 20100066450 12/524525 |
Document ID | / |
Family ID | 39388278 |
Filed Date | 2010-03-18 |
United States Patent
Application |
20100066450 |
Kind Code |
A1 |
Palmer; Robert E. ; et
al. |
March 18, 2010 |
High-Speed Low-Power Differential Receiver
Abstract
A low-voltage differential communication system includes a low-
and programmable-swing voltage-mode transmitter that delivers a
low-voltage differential signal to a receiver via differential
channel. The receiver employs two input transistors, each in a
common-gate configuration, to recover the low-voltage differential
signal. A current source in the receiver biases the input
transistors such that their source voltages are nominally biased at
the common-mode voltage of the differential signal, and their
gate-source voltages remain essentially constant with
common-mode-voltage fluctuations.
Inventors: |
Palmer; Robert E.;
(Carrboro, NC) ; Poulton; John W.; (Chapel Hill,
NC) |
Correspondence
Address: |
SILICON EDGE LAW GROUP, LLP
6601 KOLL CENTER PARKWAY, SUITE 245
PLEASANTON
CA
94566
US
|
Assignee: |
Rambus Inc.
Los Altos
CA
|
Family ID: |
39388278 |
Appl. No.: |
12/524525 |
Filed: |
February 11, 2008 |
PCT Filed: |
February 11, 2008 |
PCT NO: |
PCT/US2008/001826 |
371 Date: |
July 24, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60900804 |
Feb 12, 2007 |
|
|
|
Current U.S.
Class: |
330/261 ;
327/534 |
Current CPC
Class: |
H03F 2203/45008
20130101; H04L 25/0278 20130101; H04L 25/063 20130101; H03F
2203/45306 20130101; H03F 3/45179 20130101; H03F 2203/45588
20130101; H04L 7/046 20130101 |
Class at
Publication: |
330/261 ;
327/534 |
International
Class: |
H03F 3/45 20060101
H03F003/45; H03K 3/01 20060101 H03K003/01 |
Claims
1. An amplifier comprising: a voltage divider having a
common-mode-voltage tap between differential first and second
inputs; a first transistor having a first current-handling
terminal, coupled to the first input, and a first control terminal;
a second transistor having a second current-handling terminal,
coupled to the second input, and a second control terminal coupled
to the first control terminal; a third transistor having a third
current-handling terminal, coupled to the tap, a third control
terminal coupled to the first control terminal, and a fourth
current-handling terminal; and a current source having a
bias-current output node coupled to the fourth current-handling
terminal to provide a bias current through the third
transistor.
2. The amplifier of claim 1, wherein the first, second, and third
transistors are nMOS transistors.
3. The amplifier of claim 1, wherein the bias current through the
fourth current-handling terminal of the third transistor fixes a
voltage between the tap and the first and second control
terminals.
4. The amplifier of claim 1, wherein the current source includes a
replica transistor having a replica control terminal and a replica
current-handling terminal.
5. The amplifier of claim 4, wherein the current source is to hold
the replica current-handling terminal at a reference voltage.
6. The amplifier of claim 5, wherein the reference voltage
approximates a common-mode voltage on the tap.
7. The amplifier of claim 1, further comprising a diode having an
anode connected to the first input and a cathode connected to a
ground terminal at a ground potential, wherein the diode exhibits a
threshold voltage.
8. The amplifier of claim 7, wherein a common-mode voltage on the
tap is referenced to the ground potential, and wherein the
common-mode voltage is less than half the threshold voltage.
9. A communication system comprising: a differential transmitter
having first and second transmitter nodes to convey a differential
signal referenced to a ground node at ground potential; first and
second diodes each having an anode connected to one of the first
and second transmitter nodes and a cathode connected to the ground
node, wherein each of the first and second diodes conducts current
from the anode to the cathode when the anode-to-cathode voltage
exceeds a diode threshold voltage, and wherein the differential
signal exhibits a common-mode voltage, referenced to the ground
potential, that is less than half of the diode threshold voltage;
and a differential receiver having: a voltage divider having a
common-mode-voltage tap between the first and second transmitter
nodes; a first transistor having a first current-handling terminal,
coupled to the first transmitter node, and a first control
terminal; a second transistor having a second current-handling
terminal, coupled to the second transmitter node, and a second
control terminal coupled to the first control terminal; a third
transistor having a third current-handling terminal, coupled to the
tap, a third control terminal coupled to the first control
terminal, and a fourth current-handling terminal; and a current
source having a bias-current output node coupled to the fourth
current-handling terminal to provide a bias current through the
third transistor.
10. The system of claim 9, wherein the first, second, and third
transistors are nMOS transistors.
11. The system of claim 9, wherein the bias current through the
fourth current-handling terminal of the third transistor fixes a
second voltage between the tap and the first and second control
terminals.
12. The system of claim 9, wherein the current source includes a
replica transistor similar to the first transistor and having a
replica control terminal and a replica current-handling
terminal.
13. The amplifier of claim 12, wherein the current source is to
hold the replica current-handling terminal at a reference
voltage.
14. The amplifier of claim 13, wherein the reference voltage
approximates the common-mode voltage.
15. A method for receiving first and second complementary signals
on respective complementary input pads and exhibiting a common-mode
voltage, wherein each of the complementary input pads is coupled to
a supply node via a respective diode that exhibits a diode
threshold voltage, the method comprising: biasing a source or
emitter of each of a first and second n-type transistors to a
reference voltage less than half of the diode threshold voltage and
a gate or base of the first and second transistors to a gate-bias
voltage above the reference voltage; applying the first and second
complementary signals to the sources or emitters of the respective
first and second n-type transistors; extracting the common-mode
voltage from the first and second complementary signals; and
changing the gate-bias voltage with changes in the extracted
common-mode voltage, wherein the gate-bias voltage rises and falls
with the extracted common-mode voltage.
16. The method of claim 15, further comprising generating the
gate-bias voltage by passing a bias current through a third
transistor having a gate or base connected to the gate or base of
the first and second n-type transistors.
17. The method of claim 16, further comprising passing a current
through a replica of the first transistors to establish the bias
current.
18. An amplifier comprising: complementary first and second inputs
to receive a differential signal that exhibits a common-mode
voltage; a first transistor having a first current-handling
terminal coupled to the first input, a second current-handling
terminal, and a first control terminal; a second transistor having
a third current-handling terminal coupled to the second input, a
fourth current-handling terminal, and a second control terminal
coupled to the first control terminal; means for biasing the first
and third current-handling terminals at the common-mode voltage,
and the first and second control terminals at a gate-bias voltage
above the common-mode voltage; and means for changing the gate-bias
voltage with changes in the common-mode voltage.
19. A computer-readable medium having stored thereon a data
structure defining an amplifier, the data structure comprising:
first data representing a voltage divider having a
common-mode-voltage tap between differential first and second
inputs; second data representing a first transistor having a first
current-handling terminal, coupled to the first input, and a first
control terminal; third data representing a second transistor
having a second current-handling terminal, coupled to the second
input, and a second control terminal coupled to the first control
terminal; fourth data representing a third transistor having a
third current-handling terminal, coupled to the tap, a third
control terminal coupled to the first control terminal, and a
fourth current-handling terminal; and fifth data representing a
current source having a bias-current output node coupled to the
fourth current-handling terminal to provide a bias current through
the third transistor.
20. A receiver comprising: complementary first and second
differential inputs to receive a differential signal that exhibits
a common-mode voltage; complementary first and second signal paths
that extend from the respective first and second differential
inputs; a differential amplifier having first and second amplifier
inputs coupled to the respective first and second differential
inputs via the first and second signal paths; and common-mode
rejection circuitry outside of the first and second differential
signal paths.
21. The receiver of claim 20, further comprising a voltage divider
extending between the first and second inputs and including a
common-mode-voltage tap coupled to the common-mode rejection
circuitry.
22. The receiver of claim 20, wherein the differential amplifier
includes a first transistor and a second transistor, wherein the
first amplifier input is a first source of the first transistor,
and wherein the second amplifier input is a second source of the
second transistor.
23. The receiver of claim 22, wherein the common-mode rejection
circuitry includes a diode-connected third transistor, and wherein
the first, second, and third transistors have interconnected gate
terminals.
Description
FIELD
[0001] The subject matter disclosed herein relates generally to the
field of communications, and more particularly to high speed
electronic signaling within and between integrated circuit
devices.
BACKGROUND
[0002] Present-day computing systems require very high off-chip
communications bandwidth, and high-speed serial links for
chip-to-chip interconnect are now ubiquitous. Many of these links
have channels that present modest attenuation, crosstalk, and
reflections. Chip-to-chip serial links, however, have generally
evolved from backplane transceivers that must deal with
comparatively difficult channels, and so often dissipate far more
power than necessary for short-haul chip-to-chip links. Such
channels are therefore relatively power inefficient.
[0003] Many systems would benefit from links that require less
power to move information at high data rates. For example, laptop
computers quickly drain expensive batteries, and power dissipated
as heat can be uncomfortable and often necessitates noisy fans
and/or complex power-management schemes. Perhaps more important,
power requirements significantly impact the usage time and
performance of handheld devices. There is therefore a demand for
systems and methods for communicating data at high speeds using
minimal power. The term "specific power" is a helpful performance
metric that considers the power required to move data at speed, and
is typically expressed in units of Watts per Gigabit per second
(W/Gb/s). The demand for efficient high-speed signaling can thus be
phrased as a need for systems with very low specific-power
requirements.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] The subject matter disclosed is illustrated by way of
example, and not by way of limitation, in the figures of the
accompanying drawings and in which like reference numerals refer to
similar elements and in which:
[0005] FIG. 1 depicts a differential, low-voltage system 100 in
accordance with one embodiment.
[0006] FIG. 2 details a current source 200 that can be used as an
embodiment of current source 190 of FIG. 1.
[0007] FIG. 3 details a transmitter 300 for use in one
embodiment.
[0008] FIG. 4 details an embodiment of a receiver 400 for use in
one embodiment.
DETAILED DESCRIPTION
[0009] FIG. 1 depicts a differential, low-voltage system 100 in
accordance with one embodiment. System 100 includes a transmitter
105 and a receiver 110 interconnected by a differential
communication channel 115. Transmitter 105 efficiently delivers a
low-voltage differential signal to receiver 110. Receiver 110
amplifies the differential signal while providing excellent
common-mode noise rejection. Both the transmitter and receiver have
very low specific-power requirements, and can thus be used to
advantage in applications that require both power efficiency and
speed performance.
[0010] Transmitter 105 includes a pair of voltage regulators 120
and 122, a complementary pre-driver 125, a differential stacked
nMOS transmit stage 130, and a pair of complementary output pads
135/140. Output driver 130 is powered by regulator 122 and ground
potential. Regulator 122 can adjust swing voltage Vo such that the
output signal TX[P,N] is anywhere between 50 and 300 mVppd
(millivolts peak-to-peak, differential).
[0011] Pre-driver 125 splits incoming data stream Din into
complementary bit streams DP/DN to the gates of the nMOS
transistors within output driver 130. When signal DP is high and DN
low, the upper left and lower right nMOS transistors are turned on.
In that case, current flows from power node Vo to ground via
channel 115 and receiver 110. Conversely, when signal DP is low and
DN high, the upper right and lower left nMOS transistors are turned
on. Once again, current flows from power node Vo to ground via
channel 115 and receiver 110, albeit in the opposite direction
through receiver 110. The power efficiency of this signaling scheme
is evident in the fact that substantially all the current between
supply nodes Vo and ground is used to convey signals to receiver
110.
[0012] Pre-driver 125 is powered by regulator 120 and ground
potential, so the signals DP/DN applied to the nMOS gates alternate
between regulated voltage Vr and ground. Regulator 120 adjusts
voltage Vr to set the sum of the pull-up and pull-down impedances
of stage 130 approximately equal to the differential impedance of
channel 115. The relative sizes of the pull-up and pull-down
transistors may be fixed at design time to give equal impedance at
an assumed operating point.
[0013] The differential impedance looking into the transmitter
output terminals 135/140 is fairly independent of the common-mode
voltage Vcm of signal TX[P,N] because the pull-up transistor is
operating as a source follower while the pull-down transistor is
common-source. As common-mode voltage Vcm increases, the
pull-down's small-signal impedance increases, while the pull-up's
small-signal impedance decreases.
[0014] To provide high-quality termination, the capacitance
shunting the termination should be small. In both the transmitter
and receiver, shunt capacitance is generally dominated by wiring
and ESD clamps 145/150. Using a low voltage Vo and referencing the
output signal TX[P,N] to ground allows ESD clamps 145/150 to
include forward-biased diodes. The overall ESD protection strategy
is detailed later in connection with FIG. 3. Regulator 122 keeps
voltage Vo low enough to prevent the forward-biased ESD diode from
turning on (i.e., Vo<Vtd), and can be adjusted between 50 and
300 mVppd in one embodiment. That is, the common-mode voltage Vcm
can be adjusted between 25 and 150 mV. Regulator 120 then regulates
voltage Vr such that the nMOS transistors of output driver 130,
when biased on, exhibit a desired resistance and remain in the
triode region. In one embodiment, the desired on-resistance for the
nMOS transistors is fifty ohms.
[0015] In a typical example, assume it is desired that transmitter
105 convey a differential signal TX[P,N] having an output swing
voltage of about 200 mVppd and exhibiting a differential output
impedance of 100 ohms. Regulator 122 may be set such that output
voltage Vo is about 200 mV. The output swing of each half of the
differential output driver 130 is equal to half the regulated
supply voltage Vo, centered at a common-mode voltage equal to half
the regulated supply voltage Vo. Regulator 120 may then set voltage
Vr to a level that provides, on each of the complementary
transmitter outputs, an output impedance of the desired 50 ohms.
There are a number of methods and circuits for controlling Vr to
obtain a desired impedance, some of which are discussed below. A
single-ended transmitter that is in many respects similar to
transmitter 105 is detailed in "Self Terminating Low Voltage Swing
CMOS Output Driver," by Tom Knight and Alex Krymm (CICC 1987).
[0016] The transistors within output driver 130 double as
termination impedances. As such, the "on" impedance of each
transistor should be matched to the channel and should behave
linearly (like a resistor) over the range of output voltages. To
accomplish this, each transistor is biased to remain in the
"linear" region (aka the "triode" region) when conducting. When a
transistor is in the linear region the current through the
transistor changes linearly with changes in drain-source voltage
Vds: in other words, the transistor behaves like a resistor.
[0017] As is well known, a transistor is in the linear region when
its gate/source voltage Vgs is greater than the threshold voltage
Vt of the transistor (Vgs>Vt) and its drain-source voltage Vds
is less than or equal to Vgs-Vt. Stated mathematically, a
transistor is in the linear region when:
Vgs>Vt&Vds.ltoreq.Vgs-Vt (1)
[0018] In FIG. 1, output driver 130 is referenced to ground, or
zero volts. The voltage Vgs for a given transistor is therefore
either zero volts (transistor off) or Vr (transistor on), and Vds
is at most 0.75.times.Vo. We can ignore the case where a transistor
is off because the impedance of a transistor biased off is very
large relative to the impedance of the transistor biased on.
Equation (1) therefore simplifies to:
0.75*Vo.ltoreq.Vr-Vt. (2)
which can be rearranged to derive the voltage Vr that keeps the
transistors of output driver 130 in the triode region when
active:
Vr.gtoreq.0.75*Vo+Vt (3)
The transistors in driver 130 are selected such that regulator 120
can provide a voltage Vr that produces a desired output impedance
over the expected range of output-voltage swings. The voltage Vt in
equations 1 through 3 relates to the transistors within driver 130,
and is assumed to be the same or similar for each nMOS transistor
in this example. Voltage Vt may be the same or different from diode
threshold Vtd.
[0019] A waveform diagram 155 inset over channel 115 in FIG. 1
shows output signal TX[P,N] as a differential signal between output
voltage Vo and ground, and shows that output voltage Vo is well
below Vtd and regulated voltage Vr is above Vtd. In a typical
example, voltage Vo is 200 mV, Vcm is 100 mV, signal TX[P,N] is 100
mV peak-to-peak (200 mVppd) centered about voltage Vcm, threshold
voltages Vt and Vtd are respectively about 400 mV and 600 mv, and
regulated voltage Vr is somewhere above 700 mV and is selected such
that the output impedance of an nMOS transistor in driver 130 is 50
ohms when biased on.
[0020] Receiver 110 receives the low-voltage differential signal
TX[P,N] as a differential, low-common-mode, signal RX[P,N] on
complementary input pads 165/170. ESD clamps 175/180 similar to
clamps 145 and 150 protect these differential input nodes and the
input devices of receiver 110 from damage due to electrostatic
discharge. Pads 165 and 170 drive a common-gate amplifier 185 that
provides both gain and level conversion for the incoming
differential signal RX[P,N]. In this example, the inputs of
amplifier 185 are terminated for the differential mode only, and
about 25% of the termination impedance is represented by the
amplifier's input impedance.
[0021] A voltage divider consisting of two equivalent resistors R1
and R2 (e.g., 75 ohms each) extends between input nodes RXP and
RXN. The node common to resistors R1 and R2 is a tap from which
amplifier 185 extracts the common-mode voltage Vcm of the incoming
signal. A first nMOS transistor T1 has its source coupled to input
node 165 and, via a resistor R3, to ground; its drain tied to
supply voltage Vdd via a resistor R4; and its gate tied to a bias
voltage Vcg (for "voltage common-gate"). A second nMOS transistor
T2 has its source coupled to input node 170 and, via a resistor R5,
to ground; its drain tied to supply voltage Vdd via a resistor R6;
and its gate tied to bias voltage Vcg. A third nMOS transistor T3
has its source coupled to the common-mode-voltage tap Vcm; its
drain coupled to a current source 190 that delivers a bias current
Ibias; and its gate tied to both its drain and to bias voltage
Vcg.
[0022] Common-gate amplifier 185 works well for relatively low
input voltages, and the bias scheme provided by current source 190
and transistor T3 affords considerable common-mode rejection
without compromising the amplifier bandwidth.
[0023] Common-mode voltage fluctuations appear on the sources of
transistors T1 and T2, and at the common-mode-voltage tap Vcm
between resistors R1 and R2. The gate-source voltage Vgs3 of
transistor T3 depends upon the value of bias current Ibias. Because
bias current Ibias is constant, so too is voltage Vgs3. Common-gate
voltage Vcg is the sum of Vcm and Vcg3, so common-gate voltage Vcg
rises and falls with voltage Vcm. Common-mode-voltage fluctuations
thus appear on both the sources and the gates of transistors T1 and
T2. As a consequence, the gate-source voltages Vgs1 and Vgs2 of
input transistors T1 and T2 remain constant in the face of
common-mode noise. It follows that the currents through resistors
R4 and R6 and respective output voltages DinP and DinN also remain
constant. Common-gate amplifier 185 thus provides effective
common-mode noise rejection. Further, the common-mode rejection
circuitry, which includes current source 190 and transistor T3 in
this embodiment, is outside of the differential signal paths
between nodes 165/170 and the sources of respective transistors T1
and T2. Transistor T3 is diode-connected in this embodiment, and
functions to convert bias current Ibias into a stable gate-source
voltage Vgs. Transistor T3 might be replaced with e.g. a diode or
resistor in other embodiments.
[0024] In some embodiments the source voltages Vs1 and Vs2 of
transistors T1 and T2, the inputs of common-gate amplifier 185, are
biased to the nominal common-mode voltage. In this example, voltage
Vcm should be at or very near output voltage Vo divided by two
(Vcm=Vo/2). Bias current Ibias is thus carefully controlled such
that the gate-source voltage Vgs3 of transistor T3 sets voltage Vcg
to a level that biases the source voltages Vs1 and Vs2 of
transistors T1 and T2 to the nominal common-mode voltage Vo/2.
[0025] FIG. 2 details a current source 200 that can be used as an
embodiment of current source 190 of FIG. 1. Current source 200
includes a voltage reference 202, a replica common-gate amplifier
205, a level converter 210, an operational amplifier 215, and some
bias circuitry 220 to create the appropriate bias levels for
converter 210 and op-amp 215. The purpose of current source 200, as
noted above in connection with current source 190 of FIG. 1, is to
set current Ibias to a level that ensures transistors T1 and T2
(FIG. 1) are biased such that their source voltages Vs1 and Vs2 are
set to the nominal common-mode voltage Vo/2.
[0026] Voltage reference 202 is a simple voltage divider, in this
example, that divides output voltage Vo by two. Voltage Vo or Vo/2
can be sourced on or off chip, and can be fixed or adjustable. In
embodiments in which receiver 110 has one or more neighboring
transmitter like transmitter 105 of FIG. 1, voltage Vo can be taken
from one of those. Alternatively, voltage Vo/2 can be derived from
the common-mode voltage Vcm at the receiver. Many other methods of
providing an appropriate reference common-mode voltage can be used,
as will be readily apparent to those of skill in the art.
[0027] Replica amplifier 205 includes transistors T1' and T3' and
resistors R3' and R4', each of which is fabricated to behave in the
same manner as the like-named elements of FIG. 1. Transistors T1'
and T3 and resistors R3' and R4' can thus be expected to behave in
the same manner as transistor T1 and resistors R3 and R4,
respectively.
[0028] Level converter 210 raises voltages Vo/2 and Vcm' to Vo1 and
Vcm1 respectively. Op-amp 215 then amplifies the difference between
signals Vo1 and Vcm1 and presents the resulting output voltage to
the gate of an nMOS transistor T4, and consequently controls a bias
current Ibias'. A current minor comprised of PMOS transistors T5,
T6, and T7 replicates current Ibias', by distributing a bias
voltage Pbias, to produce current Ibias of FIG. 1 and Ibias'' in
replica amplifier 205. (The transistor T8 below transistor T6 is
off when the receiver is operational.)
[0029] The feedback from the output of op-amp 215 to transistor T7
forces voltage Vcg' to change until the current through transistor
T1' and resistor R3' causes voltage Vcm', the source voltage of
transistor T1', to match the nominal common-mode voltage Vo/2. The
current Ibias'' dictates voltage Vcg', so the identical bias
current Ibias sets voltage Vcg of FIG. 1 equal to Vcg'. Because
transistor T1' and resistors R3' and R4' replicate transistor T1
and resistors R3 and R4, applying a gate voltage Vcg that matches
the replica control voltage Vcg' sets the source of transistor T1
to the nominal common-mode voltage Vo/2. The same holds true for
transistor T2. Current source 200 thus ensures that the source
voltages of transistors T1 and T2 are nominally biased at voltage
Vo/2.
[0030] Returning to FIG. 2, a pair of inverters 250 and 255
generates signals ponL and ponH from a power-on signal Pon.
Asserting signal Pon places current source 200 in an operational
mode, whereas deasserting signal Pon places current source 200 in a
low-power state. Voltage Vo may be pulled to ground upon power
down, or reference voltage 202 can otherwise be disabled in a
manner that reduces or eliminates current flow when current source
200 is disabled.
[0031] FIG. 3 details a transmitter 300 for use in one embodiment.
Transmitter 300 is in many ways similar to transmitter 105 of FIG.
1, with like-labeled elements being the same or similar. Output
terminals TX[P,N] are driven by an N-over-N output driver 130
operating between ground GND and a regulated supply voltage Vo,
which is generated by an on-chip regulator 305 in this embodiment.
A pre-driver 125 operating between ground GND and a second
regulated voltage Vr drives the gates of the nMOS transistors in
driver 130. The second regulated voltage Vr determines the output
impedance of output driver 130 and is generated by an on-chip
regulator 310 in this embodiment. The output voltage Vo, and thus
the output swing, are adjusted digitally via a DAC 315 that sets
the currents both regulators 305 and 310. In systems with a number
of transmitters, one or both of regulators 305 and 310 may be
shared among the transmitters. Providing each transmitter with a
dedicated regulator or regulators, however, allows the output
impedance and/or output swing to be adjusted on a per-transmitter
basis.
[0032] Voltage regulator 310 is a replica-bias circuit that forces
a replica transmitter 320 to have the same impedance as a scaled
resistor. This method sets the sum of the pull-up and pull-down
impedances of driver 130 approximately equal to the line impedance
of an associated channel (e.g., channel 115 of FIG. 1). The
relative sizes of the pull-up and pull-down transistors are fixed
at design time to give equal impedance at an assumed operating
point.
[0033] The differential impedance looking into the transmitter
output terminals (e.g., nodes TX[P,N]) is fairly independent of
common-mode voltage Vcm because the active pull-up transistor is
configured as a source follower while the active pull-down
transistor is in a common-source configuration. As the common-mode
voltage Vcm increases, the pull-down transistor's small-signal
impedance increases, while the pull-up transistor's impedance
decreases. During a data transition, the output impedance depends
on the details of the trajectories of the drive voltages at the
gates of the output transistors. Simulation indicates that the
small-signal differential output impedance varies by less than 15%
during a transition.
[0034] The capacitance Cbyp rejects noise and contributes to the
termination impedance. Line currents into terminals TX[P,N] flow
through the pull-up/pull-down impedances in series with the
regulator 305 output impedance, which is dominated by the reactance
XCbyp of capacitance Cbyp at high frequencies. Capacitance Cbyp,
about 36 pF in one example, may be implemented in the 2.5-V
"native" nMOS device and occupy about 8400 um.sup.2. Capacitance
Cbyp can be implemented as a thick-oxide device for improved
reliability, but this capacitor is charged to less than 300 mV, so
the oxide is not heavily stressed in any case. Use of the 1-V
native device would have provided 2.5 the capacitance in the same
area.
[0035] As noted previously, pre-driver 125 is powered from the
regulated termination-control Voltage Vr. The paired inverters
ensure that transition times for both data-edge polarities will be
equal. The pre-driver provides fanout, which allows a 2:1
multiplexer 325 at the input of pre-driver 125 to be drawn quite
small, thereby minimizing the load on a half-bit-rate distributed
clock Clk[P,N]. Since pre-driver 125 is powered from a regulated
supply, it is fairly immune to power supply noise and introduces
very little timing jitter. The variation of regulated voltage Vr
across cases tends to make the edge rate of the gate control
signals driving the output stage nearly constant across PVT
variation, and the edge rate of the transmitter output is also
nearly constant.
[0036] With reference to both voltage regulators, since the
voltages that must be compared within the regulator circuitry are
near GND, common-gate (CG) nMOS amplifiers are a good choice for
the gain blocks. A Vt-referenced current source 330 produces a bias
voltage Vb for pMOS DAC 315. The current in the reference is
proportional to Vtn/R, so the voltage across the resistor load in
the DAC is Vref=KVtn, independent of R, where K can be adjusted
digitally via Vs_set. The diode-connected nMOS in DAC 315 is drawn
the same size as the nMOS common-gate devices in regulators 305 and
310, and, assuming high loop gain, the voltage appears at all four
of the input terminals of the CG amplifiers.
[0037] Regulator 305 is a simple series regulator that forces
output voltage Vo equal to reference voltage Vref (Vo=Vref),
thereby allowing Vo to be set directly by Vo_set. Regulator 305 has
two poles in its loop transfer function: one set by the output
impedance of the CG amplifier and the input capacitance of the pMOS
series regulator, and the second by the load impedance and bypass
capacitor Cbyp in output driver 130. An additional compensating
capacitor Ccomp makes the amplifier pole the dominant one. The
addition of capacitor Ccomp saves power in the CG error amp of
regulator 305 and avoids an extremely large bypass capacitor, but
compromises the power supply rejection for regulator 305, allowing
half of the supply noise to get through the regulator between
10-100 MHz. A production version of this link may have the output
pole be dominant, which may require a larger bypass capacitance and
higher power consumption in the CG amplifier of regulator 305. For
example, with capacitor Cbyp implemented in the thin-oxide native
nMOS in the same 8200 um.sup.2 area, it appears possible to build a
greatly improved regulator for about 1 mW of additional power
dissipation.
[0038] Regulator 310 is a two-stage design. The first stage
generates a "master" copy Vm of the Vr control voltage. Since the
load current for the pMOS stage is near zero, it is easy to make
the output pole for this two-pole regulator the dominant one, and
power supply rejection is quite good. The second stage is a simple
series regulator with a gain of one, and it serves to isolate the
"master" voltage Vm from the time-varying load of the transmitter's
pre-driver inverters. The transmitter replica 320 used to set the
impedance is drawn very small ( 1/16th scale); mismatch between the
replica devices and the main transmitter contributes about a 5%
variation in output impedance.
[0039] All of the P+/poly de-salicided resistors are digitally
trimmable by .+-.20% to account for process variation. Trim is
performed using a bench measurement in some embodiments; a
production link may use e.g. a resistor trim cell and an external
reference resistor.
[0040] A half-bit-rate distributed clock Clk[P,N] is received and
buffered in two CMOS inverter stages to drive the final 2:1
multiplexer (mux) 325 and a clock divider stage 335 that generates
one-quarter, one-eighth, and one-sixteenth-rate clocks for a 16:2
mux stage 340. Since the clock loading is relatively small, the
fanout of the two-stage clock buffer is set to two to avoid
introducing jitter from power supply noise, while still dissipating
relatively little power in the clock buffer.
[0041] An embodiment of ESD clamps 145/150 is detailed in the lower
right corner of FIG. 3. Similar ESD claims can be used in receiver
110. In this example, a cross-coupled diode pair 445 extends
between the output pad (e.g., 140) and ground. The left-most diode
is forward biased, which is to say its anode is connected to the
output terminal and its cathode is connected to ground. The ESD
claim will therefore shunt current to ground if the voltage on node
140 rises above a diode threshold voltage Vtd. The series-connected
nMOS transistors and the resistor represent the output from one leg
of driver 130. Additional diodes 450 establish shunt paths between
ground and supply line Vdd. Other suitable low-voltage ESD clamps
are detailed by John Poulton in published U.S. Application No.
20060132996.
[0042] FIG. 4 details a receiver 400 for use in one embodiment.
Input nodes RX[P,N] drive a common-gate amplifier that provides
both gain and level conversion for a second-stage
amplifier/equalizer 405. The input is terminated for the
differential mode only, and about 25% of the termination impedance
is represented by the common-gate amplifier's input. Correctly
terminating the common mode in the common-gate amplifier would have
required burning five times the power to maintain the proper input
common-mode bias. This embodiment instead relies on the
transmitter's common-mode termination along with the receiver's
common-mode rejection.
[0043] Large nFET switches 410 enabled by a control signal dgate
allow the receiver to be disconnected from the line for offset
trim. The bias voltage Vcg may be developed in a replica bias
arrangement as detailed previously in connection with FIG. 2.
Voltage Vcg sets the input common-mode voltage of the receiver to
the nominal output common-mode voltage of the transmitter;
alternatively, voltage Vcg can be programmed externally.
[0044] The second-stage amplifier 405 is a fairly conventional
source-degenerated differential amplifier. The amount of
degeneration is controlled digitally via the eq_set input to a
decoder 412. In an embodiment designed for 6.25 Gb/s operation in
90 nm CMOS, the maximum EQ setting in this amplifier provides about
8.7 dB of peaking at the Nyquist frequency relative to dc gain,
with a slope of three dB/octave. The offset of the two input
amplifier stages can be trimmed, separately from the samplers, by
adjusting a trim signal eqtrim to a DAC 415. The EQ amplifier
drives a bank of four samplers, two data and two edge, derived from
StrongARM flip-flops, e.g. of the type described in J. Montanaro et
al., "A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor," IEEE J.
Solid-State Circuits, vol. 31, no. 11, pp. 1703-1714, November
1996.
[0045] Each sampler has an associated 8-bit DAC 420 to cancel input
offset to within about 1 mV. Each sampler pair (data and edge)
drives identical 2:16 demultiplexers 425 composed of a binary tree
of 1:2 stages. The samplers are equipped with an enable input,
which, when signal enab_edge is de-asserted, prevent the samplers
from toggling. Edge samplers are enabled infrequently by a software
CDR and adaptive EQ algorithm, neither of which is detailed here.
When disabled, the edge samplers and their associated 2:16
demultiplexer dissipate essentially no power. A 7-bit digitally
programmable phase rotator 430, implemented as a PLL in one
embodiment, accepts the distributed half-bit-rate clock clk[P,N] as
input and generates four quadrature half-bit-rate clocks eclkN,
eclkP, dclkN, and dclkP to drive the four samplers.
[0046] The input offset of receiver 400 may be trimmed iteratively.
First, both input amplifiers are powered down, allowing each
sampler to be trimmed with its inputs at Vdd. Next, the input
amplifiers are powered on, with inputs RX[P,N] disconnected from
the inputs of the common-gate amplifier by de-asserting dgate. The
resulting offset, averaged over the samplers, is then trimmed by
adjusting signal eqtrim to DAC 415. Finally, any residual offset is
removed at each sampler. The maximum required offset trim across 32
receivers (128 samplers) was about 45 mV for the samplers and 25 mV
for the input amplifiers in one example.
[0047] The above-described transmitters and receivers are designed
to operate at a single speed, but could be modified to operate over
a range of speeds, though providing serial links that work over a
wide range of data rates typically requires more power consumption.
Whether fixed or adjustable, the frequency of operation can be
chosen to best utilize the process technology used to fabricate the
devices.
[0048] In the foregoing description and in the accompanying
drawings, specific terminology and drawing symbols are set forth to
provide a thorough understanding of the present invention. In some
instances, the terminology and symbols may imply specific details
that are not required to practice the invention. For example, the
interconnection between circuit elements or circuit blocks may be
shown or described as multi-conductor or single conductor signal
lines. Each of the multi-conductor signal lines may alternatively
be single-conductor signal lines, and each of the single-conductor
signal lines may alternatively be multi-conductor signal lines.
Signals and signaling paths shown or described as being
single-ended may also be differential, and vice-versa. Similarly,
signals described or depicted as having active-high or active-low
logic levels may have opposite logic levels in alternative
embodiments.
[0049] With reference to FIG. 1, output driver 130 and amplifier
185 used nMOS transistors, which are well suited for low-voltage
operation when configured as shown. However, other types of n- and
p-type transistors might also be used. For example, transistors T1,
T2, and T3 might be implemented using n-type bipolar junction
transistors (BJTs). A BJT configured like transistor T1 would be in
a common-base configuration, the current-handling terminals would
be called the collector and emitter instead of the drain and
source, and the BJT control terminal would be called the base
instead of the gate.
[0050] An output of a process for designing an integrated circuit,
or a portion of an integrated circuit, comprising one or more of
the circuits described herein may be a computer-readable medium
such as, for example, a magnetic tape or an optical or magnetic
disk. The computer-readable medium may be encoded with data
structures or other information describing circuitry that may be
physically instantiated as an integrated circuit or portion of an
integrated circuit. Although various formats may be used for such
encoding, these data structures are commonly written in Caltech
Intermediate Format (CIF), Calma GDS II Stream Format (GDSII), or
Electronic Design Interchange Format (EDIF). Those of skill in the
art of integrated circuit design can develop such data structures
from schematic diagrams of the type detailed above and the
corresponding descriptions and encode the data structures on
computer readable medium. Those of skill in the art of integrated
circuit fabrication can use such encoded data to fabricate
integrated circuits comprising one or more of the circuits
described herein.
[0051] While the present invention has been described in connection
with specific embodiments, variations of these embodiments will be
obvious to those of ordinary skill in the art. For example, the
above-described links can be bidirectional, as would be required
e.g. for memory systems, and might operate with a non-terminated
receiver in channels with little crosstalk and reflections.
Moreover, some components are shown directly connected to one
another while others are shown connected via intermediate
components. In each instance the method of interconnection, or
"coupling," establishes some desired electrical communication
between two or more circuit nodes, or terminals. Such coupling may
often be accomplished using a number of circuit configurations, as
will be understood by those of skill in the art. Therefore, the
spirit and scope of the appended claims should not be limited to
the foregoing description. Only those claims specifically reciting
"means for" or "step for" should be construed in the manner
required under the sixth paragraph of 35 U.S.C. .sctn.112.
* * * * *