U.S. patent application number 12/536469 was filed with the patent office on 2010-02-11 for memory cell that includes a carbon-based memory element and methods of forming the same.
This patent application is currently assigned to SanDisk 3D LLC. Invention is credited to Huiwen Xu.
Application Number | 20100032640 12/536469 |
Document ID | / |
Family ID | 41119448 |
Filed Date | 2010-02-11 |
United States Patent
Application |
20100032640 |
Kind Code |
A1 |
Xu; Huiwen |
February 11, 2010 |
MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS
OF FORMING THE SAME
Abstract
Memory cells, and methods of forming such memory cells, are
provided that include a carbon-based reversible resistivity
switching material. In particular embodiments, methods in
accordance with this invention form a memory cell by forming a
layer of carbon material above a substrate, forming a barrier layer
above the carbon layer, forming a hardmask layer above the barrier
layer, forming a photoresist layer above the hardmask layer,
patterning and developing the photoresist layer to form a
photoresist region, patterning and etching the hardmask layer to
form a hardmask region, and using an ashing process to remove the
photoresist region while the barrier layer remains above the carbon
layer. Other aspects are also provided.
Inventors: |
Xu; Huiwen; (Sunnyvale,
CA) |
Correspondence
Address: |
DUGAN & DUGAN, PC
245 Saw Mill River Road, Suite 309
Hawthorne
NY
10532
US
|
Assignee: |
SanDisk 3D LLC
Milpitas
CA
|
Family ID: |
41119448 |
Appl. No.: |
12/536469 |
Filed: |
August 5, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61087164 |
Aug 7, 2008 |
|
|
|
Current U.S.
Class: |
257/2 ;
257/E47.001; 257/E47.005; 438/488; 438/509; 977/742 |
Current CPC
Class: |
H01L 27/2409 20130101;
H01L 27/2481 20130101; H01L 45/1675 20130101; H01L 45/1641
20130101; H01L 45/149 20130101; H01L 45/1616 20130101; H01L 45/1625
20130101; G11C 2213/35 20130101; H01L 21/318 20130101; H01L 27/101
20130101; H01L 27/2463 20130101; H01L 45/04 20130101; G11C 2213/71
20130101; H01L 21/3146 20130101; H01L 45/1233 20130101 |
Class at
Publication: |
257/2 ; 438/509;
438/488; 257/E47.001; 257/E47.005; 977/742 |
International
Class: |
H01L 47/00 20060101
H01L047/00 |
Claims
1. A method of forming a memory cell, the method comprising:
forming a layer of carbon material above a substrate; forming a
barrier layer above the carbon layer; forming a hardmask layer
above the barrier layer; forming a photoresist layer above the
hardmask layer; patterning and developing the photoresist layer to
form a photoresist region; patterning and etching the hardmask
layer to form a hardmask region; and using an ashing process to
remove the photoresist region while the barrier layer remains above
the carbon layer.
2. The method of claim 1, further comprising patterning and etching
the carbon layer using the hardmask region.
3. The method of claim 2, further comprising performing an in-situ
anneal of the etched carbon layer.
4. The method of claim 3, wherein performing the in-situ anneal
comprises thermally annealing the carbon layer at a temperature
between about 200.degree. C. to about 450.degree. C.
5. The method of claim 3, wherein performing the in-situ anneal
comprises thermally annealing the carbon layer for about 30 seconds
to about 5 minutes.
6. The method of claim 3, wherein performing the in-situ anneal
comprises thermally annealing the carbon layer at a pressure of
about 1 milliTorr to about 760 Torr.
7. The method of claim 3, wherein performing the in-situ anneal
comprises thermally annealing the carbon layer in an environment
containing any of Ar, He, or N.sub.2.
8. The method of claim 2, further comprising forming a dielectric
liner material on a sidewall of the etched carbon layer.
9. The method of claim 8, wherein the dielectric sidewall liner
material comprises silicon nitride.
10. The method of claim 1, wherein forming the carbon layer
comprises depositing carbon material using a plasma enhanced
chemical vapor deposition technique.
11. The method of claim 1, wherein the carbon material comprises
any of amorphous carbon containing nanocrystalline graphene,
graphene, graphite, carbon nano-tubes, and amorphous diamond-like
carbon.
12. The method of claim 1, wherein the hardmask layer comprises a
dielectric material.
13. The method of claim 12, wherein the dielectric material
comprises any of silicon dioxide, silicon oxide, silicon nitride,
silicon oxynitride, boron nitride, amorphous carbon, amorphous
silicon, carbon doped oxides, silicon-carbon layers or a low K
dielectric material.
14. The method of claim 1, further comprising forming a steering
element coupled to the carbon layer.
15. The method of claim 14, wherein the steering element comprises
a diode.
16. The method of claim 14, wherein the steering element comprises
a p-n or p-i-n diode.
17. The method of claim 14, wherein the steering element comprises
a polycrystalline diode.
18. A memory cell formed according to the method of claim 1.
19. A method of forming a memory cell, the method comprising:
forming a layer of carbon material above a substrate; forming a
photoresist layer above the carbon layer; patterning and developing
the photoresist layer to form a photoresist region; patterning and
etching the carbon layer using the photoresist region; and
performing an ashing process to remove the photoresist region
without substantially damaging an exposed sidewall of the etched
carbon layer.
20. The method of claim 19, wherein the ashing process comprises
using a downstream remote plasma comprising H.sub.2O and O.sub.2
processing gasses.
21. The method of claim 20, wherein the downstream remote plasma
comprises a microwave plasma.
22. The method of claim 21, wherein the microwave plasma has a
microwave power of between about 500 to about 2000 watts.
23. The method of claim 20, wherein the remote plasma comprises an
H.sub.2O flow rate of between about 50 to about 2000 standard cubic
centimeters per minute.
24. The method of claim 20, wherein the remote plasma comprises an
O.sub.2 flow rate of between about 500 to about 5000 standard cubic
centimeters per minute.
25. The method of claim 20, wherein the remote plasma further
comprises a C.sub.xF.sub.y processing gas, wherein x=1-4, y=2x, or
y=(2x+2).
26. The method of claim 25, wherein the remote plasma comprises a
C.sub.xF.sub.y flow rate of between about 0 to about 500 standard
cubic centimeters per minute.
27. The method of claim 19, wherein the ashing process comprises
using a directional radio-frequency generated oxygen-plasma to ash
the photoresist region.
28. The method of claim 27, wherein the directional plasma
comprises an O.sub.2 flow rate of between about 500 to about 10000
standard cubic centimeters per minute.
29. The method of claim 27, wherein the directional plasma
comprises an H.sub.2 flow rate of between about 50 to about 2000
standard cubic centimeters per minute.
30. The method of claim 27, wherein the directional plasma
comprises a radio frequency power of between about 100 to about
1500 watts.
31. The method of claim 27, wherein the directional plasma is
performed at a pressure of between about 0.1 Torr to about 2.0
Torr.
32. The method of claim 27, wherein the directional plasma is
performed at a temperature of between about 5.degree. C. to about
250.degree. C.
33. The method of claim 19, further comprising performing an
in-situ anneal of the etched carbon layer.
34. The method of claim 33, wherein performing the in-situ anneal
comprises thermally annealing the carbon layer at a temperature
between about 200.degree. C. to about 450.degree. C.
35. The method of claim 33, wherein performing the in-situ anneal
comprises thermally annealing the carbon layer for about 30 seconds
to about 5 minutes.
36. The method of claim 33, wherein performing the in-situ anneal
comprises thermally annealing the carbon layer at a pressure of
about 1 milliTorr to about 760 Torr.
37. The method of claim 33, wherein performing the in-situ anneal
comprises thermally annealing the carbon layer in an environment
containing any of Ar, He, or N.sub.2.
38. The method of claim 19, further comprising forming a dielectric
liner material on a sidewall of the etched carbon layer.
39. The method of claim 38, wherein the dielectric sidewall liner
material comprises silicon nitride.
40. The method of claim 19, wherein forming the carbon layer
comprises depositing carbon material using a plasma enhanced
chemical vapor deposition technique.
41. The method of claim 19, wherein the carbon material comprises
any of amorphous carbon containing nanocrystalline graphene,
graphene, graphite, carbon nano-tubes, and amorphous diamond-like
carbon.
42. The method of claim 19, further comprising forming a steering
element coupled to the carbon layer.
43. The method of claim 42, wherein the steering element comprises
a diode.
44. The method of claim 42, wherein the steering element comprises
a p-n or p-i-n diode.
45. The method of claim 42, wherein the steering element comprises
a polycrystalline diode.
46. A memory cell formed according to the method of claim 19.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional
Patent Application Ser. No. 61/087,164, filed Aug. 7, 2008,
"Methods And Apparatus For Forming Memory Cells Using Carbon Read
Writable Materials," which is hereby incorporated by reference
herein in its entirety for all purposes.
TECHNICAL FIELD
[0002] This invention relates to non-volatile memories, and more
particularly to a memory cell that includes a carbon-based memory
element, and methods of forming the same.
BACKGROUND
[0003] Non-volatile memories formed from reversible resistance
switching elements are known. For example, U.S. patent application
Ser. No. 11/968,154, filed Dec. 31, 2007, titled "Memory Cell That
Employs A Selectively Fabricated Carbon Nano-Tube Reversible
Resistance Switching Element And Methods Of Forming The Same" (the
"'154 Application"), which is hereby incorporated by reference
herein in its entirety for all purposes, describes a rewriteable
non-volatile memory cell that includes a diode coupled in series
with a carbon-based reversible resistivity switching material.
[0004] However, fabricating memory devices from carbon-based
materials is technically challenging, and improved methods of
forming memory devices that employ carbon-based materials are
desirable.
SUMMARY
[0005] In a first aspect of the invention, a method of forming a
memory cell is provided, the method including forming a layer of
carbon material above a substrate, forming a barrier layer above
the carbon layer, forming a hardmask layer above the barrier layer,
forming a photoresist layer above the hardmask layer, patterning
and developing the photoresist layer to form a photoresist region,
patterning and etching the hardmask layer to form a hardmask
region, and using an ashing process to remove the photoresist
region while the barrier layer remains above the carbon layer.
[0006] In a second aspect of the invention, a method of forming a
memory cell is provided, the method including forming a layer of
carbon material above a substrate, forming a photoresist layer
above the carbon layer, patterning and developing the photoresist
layer to form a photoresist region, patterning and etching the
carbon layer using the photoresist region, and performing an ashing
process to remove the photoresist region without substantially
damaging an exposed sidewall of the etched carbon layer.
[0007] Other features and aspects of the present invention will
become more fully apparent from the following detailed description,
the appended claims and the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Features of the present invention can be more clearly
understood from the following detailed description considered in
conjunction with the following drawings, in which the same
reference numerals denote the same elements throughout, and in
which:
[0009] FIG. 1 is a diagram of an exemplary memory cell in
accordance with this invention;
[0010] FIG. 2A is a simplified perspective view of an exemplary
memory cell in accordance with this invention;
[0011] FIG. 2B is a simplified perspective view of a portion of a
first exemplary memory level formed from a plurality of the memory
cells of FIG. 2A;
[0012] FIG. 2C is a simplified perspective view of a portion of a
first exemplary three-dimensional memory array in accordance with
this invention;
[0013] FIG. 2D is a simplified perspective view of a portion of a
second exemplary three-dimensional memory array in accordance with
this invention;
[0014] FIG. 3 is a cross-sectional view of an exemplary embodiment
of a memory cell in accordance with this invention;
[0015] FIGS. 4A-4J illustrate cross-sectional views of a portion of
a substrate during an exemplary fabrication of a single memory
level in accordance with this invention; and
[0016] FIGS. 5A-5H illustrate cross-sectional views of a portion of
a substrate during an exemplary fabrication of a single memory
level in accordance with this invention.
DETAILED DESCRIPTION
[0017] Carbon films such as amorphous carbon ("aC") containing
nanocrystalline graphene (referred to herein as "graphitic
carbon"), graphene, graphite, carbon nano-tubes, amorphous
diamond-like carbon ("DLC") (described below), silicon carbide,
boron carbide and other similar carbon-based materials may exhibit
resistivity-switching behavior that may make such materials
suitable for use in microelectronic non-volatile memories.
[0018] Indeed, some carbon-based materials have demonstrated
reversible resistivity-switching memory properties on lab-scale
devices with a 100.times. separation between ON and OFF states and
mid-to-high range resistance changes. Such a separation between ON
and OFF states renders carbon-based materials viable candidates for
memory cells formed using the carbon materials in memory elements
in series with steering elements, such as tunnel junctions, diodes,
thin film transistors, or the like.
[0019] A carbon-based resistivity-switching material may be
characterized by its ratio of forms of carbon-carbon bonding.
Carbon typically bonds to carbon to form either an sp.sup.2-bond (a
trigonal carbon-carbon double bond ("C.dbd.C")) or an sp.sup.3-bond
(a tetrahedral carbon-carbon single bond ("C--C")). In each case, a
ratio of sp.sup.2-bonds to sp.sup.3-bonds can be determined via
Raman spectroscopy by evaluating the D and G bands. In some
embodiments, the range of materials may include those having a
ratio such as M.sub.yN.sub.z where M is the sp.sup.3 material and N
is the sp.sup.2 material and y and z are any fractional value from
zero to 1 as long as y+z=1. To provide sufficient
resistivity-switching behavior useful in a memory device, the
carbon-based material should have a relatively high concentration
of sp.sup.2 graphene crystallinity. DLC tends to be
sp.sup.3-hybridized, and to be amorphous with respect to long range
order, and also has found to be switchable.
[0020] A carbon-based memory element may be formed by arranging a
carbon-based material between two electrodes to form a
metal-insulator-metal ("MIM") structure. In such a configuration,
the carbon-based material sandwiched between the two metal or
otherwise conducting layers serves as a reversible
resistance-switching element. A memory cell may then be formed by
coupling the MIM structure in series with a steering element, such
as a diode.
[0021] Semiconductor fabrication techniques may be used to
fabricate carbon-based memory cells. For example, semiconductor
processing techniques may be used to fabricate a pillar that
includes a vertically oriented diode and a carbon-based
resistivity-switching layer coupled in series between a bottom
conductor and a top conductor. In particular, such pillars could be
formed by depositing the various layers that constitute the memory
cell on a substrate, including a carbon material layer, depositing
photoresist on top of the layers, patterning the photoresist,
etching to form the pillars, and then removing the photoresist.
[0022] In practice, however, fabricating such carbon-based memory
cells is technically challenging. In particular, after the pillars
have been formed, the photoresist must be removed. In conventional
semiconductor processing techniques, photoresist typically is
removed by using a plasma ashing process. Conventional plasma
ashing processes, however, may damage the exposed carbon material
layer in the pillars. Indeed, carbon-based materials historically
have been used in the semiconductor industry as hard masks that are
typically removed by ashing. Thus, if conventional plasma ashing
processes are used to remove the photoresist, the ashing process
may cause severe undercutting of the sidewalls of the exposed
carbon material layer, and may render the memory cell
inoperative.
[0023] Therefore, improved techniques for forming carbon-based
memory cells are desired that may be used with conventional
semiconductor processing techniques.
[0024] Exemplary methods in accordance with this invention protect
carbon-based materials from damage during subsequent processing
steps. In a first exemplary method of this invention, a barrier
layer is formed above a carbon-based material layer, a hard mask
layer is formed above the barrier layer, and photoresist is
deposited above the hard mask layer. The photoresist is patterned
and developed to form patterned photoresist regions. The patterned
photoresist regions are then used to pattern and etch the hardmask
layer to form patterned hardmask regions. The barrier layer is not
etched, and thus the carbon-based material layer remains covered by
the barrier material. The patterned photoresist regions are then
removed, such as by a conventional ashing process. The patterned
hardmask regions are then used to pattern and etch the carbon-based
material layer. In this regard, the carbon-based material layer
remains protected during the ashing process.
[0025] In an alternative method of this invention, photoresist is
deposited a carbon-based material layer, and the photoresist is
patterned and developed to form patterned photoresist. The
patterned photoresist regions are then used to pattern and etch the
carbon-based material layer. The patterned photoresist regions are
then removed by a two-step ash process that removes the photoresist
without substantially damaging the carbon-based material layer.
Exemplary Inventive Memory Cell
[0026] FIG. 1 is a schematic illustration of an exemplary memory
cell 10 in accordance with this invention. Memory cell 10 includes
a carbon-based reversible resistance-switching element 12 coupled
to a steering element 14. Carbon-based reversible
resistance-switching element 12 includes a carbon-based reversible
resistivity switching material (not separately shown) having a
resistivity that may be reversibly switched between two or more
states.
[0027] For example, carbon-based reversible resistivity-switching
material of element 12 may be in an initial, low-resistivity state
upon fabrication. Upon application of a first voltage and/or
current, the material is switchable to a high-resistivity state.
Application of a second voltage and/or current may return
reversible resistivity switching material to a low-resistivity
state. Alternatively, carbon-based reversible resistance-switching
element 12 may be in an initial, high-resistance state upon
fabrication that is reversibly switchable to a low-resistance state
upon application of the appropriate voltage(s) and/or current(s).
When used in a memory cell, one resistance state may represent a
binary "0," whereas another resistance state may represent a binary
"1," although more than two data/resistance states may be used.
Numerous reversible resistivity switching materials and operation
of memory cells employing reversible resistance switching elements
are described, for example, in U.S. patent application Ser. No.
11/125,939, filed May 9, 2005 and titled "Rewriteable Memory Cell
Comprising A Diode And A Resistance Switching Material" (the "'939
Application"), which is hereby incorporated by reference herein in
its entirety for all purposes.
[0028] Steering element 14 may include a thin film transistor, a
diode, metal-insulator-metal tunneling current device, or another
similar steering element that exhibits non-ohmic conduction by
selectively limiting the voltage across and/or the current flow
through carbon-based reversible resistance-switching element 12. In
this manner, memory cell 10 may be used as part of a two or three
dimensional memory array and data may be written to and/or read
from memory cell 10 without affecting the state of other memory
cells in the array.
[0029] Exemplary embodiments of memory cell 10, carbon-based
reversible resistance-switching element 12 and steering element 14
are described below with reference to FIGS. 2A-2D and FIG. 3.
Exemplary Embodiments of Memory Cells and Memory Arrays
[0030] FIG. 2A is a simplified perspective view of an exemplary
embodiment of a memory cell 10 in accordance with this invention.
Memory cell 10 includes a pillar 11 coupled between a first
conductor 20 and a second conductor 22. Pillar 11 includes a
carbon-based reversible resistance-switching element 12 coupled in
series with a steering element 14. In some embodiments, a barrier
layer 24 may be formed between carbon-based reversible
resistance-switching element 12 and steering element 14, a barrier
layer 28 may be formed between steering element 14 and first
conductor 20, and a barrier layer 33 may be formed between
carbon-based reversible resistance-switching element 12 and a metal
layer 35. Barrier layers 24, 28 and 33 may include titanium
nitride, tantalum nitride, tungsten nitride, or other similar
barrier layer. In some embodiments, barrier layer 33 and metal
layer 35 may be formed as part of upper conductor 22.
[0031] Carbon-based reversible resistance-switching element 12 may
include a carbon-based material suitable for use in a memory cell.
In exemplary embodiments of this invention, carbon-based reversible
resistance-switching element 12 may include graphitic carbon. For
example, in some embodiments, graphitic carbon reversible
resistivity switching materials may be formed as described in U.S.
patent application Ser. No. 12/499,467, filed Jul. 8, 2009 and
titled "Carbon-Based Resistivity-Switching Materials And Methods Of
Forming The Same" (the "'467 application") (Docket No. SD-MXA-294),
which is hereby incorporated by reference herein in its entirety
for all purposes. In other embodiments, carbon-based reversible
resistance-switching element 12 may include other carbon-based
materials such as graphene, graphite, carbon nano-tube materials,
DLC, silicon carbide, boron carbide, or other similar carbon-based
materials. For simplicity, carbon-based reversible
resistance-switching element 12 will be referred to in the
remaining discussion interchangeably as "carbon element 12," or
"carbon layer 12."
[0032] In an exemplary embodiment of this invention, steering
element 14 includes a diode. In this discussion, steering element
14 is sometimes referred to as "diode 14." Diode 14 may include any
suitable diode such as a vertical polycrystalline p-n or p-i-n
diode, whether upward pointing with an n-region above a p-region of
the diode or downward pointing with a p-region above an n-region of
the diode. For example, diode 14 may include a heavily doped n+
polysilicon region 14a, a lightly doped or an intrinsic
(unintentionally doped) polysilicon region 14b above the n+
polysilicon region 14a, and a heavily doped p+ polysilicon region
14c above intrinsic region 14b. It will be understood that the
locations of the n+ and p+ regions may be reversed.
[0033] First conductor 20 and/or second conductor 22 may include
any suitable conductive material such as tungsten, any appropriate
metal, heavily doped semiconductor material, a conductive silicide,
a conductive silicide-germanide, a conductive germanide, or the
like. In the embodiment of FIG. 2A, first and second conductors 20
and 22, respectively, are rail-shaped and extend in different
directions (e.g., substantially perpendicular to one another).
Other conductor shapes and/or configurations may be used. In some
embodiments, barrier layers, adhesion layers, antireflection
coatings and/or the like (not shown) may be used with the first
conductor 20 and/or second conductor 22 to improve device
performance and/or aid in device fabrication.
[0034] FIG. 2B is a simplified perspective view of a portion of a
first memory level 30 formed from a plurality of memory cells 10,
such as memory cell 10 of FIG. 2A. For simplicity, carbon element
12, diode 14, barrier layers 24, 28 and 33, and metal layer 35 are
not separately shown. Memory array 30 is a "cross-point" array
including a plurality of bit lines (second conductors 22) and word
lines (first conductors 20) to which multiple memory cells are
coupled (as shown). Other memory array configurations may be used,
as may multiple levels of memory.
[0035] For example, FIG. 2C is a simplified perspective view of a
portion of a monolithic three dimensional array 40a that includes a
first memory level 42 positioned below a second memory level 44.
Memory levels 42 and 44 each include a plurality of memory cells 10
in a cross-point array. Persons of ordinary skill in the art will
understand that additional layers (e.g., an interlevel dielectric)
may be present between the first and second memory levels 42 and
44, but are not shown in FIG. 2C for simplicity. Other memory array
configurations may be used, as may additional levels of memory. In
the embodiment of FIG. 2C, all diodes may "point" in the same
direction, such as upward or downward depending on whether p-i-n
diodes having a p-doped region on the bottom or top of the diodes
are employed, simplifying diode fabrication.
[0036] For example, in some embodiments, the memory levels may be
formed as described in U.S. Pat. No. 6,952,030, titled
"High-Density Three-Dimensional Memory Cell," which is hereby
incorporated by reference herein in its entirety for all purposes.
For instance, the upper conductors of a first memory level may be
used as the lower conductors of a second memory level that is
positioned above the first memory level as shown in FIG. 2D. In
such embodiments, the diodes on adjacent memory levels preferably
point in opposite directions as described in U.S. patent
application Ser. No. 11/692,151, filed Mar. 27, 2007 and titled
"Large Array Of Upward Pointing P-I-N Diodes Having Large And
Uniform Current" (the "'151 Application"), which is hereby
incorporated by reference herein in its entirety for all purposes.
For example, as shown in FIG. 2D, the diodes of the first memory
level 42 may be upward pointing diodes as indicated by arrow D1
(e.g., with p regions at the bottom of the diodes), whereas the
diodes of the second memory level 44 may be downward pointing
diodes as indicated by arrow D2 (e.g., with n regions at the bottom
of the diodes), or vice versa.
[0037] A monolithic three dimensional memory array is one in which
multiple memory levels are formed above a single substrate, such as
a wafer, with no intervening substrates. The layers forming one
memory level are deposited or grown directly over the layers of an
existing level or levels. In contrast, stacked memories have been
constructed by forming memory levels on separate substrates and
adhering the memory levels atop each other, as in Leedy, U.S. Pat.
No. 5,915,167, titled "Three Dimensional Structure Memory." The
substrates may be thinned or removed from the memory levels before
bonding, but as the memory levels are initially formed over
separate substrates, such memories are not true monolithic three
dimensional memory arrays.
[0038] FIG. 3 is a cross-sectional view of an exemplary embodiment
of memory cell 10 of FIG. 2A formed on a substrate, such as a wafer
(not shown). In particular, memory cell 10 includes a pillar 11
coupled between first and second conductors 20 and 22,
respectively. Pillar 11 includes carbon element 12 coupled in
series with diode 14, and also may include barrier layers 24, 28,
and 33, a silicide layer 50, a silicide-forming metal layer 52, and
a metal layer 35. A dielectric layer 58 substantially surrounds
pillar 11. In some embodiments, a sidewall liner 54 separates
selected layers of pillar 11 from dielectric layer 58. Adhesion
layers, antireflective coating layers and/or the like (not shown)
may be used with first and/or second conductors 20 and 22,
respectively, to improve device performance and/or facilitate
device fabrication.
[0039] First conductor 20 may include any suitable conductive
material such as tungsten, any appropriate metal, heavily doped
semiconductor material, a conductive silicide, a conductive
silicide-germanide, a conductive germanide, or the like. Second
conductor 22 includes a barrier layer 26, which may include
titanium nitride or other similar barrier layer material, and
conductive layer 140, which may include any suitable conductive
material such as tungsten, any appropriate metal, heavily doped
semiconductor material, a conductive silicide, a conductive
silicide-germanide, a conductive germanide, or the like.
[0040] Diode 14 may be a vertical p-n or p-i-n diode, which may
either point upward or downward. In the embodiment of FIG. 2D in
which adjacent memory levels share conductors, adjacent memory
levels preferably have diodes that point in opposite directions
such as downward-pointing p-i-n diodes for a first memory level and
upward-pointing p-i-n diodes for an adjacent, second memory level
(or vice versa).
[0041] In some embodiments, diode 14 may be formed from a
polycrystalline semiconductor material such as polysilicon, a
polycrystalline silicon-germanium alloy, polygermanium or any other
suitable material. For example, diode 14 may include a heavily
doped n+ polysilicon region 14a, a lightly doped or an intrinsic
(unintentionally doped) polysilicon region 14b above the n+
polysilicon region 14a, and a heavily doped p+ polysilicon region
14c above intrinsic region 14b. It will be understood that the
locations of the n+ and p+ regions may be reversed.
[0042] In some embodiments, a thin germanium and/or
silicon-germanium alloy layer (not shown) may be formed on n+
polysilicon region 14a to prevent and/or reduce dopant migration
from n+ polysilicon region 14a into intrinsic region 14b. Use of
such a layer is described, for example, in U.S. patent application
Ser. No. 11/298,331, filed Dec. 9, 2005 and titled "Deposited
Semiconductor Structure To Minimize N-Type Dopant Diffusion And
Method Of Making" (the "'331 Application"), which is hereby
incorporated by reference herein in its entirety for all purposes.
In some embodiments, a few hundred angstroms or less of
silicon-germanium alloy with about 10 at % or more of germanium may
be employed.
[0043] A barrier layer 28, such as titanium nitride, tantalum
nitride, tungsten nitride, or other similar barrier layer material,
may be formed between the first conductor 20 and the n+ region 14a
(e.g., to prevent and/or reduce migration of metal atoms into the
polysilicon regions).
[0044] If diode 14 is fabricated from deposited silicon (e.g.,
amorphous or polycrystalline), a silicide layer 50 may be formed on
diode 14 to place the deposited silicon in a low resistivity state,
as fabricated. Such a low resistivity state allows for easier
programming of memory cell 10, as a large voltage is not required
to switch the deposited silicon to a low resistivity state. For
example, a silicide-forming metal layer 52 such as titanium or
cobalt may be deposited on p+ polysilicon region 14c. In some
embodiments, an additional nitride layer (not shown) may be formed
at a top surface of silicide-forming metal layer 52. In particular,
for highly reactive metals, such as titanium, an additional cap
layer such as TiN layer may be formed on silicide-forming metal
layer 52. Thus, in such embodiments, a Ti/TiN stack is formed on
top of p+ polysilicon region 14c.
[0045] A rapid thermal anneal ("RTA") step may then be performed to
form silicide regions by reaction of silicide-forming metal layer
52 with p+ region 14c. The RTA step may be performed at a
temperature between about 650.degree. C. to about 750.degree. C.,
more generally between about 600.degree. C. to about 800.degree.
C., preferably at about 750.degree. C., for a duration between
about 10 seconds to about 60 seconds, more generally between about
10 seconds to about 90 seconds, preferably about 1 minute, and
causes silicide-forming metal layer 52 and the deposited silicon of
diode 14 to interact to form silicide layer 50, consuming all or a
portion of the silicide-forming metal layer 52.
[0046] As described in U.S. Pat. No. 7,176,064, titled "Memory Cell
Comprising A Semiconductor Junction Diode Crystallized Adjacent To
A Silicide," which is hereby incorporated by reference herein in
its entirety for all purposes, silicide-forming materials such as
titanium and/or cobalt react with deposited silicon during
annealing to form a silicide layer. The lattice spacing of titanium
silicide and cobalt silicide are close to that of silicon, and it
appears that such silicide layers may serve as "crystallization
templates" or "seeds" for adjacent deposited silicon as the
deposited silicon crystallizes (e.g., silicide layer 50 enhances
the crystalline structure of silicon diode 14 during annealing).
Lower resistivity silicon thereby is provided. Similar results may
be achieved for silicon-germanium alloy and/or germanium
diodes.
[0047] In embodiments in which a nitride layer was formed at a top
surface of silicide-forming metal layer 52, following the RTA step,
the nitride layer may be stripped using a wet chemistry. For
example, if silicide-forming metal layer 52 includes a TiN top
layer, a wet chemistry (e.g., ammonium, peroxide, water in a 1:1:1
ratio) may be used to strip any residual TiN.
[0048] A barrier layer 33, such as titanium nitride, tantalum
nitride, tungsten nitride, or other similar barrier layer material,
may be formed above carbon layer 12.
[0049] In exemplary methods in accordance with this invention,
described in more detail with respect to FIGS. 4 and 5, processing
methods are used to protect carbon layer 12 from damage during
subsequent processing steps. In a first exemplary method of this
invention, a hard mask layer is formed above metal layer 35, and
photoresist is deposited above the hard mask layer. The photoresist
is patterned and developed to form patterned photoresist regions.
The patterned photoresist regions are then used to pattern and etch
the hardmask layer to form patterned hardmask regions. The
patterned photoresist regions are then removed, such as by a
conventional ashing process. The patterned hardmask regions are
then used to pattern and etch metal layer 35, barrier layer 33,
carbon layer 12, barrier layer 24, silicide forming metal layer 52,
silicide layer 50, diode 14 and barrier layer 28. In this regard,
carbon layer 12 remains protected by barrier layer 33 during the
ashing process.
[0050] In an alternative method of this invention, photoresist is
deposited on metal layer 35, and the photoresist is patterned and
developed to form patterned photoresist. The patterned photoresist
regions are then used to pattern and etch metal layer 35, barrier
layer 33, carbon layer 12, barrier layer 24, silicide forming metal
layer 52, silicide layer 50, diode 14 and barrier layer 28. The
patterned photoresist regions are then removed by a two-step
"engineered ash" process that removes the photoresist without
substantially damaging carbon layer 12.
Exemplary Fabrication Processes for Memory Cells
[0051] Referring now to FIGS. 4 and 5, exemplary methods in
accordance with this invention for forming a memory level are
described. In particular, FIGS. 4 and 5 illustrate exemplary
methods of forming an exemplary memory level that includes memory
cells 10 of FIG. 3. As will be described below, the first memory
level includes a plurality of memory cells that each include a
steering element and a carbon-based reversible resistance switching
element coupled to the steering element. Additional memory levels
may be fabricated above the first memory level (as described
previously with reference to FIGS. 2C-2D).
[0052] With reference to FIG. 4A, substrate 100 is shown as having
already undergone several processing steps. Substrate 100 may be
any suitable substrate such as a silicon, germanium,
silicon-germanium, undoped, doped, bulk, silicon-on-insulator
("SOI") or other substrate with or without additional circuitry.
For example, substrate 100 may include one or more n-well or p-well
regions (not shown).
[0053] Isolation layer 102 is formed above substrate 100. In some
embodiments, isolation layer 102 may be a layer of silicon dioxide,
silicon nitride, silicon oxynitride or any other suitable
insulating layer.
[0054] Following formation of isolation layer 102, an adhesion
layer 104 is formed over isolation layer 102 (e.g., by physical
vapor deposition ("PVD") or another method). For example, adhesion
layer 104 may be about 20 to about 500 angstroms, and preferably
about 100 angstroms, of titanium nitride or another suitable
adhesion layer such as tantalum nitride, tungsten nitride,
combinations of one or more adhesion layers, or the like. Other
adhesion layer materials and/or thicknesses may be employed. In
some embodiments, adhesion layer 104 may be optional.
[0055] After formation of adhesion layer 104, a conductive layer
106 is deposited over adhesion layer 104. Conductive layer 106 may
include any suitable conductive material such as tungsten or
another appropriate metal, heavily doped semiconductor material, a
conductive silicide, a conductive silicide-germanide, a conductive
germanide, or the like deposited by any suitable method (e.g.,
chemical vapor deposition ("CVD"), PVD, etc.). In at least one
embodiment, conductive layer 106 may comprise about 200 to about
2500 angstroms of tungsten. Other conductive layer materials and/or
thicknesses may be used.
[0056] Following formation of conductive layer 106, adhesion layer
104 and conductive layer 106 are patterned and etched. For example,
adhesion layer 104 and conductive layer 106 may be patterned and
etched using conventional lithography techniques, with a soft or
hard mask, and wet or dry etch processing. In at least one
embodiment, adhesion layer 104 and conductive layer 106 are
patterned and etched to form substantially parallel, substantially
co-planar first conductors 20. Exemplary widths for first
conductors 20 and/or spacings between first conductors 20 range
from about 200 to about 2500 angstroms, although other conductor
widths and/or spacings may be used.
[0057] After first conductors 20 have been formed, a dielectric
layer 58a is formed over substrate 100 to fill the voids between
first conductors 20. For example, approximately 3000-7000 angstroms
of silicon dioxide may be deposited on the substrate 100 and
planarized using chemical mechanical polishing or an etchback
process to form a planar surface 110. Planar surface 110 includes
exposed top surfaces of first conductors 20 separated by dielectric
material (as shown). Other dielectric materials such as silicon
nitride, silicon oxynitride, low K dielectrics, etc., and/or other
dielectric layer thicknesses may be used. Exemplary low K
dielectrics include carbon doped oxides, silicon carbon layers, or
the like.
[0058] In other embodiments of the invention, first conductors 20
may be formed using a damascene process in which dielectric layer
58a is formed, patterned and etched to create openings or voids for
first conductors 20. The openings or voids then may be filled with
adhesion layer 104 and conductive layer 106 (and/or a conductive
seed, conductive fill and/or barrier layer if needed). Adhesion
layer 104 and conductive layer 106 then may be planarized to form
planar surface 110. In such an embodiment, adhesion layer 104 will
line the bottom and sidewalls of each opening or void.
[0059] Following planarization, the diode structures of each memory
cell are formed. With reference to FIG. 4B, a barrier layer 28 is
formed over planarized top surface 110 of substrate 100. Barrier
layer 28 may be about 20 to about 500 angstroms, and preferably
about 100 angstroms, of titanium nitride or another suitable
barrier layer such as tantalum nitride, tungsten nitride,
combinations of one or more barrier layers, barrier layers in
combination with other layers such as titanium/titanium nitride,
tantalum/tantalum nitride or tungsten/tungsten nitride stacks, or
the like. Other barrier layer materials and/or thicknesses may be
employed.
[0060] After deposition of barrier layer 28, deposition of the
semiconductor material used to form the diode of each memory cell
begins (e.g., diode 14 in FIGS. 2 and 3). Each diode may be a
vertical p-n or p-i-n diode as previously described. In some
embodiments, each diode is formed from a polycrystalline
semiconductor material such as polysilicon, a polycrystalline
silicon-germanium alloy, polygermanium or any other suitable
material. For convenience, formation of a polysilicon,
downward-pointing diode is described herein. It will be understood
that other materials and/or diode configurations may be used.
[0061] With reference to FIG. 4B, following formation of barrier
layer 28, a heavily doped n+ silicon layer 14a is deposited on
barrier layer 28. In some embodiments, n+ silicon layer 14a is in
an amorphous state as deposited. In other embodiments, n+ silicon
layer 14a is in a polycrystalline state as deposited. CVD or
another suitable process may be employed to deposit n+ silicon
layer 14a. In at least one embodiment, n+ silicon layer 14a may be
formed, for example, from about 100 to about 1000 angstroms,
preferably about 100 angstroms, of phosphorus or arsenic doped
silicon having a doping concentration of about 10.sup.21 cm.sup.-3.
Other layer thicknesses, doping types and/or doping concentrations
may be used. N+ silicon layer 14a may be doped in situ, for
example, by flowing a donor gas during deposition. Other doping
methods may be used (e.g., implantation).
[0062] After deposition of n+ silicon layer 14a, a lightly doped,
intrinsic and/or unintentionally doped silicon layer 14b may be
formed over n+ silicon layer 14a. In some embodiments, intrinsic
silicon layer 14b may be in an amorphous state as deposited. In
other embodiments, intrinsic silicon layer 14b may be in a
polycrystalline state as deposited. CVD or another suitable
deposition method may be employed to deposit intrinsic silicon
layer 14b. In at least one embodiment, intrinsic silicon layer 14b
may be about 500 to about 4800 angstroms, preferably about 2500
angstroms, in thickness. Other intrinsic layer thicknesses may be
used.
[0063] A thin (e.g., a few hundred angstroms or less) germanium
and/or silicon-germanium alloy layer (not shown) may be formed on
n+ silicon layer 14a prior to depositing intrinsic silicon layer
14b to prevent and/or reduce dopant migration from n+ silicon layer
14a into intrinsic silicon layer 14b (as described in the '331
Application, previously incorporated).
[0064] Heavily doped, p-type silicon may be either deposited and
doped by ion implantation or may be doped in situ during deposition
to form a p+ silicon layer 14c. For example, a blanket p+ implant
may be employed to implant boron a predetermined depth within
intrinsic silicon layer 14b. Exemplary implantable molecular ions
include BF.sub.2, BF.sub.3, B and the like. In some embodiments, an
implant dose of about 1-5.times.10.sup.15 ions/cm.sup.2 may be
employed. Other implant species and/or doses may be used. Further,
in some embodiments, a diffusion process may be employed. In at
least one embodiment, the resultant p+ silicon layer 14c has a
thickness of about 100-700 angstroms, although other p+ silicon
layer sizes may be used.
[0065] Following formation of p+ silicon layer 14c, a
silicide-forming metal layer 52 is deposited over p+ silicon layer
14c. Exemplary silicide-forming metals include sputter or otherwise
deposited titanium or cobalt. In some embodiments, silicide-forming
metal layer 52 has a thickness of about 10 to about 200 angstroms,
preferably about 20 to about 50 angstroms and more preferably about
20 angstroms. Other silicide-forming metal layer materials and/or
thicknesses may be used. A nitride layer (not shown) may be formed
at the top of silicide-forming metal layer 52.
[0066] Following formation of silicide-forming metal layer 52, an
RTA step may be performed to form silicide layer 50, consuming all
or a portion of the silicide-forming metal layer 52. The RTA step
may be performed at a temperature between about 650.degree. C. and
about 750.degree. C., more generally between about 600.degree. C.
and about 800.degree. C., preferably at about 750.degree. C., for a
duration between about 10 seconds to about 60 seconds, more
generally between about 10 seconds to about 90 seconds, preferably
about 60 seconds. Following the RTA step, any residual nitride
layer from silicide-forming metal layer 52 may be stripped using a
wet chemistry, as described above, and as is known in the art.
[0067] Following the RTA step and the nitride strip step, a barrier
layer 24 is deposited. Barrier layer 24 may be about 20 to about
500 angstroms, and preferably about 200 angstroms, of titanium
nitride or another suitable barrier layer such as tantalum nitride,
tungsten nitride, combinations of one or more barrier layers,
barrier layers in combination with other layers such as
titanium/titanium nitride, tantalum/tantalum nitride or
tungsten/tungsten nitride stacks, or the like. Other barrier layer
materials and/or thicknesses may be employed. Any suitable method
may be used to form barrier layer 24. For example, PVD, atomic
layer deposition ("ALD"), or the like may be used.
[0068] Next, carbon layer 12 is deposited over barrier layer 24.
Carbon layer 12 may be formed by a PECVD method, for example. Other
methods may be used, including, without limitation, sputter
deposition from a target, PVD, CVD, arc discharge techniques, and
laser ablation. Other methods may be used to form carbon layer 12,
such as a damascene integration method, for example. Carbon layer
12 may include graphitic carbon. In alternative embodiments, other
carbon-based materials may be used, such as graphene, graphite,
carbon nano-tube materials, DLC or other similar carbon-based
materials. Carbon layer 12 is formed having a thickness between
about 100 and about 600 angstroms, more generally between about 1
and about 1000 angstroms. Other thicknesses may be used.
[0069] Referring again to FIG. 4B, barrier layer 33 is formed over
carbon layer 12. Barrier layer 33 may be about 5 to about 800
angstroms, and preferably about 100 angstroms, of titanium nitride
or another suitable barrier layer such as tantalum nitride,
tungsten nitride, combinations of one or more barrier layers,
barrier layers in combination with other layers such as
titanium/titanium nitride, tantalum/tantalum nitride or
tungsten/tungsten nitride stacks, or the like. Other barrier layer
materials and/or thicknesses may be employed.
[0070] Next, a metal layer 35 may be deposited over barrier layer
33. For example, between about 800 to about 1200 angstroms, more
generally between about 500 angstroms to about 1500 angstroms, of
tungsten may be deposited on barrier layer 33. Other materials and
thicknesses may be used. Any suitable method may be used to form
metal layer 35. For example, CVD, PVD, or the like may be employed.
As described in more detail below, metal layer 35 may be used as a
hard mask layer, and also may be used as a stop during a subsequent
chemical mechanical planarization ("CMP") step. A hard mask is an
etched layer which serves to pattern the etch of an underlying
layer.
[0071] In accordance with this invention, processing methods are
used to protect carbon layer 12 from damage during subsequent
processing steps. In an exemplary method of this invention, a hard
mask is used to avoid damage to carbon layer 12 during subsequent
processing steps. In an alternative method of this invention, an
"engineered ash" process is used that removes photoresist, without
causing substantial damage carbon layer 12. Each of these will be
discussed in turn.
Hardmask
[0072] In a first exemplary method of this invention, and
continuing to refer to FIG. 4B, a dielectric hard mask layer 94 is
deposited over metal layer 35. For example, about 200 to about 3000
angstroms of silicon dioxide may be deposited. Other dielectric
materials such as silicon oxide, silicon nitride, silicon
oxynitride, amorphous carbon, amorphous silicon, boron nitride, low
K dielectrics, and other similar dielectric materials, and/or other
dielectric layer thicknesses may be used. Exemplary low K
dielectrics include carbon doped oxides, silicon carbon layers, or
the like. For example, PECVD, low pressure chemical vapor
deposition ("LPCVD"), or other similar methods may be employed to
form hard mask layer 94.
[0073] After depositing dielectric hard mask layer 94, a
photoresist layer 96 is formed on hard mask layer 94. Photoresist
layer 96 may be between about 200 to 2000 angstroms of any suitable
positive or negative resist material, such as
polymethylmethacrylate ("PMMA"), or other photosensitive organic
polymers known in the art. Other photoresist layer materials and/or
thicknesses may be employed. Photoresist layer 96 may be formed
using a spin-on technique or other similar method.
[0074] Referring now to FIG. 4C, photoresist layer 96 is next
patterned and developed to a desired width. For example,
photoresist layer 96 may be patterned and etched using conventional
lithography techniques. As shown in FIG. 4C, photoresist layer 96
is patterned and developed to form substantially parallel,
substantially coplanar patterned photoresist regions 96. In the
exemplary embodiment, photoresist regions 96 each have a width
substantially the same as the width of conductors 20 below. Other
photoresist region widths may be used.
[0075] With reference to FIG. 4D, photoresist regions 96 are used
to pattern and etch dielectric hard mask layer 94 to a top surface
of metal layer 35, to form hardmask regions 94. A hard mask is an
etched layer which serves to pattern the etch of an underlying
layer. Conventional etch techniques, such as wet or dry etch
processing, or other similar etching techniques, may be used. Metal
layer 35 may serve as an etch stop.
[0076] After hard mask layer 94 is etched, photoresist regions 96
are removed. Conventional plasma ashing techniques, in which the
substrate is exposed to an oxidative or reductive plasma etch, may
be used to remove photoresist layer 96. Because carbon layer 12
remains covered (e.g., by metal layer 35 and barrier layer 33)
during the ashing step, the ashing process does not damage carbon
layer 12.
[0077] After photoresist regions 96 have been removed, dielectric
hardmask regions 94 remain, as illustrated in FIG. 4E. Dielectric
hard mask regions 94 are then used to pattern and etch selected
layers that will form the memory cells.
[0078] One or more etch steps may be performed. In the exemplary
embodiment, metal layer 35, barrier layer 33, carbon layer 12,
barrier layer 24, silicide-forming metal layer 52, diode layers
14a-14c, and barrier layer 28 are etched in a single etch step to
the top surface of dielectric layer 58a, to form substantially
parallel pillars 132 having a width substantially equal to the
width of conductors 20 below, as illustrated in FIG. 4F. Persons of
ordinary skill in the art will understand that other combinations
of layers may be etched in separate etch steps. Persons of ordinary
skill in the art will understand that pillars 132 may have a
smaller width than conductors 20.
[0079] The memory cell layers may be etched using chemistries
selected to minimize or avoid damage to carbon material. For
example, O.sub.2, CO, CO.sub.2, N.sub.2, or H.sub.2, or other
similar chemistries may be used. In embodiments in which CNT
material is used in the memory cells, oxygen ("O.sub.2"), boron
trichloride ("BCl.sub.3") and/or chlorine ("Cl.sub.2") chemistries,
or other similar chemistries, may be used. Any suitable etch
parameters, flow rates, chamber pressures, power levels, process
temperatures, and/or etch rates may be used. Exemplary methods for
etching carbon material are described, for example, in U.S. patent
application Ser. No. 12/415,964, "Electronic Devices Including
Carbon-Based Films Having Sidewall Liners, and Methods of Forming
Such Devices," filed Mar. 31, 2009 (Docket No. SD-MXA-315), which
is hereby incorporated by reference in its entirety for all
purposes.
[0080] After the memory cell layers have been etched, pillars 132
may be cleaned. In some embodiments, a dilute hydrofluoric/sulfuric
acid clean is performed. Post-etch cleaning may be performed in any
suitable cleaning tool, such as a Raider tool, available from
Semitool of Kalispell, Mont. Exemplary post-etch cleaning may
include using ultra-dilute sulfuric acid (e.g., about 1.5-1.8 wt %)
for about 60 seconds and ultra-dilute hydrofluoric ("HF") acid
(e.g., about 0.4-0.6 wt %) for about 60 seconds. Megasonics may or
may not be used. Alternatively, H.sub.2SO.sub.4 may be used.
[0081] After pillars 132 have been cleaned, an in-situ anneal or
degas in vacuum step may be performed. Carbon material tends to
absorb moisture, especially during a wet clean process. This is
problematic, because trapped moisture may result in de-lamination
of carbon material and degradation in switching. In-situ annealing
or degas in vacuum helps to drive out moisture before the next
process step. In particular, the in-situ anneal or degas in vacuum
is performed in the chamber of the next processing step. Degas in
vacuum can also be performed in a transfer chamber or loadlock
mounted on the same platform as that process chamber. For example,
if the next processing step is formation of a sidewall liner, the
in-situ anneal is performed in the chamber used to form the
sidewall liner. The in-situ anneal may be performed at a
temperature between about 200.degree. C. and about 350.degree. C.,
more generally between about 200.degree. C. and about 450.degree.
C., for a duration between about 1 to about 2 minutes, more
generally between about 30 seconds and about 5 minutes, at a
pressure of between about 0.1 mT to about 10 T, more generally
between about 0.1 mT to about 760 T. Alternatively, the in-situ
anneal may be performed in an environment containing Ar, He, or
N.sub.2, or a forming gas containing H.sub.2 and N.sub.2, at a flow
rate of between about 1000 to about 8000 sccm, more generally
between about 1000-20000 sccm. If degas in vacuum step is used
instead of in-situ annealing, the degas is performed at a pressure
between about 0.1 mT to about 50 mT, and at a temperature between
about room temperature to about 450.degree. C.
[0082] Next, a conformal dielectric liner 54 is deposited above and
around pillars 132, resulting in the exemplary structure
illustrated in FIG. 4G. Dielectric liner 54 may be formed with an
oxygen-poor deposition chemistry (e.g., without a high density of
oxygen plasma) to protect sidewalls of carbon layer 12 during a
subsequent deposition containing a high oxygen plasma density of
gap-fill dielectric 58b (e.g., SiO.sub.2) (not shown in FIG.
4E).
[0083] In an exemplary embodiment of this invention, dielectric
liner 54 may be formed from boron nitride, such as described in
commonly owned co-pending U.S. patent application Ser. No.
12/536,457, "A Memory Cell That Includes A Carbon-Based Memory
Element And Methods Of Forming The Same,"filed Aug. 5, 2009 (Docket
Number SD-MXA-335), which is incorporated by reference herein in
its entirely for all purposes. Alternatively, dielectric sidewall
liner 54 may be formed from other materials, such as SiN,
Si.sub.xC.sub.yN.sub.z, Si.sub.xO.sub.yN.sub.z,
Si.sub.xB.sub.yN.sub.z, (with low O content), where x, y and z are
non-zero numbers resulting in stable compounds. Persons of ordinary
skill in the art will understand that other dielectric materials
may be used to form dielectric liner 54.
[0084] In one exemplary embodiment, a SiN dielectric sidewall liner
54 may be formed by PECVD using the process parameters listed in
Table 1. Liner film thickness scales linearly with time. Other
powers, temperatures, pressures, thicknesses and/or flow rates may
be used.
TABLE-US-00001 TABLE 1 PECVD SiN LINER PROCESS PARAMETERS EXEMPLARY
PROCESS PARAMETER RANGE PREFERRED RANGE SiH.sub.4 Flow Rate (slm)
0.1-2.0 0.4-0.7 NH.sub.3 Flow Rate (slm) 1-10 2-8 N.sub.2 Flow Rate
(slm) 0.5-10 1.0-5 Temperature (.degree. C.) 300-500 350-450 Low
Frequency Bias (kW) 0-1 0.2-0.6 High Frequency Bias (kW) 0-1
0.2-0.6 Thickness (Angstroms) 100-500 250-350
[0085] With reference to FIG. 4H, an anisotropic etch is used to
remove lateral portions of sidewall liner 54, leaving only sidewall
portions of sidewall liner 54 on the sides of pillars 132. For
example, a sputter etch or other suitable process may be used to
anisotropically etch sidewall liner 54. Dielectric sidewall liner
54 may protect the carbon material of carbon layer 12 from damage
during deposition of dielectric layer 58b (not shown in FIG. 4F),
described below.
[0086] After pillars 132 have been formed, a dielectric layer 58b
is deposited over pillars 132 to gapfill between pillars 132. For
example, approximately 2000-7000 angstroms of silicon dioxide may
be deposited and planarized using CMP or an etchback process to
remove excess dielectric layer material 58b and dielectric hard
mask layer 94 to form a planar surface 134, resulting in the
structure illustrated in FIG. 41. During the planarization process,
metal layer 35 may be used as a CMP stop. Planar surface 134
includes exposed top surfaces of pillars 132 separated by
dielectric material 58b (as shown). Other dielectric materials may
be used for the dielectric layer 58b such as silicon nitride,
silicon oxynitride, low K dielectrics, etc., and/or other
dielectric layer thicknesses may be used. Exemplary low K
dielectrics include carbon doped oxides, silicon carbon layers, or
the like.
[0087] With reference to FIG. 4J, second conductors 22 may be
formed above pillars 132 in a manner similar to the formation of
first conductors 20. For example, in some embodiments, one or more
barrier layers and/or adhesion layers 26 may be deposited over
pillars 132 prior to deposition of a conductive layer 140 used to
form second conductors 22. Barrier and/or adhesion layer 26 may be
about 20 to about 500 angstroms, and more preferably about 200
angstroms, of titanium nitride or another suitable barrier layer
such as tantalum nitride, tungsten nitride, combinations of one or
more barrier layers, barrier layers in combination with other
layers such as titanium/titanium nitride, tantalum/tantalum nitride
or tungsten/tungsten nitride stacks, or the like. Other barrier
layer materials and/or thicknesses may be employed.
[0088] Conductive layer 140 may be formed from any suitable
conductive material such as tungsten, another suitable metal,
heavily doped semiconductor material, a conductive silicide, a
conductive silicide-germanide, a conductive germanide, or the like
deposited by PVD or any other any suitable method (e.g., CVD,
etc.). In at least one embodiment, conductive layer 140 may
comprise about 200 to about 2500 angstroms of tungsten. Other
conductive layer materials and/or thicknesses may be used.
[0089] The deposited conductive layer 140 and barrier and/or
adhesion layer 26 may be patterned and etched to form second
conductors 22. In at least one embodiment, second conductors 22 are
substantially parallel, substantially coplanar conductors that
extend in a different direction than first conductors 20.
[0090] In other embodiments of the invention, second conductors 22
may be formed using a damascene process in which a dielectric layer
is formed, patterned and etched to create openings or voids for
conductors 22. The openings or voids may be filled with adhesion
layer 26 and conductive layer 140 (and/or a conductive seed,
conductive fill and/or barrier layer if needed). Adhesion layer 26
and conductive layer 140 then may be planarized to form a planar
surface.
[0091] Following formation of second conductors 22, the resultant
structure may be annealed to crystallize the deposited
semiconductor material of diodes 14 (and/or to form silicide
regions by reaction of the silicide-forming metal layer 52 with p+
region 14c). The lattice spacing of titanium silicide and cobalt
silicide are close to that of silicon, and it appears that silicide
layers 50 may serve as "crystallization templates" or "seeds" for
adjacent deposited silicon as the deposited silicon crystallizes
(e.g., silicide layer 50 enhances the crystalline structure of
silicon diode 14 during annealing at temps of about 600-800.degree.
C.). Lower resistivity diode material thereby is provided. Similar
results may be achieved for silicon-germanium alloy and/or
germanium diodes.
[0092] Thus in at least one embodiment, a crystallization anneal
may be performed for about 10 seconds to about 2 minutes in
nitrogen at a temperature of about 600-800.degree. C., and more
preferably between about 650-750.degree. C. Other annealing times,
temperatures and/or environments may be used.
Two-Step Ash Process
[0093] An alternative method of this invention uses a two-step ash
process to remove photoresist without substantially damaging carbon
layer 12. Referring now to FIG. 5A, an exemplary process in
accordance with this alternative embodiment is described. Barrier
layer 28, diode layers 14a-14c, silicide-forming metal layer 52,
barrier layer 24, carbon layer 12, barrier layer 33 and metal layer
35 are formed as described above in connection with FIG. 2B. Next,
a photoresist layer 96 is formed on metal layer 35. Photoresist
layer 96 may be between about 200-2000 angstroms of any suitable
positive or negative resist material, such as
polymethylmethacrylate ("PMMA"), or other photosensitive organic
polymers known in the art. Other photoresist layer materials and/or
thicknesses may be employed. Photoresist layer 96 may be formed
using a spin-on technique or other similar method.
[0094] Referring now to FIG. 5B, photoresist layer 96 is next
patterned and developed to a desired width. For example,
photoresist layer 96 may be patterned and etched using conventional
lithography techniques. As shown in FIG. 5B, photoresist layer 96
may be patterned and developed to form substantially parallel,
substantially coplanar patterned photoresist regions 96. In the
exemplary embodiment, photoresist regions 96 each have a width
substantially the same as the width of conductors 20 below. Other
photoresist region widths may be used.
[0095] Next, photoresist regions 96 are used to pattern and etch
metal layer 35, barrier layer 33, carbon layer 12, barrier layer
24, silicide-forming metal layer 52, diode layers 14a-14c, and
barrier layer 28 to the top surface of dielectric layer 58a, to
form substantially parallel pillars 132 having a width
substantially equal to the width of conductors 20 below, as
illustrated in FIG. 5C. As described above in connection with FIG.
4F, one or more etch steps may be performed, and the etch
chemistries may be selected to minimize or avoid damage to carbon
material, such as described above.
[0096] As a result of exposure to the etching process, photoresist
regions 96 may develop a hardened crust on the surface of the
material. In particular, photoresist exposed to a gas-phase plasma
etching may develop a hardened crust composed of cross-linked
organic polymer, and may contain small amounts of silicon or metal
atoms. The surface crust may decrease the solubility of photoresist
regions 96 and may increase the resistance of photoresist regions
96 to chemical removal. To overcome these problems, and also
protect carbon layer 12 from damage, methods in accordance with
this invention use a two-step ash process to remove photoresist
regions 12.
[0097] Exemplary two-step ashing methods in accordance with this
invention may use a microwave plasma generating reactor. Such a
reactor may have a microwave source near the substrate, a parallel
plate reactor with a microwave or radio frequency power source, or
a reactor having a helical resonator. In some exemplary
embodiments, the reactor is an inductively coupled plasma
generating reactor.
[0098] In a first ashing step, water ("H.sub.2O") and oxygen
("O.sub.2") are primarily used in a downstream remote plasma (e.g.,
in which the substrate is located away from the plasma and/or not
directly exposed to the plasma) to soften the hardened photoresist
crust. In some embodiments, an additional processing gas, such as
C.sub.xF.sub.y, x=1-4, y=2x, or y=(2x+2), may be used. Persons of
ordinary skill in the art will understand that other gases may be
used. Table 2 below describes an exemplary process window for the
first step of the ashing process.
TABLE-US-00002 TABLE 2 EXEMPLARY 1.sup.st ASHING STEP PROCESS
PARAMETERS EXEMPLARY PREFERRED PROCESS PARAMETER RANGE RANGE
H.sub.2O Flow Rate (sccm) 50-2000 100-1000 O.sub.2 Flow Rate (sccm)
500-5000 500-3000 CF.sub.4 Flow Rate (sccm) 0-500 10-150
H.sub.2O:(O.sub.2 + H.sub.2O) Ratio 0.05-0.2 0.07-0.15
CF.sub.4:(O.sub.2 + CF.sub.4) Ratio 0-0.05 0-0.025 Microwave Power
(Watts) 500-2000 500-1500 RF Power (Watts) 100-1000 100-300
Pressure (Torr) 0.1-2.0 0.2-0.8 Process Temperature (.degree. C.)
5-100 5-40 Processing Time (seconds) 5-300 5-50
Other reactant gas species, flow rates, powers, pressures,
temperatures and processing times may be used.
[0099] In a second ashing step, a directional in-situ
radio-frequency ("RF") generated oxygen-plasma (without remote
plasma) is used to ash the photoresist. In particular, H.sub.2 is
added, which may effectively reduce the photoresist ashing
activation energy, without reducing the carbon layer 12 ashing
activation energy. Therefore, the ashing rate of the photoresist is
substantially independent of temperature, but the ashing rate of
carbon layer 12 is temperature-dependent. As a result, by reducing
the processing temperature, the ashing rate of photoresist regions
12 may remain substantially unchanged, whereas the ashing rate of
carbon layer 12 may substantially decrease. In this regard, the
directionality of the plasma may increase with reduced pressure.
Both effects may reduce the undercut of carbon material on the
sidewall of carbon layer 12.
[0100] Exemplary process parameters for the second ashing step,
using O.sub.2 and H.sub.2, are provided in Table 3 below.
TABLE-US-00003 TABLE 3 EXEMPLARY 2.sup.nd ASHING STEP PROCESS
PARAMETERS EXEMPLARY PREFERRED PROCESS PARAMETER RANGE RANGE
O.sub.2 Flow Rate (sccm) 500-10000 1000-3000 H.sub.2 Flow Rate
(sccm) 50-2000 100-500 H.sub.2:(O.sub.2 + H.sub.2) Ratio 0.05-0.2
0.05-0.15 RF Power (Watts) 100-1500 500-1000 Pressure (Torr)
0.1-2.0 0.2-0.8 Processing Temperature (.degree. C.) 5-250 5-40
Processing Time (seconds) 10-300 10-100
Other reactant gas species, flow rates, powers, pressures,
temperatures and processing times may be used.
[0101] Alternative exemplary process parameters for the second
ashing step, using N.sub.2 and H.sub.2, are provided in Table 4
below.
TABLE-US-00004 TABLE 4 EXEMPLARY 2.sup.nd ASHING STEP PROCESS
PARAMETERS EXEMPLARY PREFERRED PROCESS PARAMETER RANGE RANGE
N.sub.2 Flow Rate (sccm) 1000-5000 1000-3000 H.sub.2 Flow Rate
(sccm) 50-250 50-150 N.sub.2:(N.sub.2 + H.sub.2) Ratio 0.01-0.10
0.02-0.06 RF Power (Watts) 100-1500 500-1000 Pressure (Torr)
0.1-2.0 0.2-0.8 Processing Temperature (.degree. C.) 5-250 5-40
Processing Time (seconds) 10-300 10-100
Other reactant gas species, flow rates, powers, pressures,
temperatures and processing times may be used. The resulting
structure after the two-step ash process is illustrated in FIG.
5D.
[0102] After the memory cell layers have been ashed, pillars 132
may be cleaned. In some embodiments, a dilute hydrofluoric/sulfuric
acid clean is performed. Post-etch cleaning may be performed in any
suitable cleaning tool, such as a Raider tool, available from
Semitool of Kalispell, Mont. Exemplary post-etch cleaning may
include using ultra-dilute sulfuric acid (e.g., about 1.5-1.8 wt %)
for about 60 seconds and ultra-dilute HF acid (e.g., about 0.4-0.6
wt %) for about 60 seconds. Megasonics may or may not be used.
Alternatively, H.sub.2SO.sub.4 may be used.
[0103] After pillars 132 have been cleaned, an in-situ anneal or
degas in vacuum step may be performed. Carbon material tends to
absorb moisture, especially during a wet clean process. This is
problematic, because trapped moisture may result in de-lamination
of carbon material and degradation in switching. In-situ annealing
or degas in vacuum helps to drive out moisture before the next
process step. In particular, the in-situ anneal or degas in vacuum
is performed in the chamber of the next processing step. Degas in
vacuum can also be performed in a transfer chamber or loadlock
mounted on the same platform as that process chamber. For example,
if the next processing step is formation of a sidewall liner, the
in-situ anneal is performed in the chamber used to form the
sidewall liner. The in-situ anneal may be performed at a
temperature between about 200.degree. C. and about 350.degree. C.,
more generally between about 200.degree. C. and about 450.degree.
C., for a duration between about 1 to about 2 minutes, more
generally between about 30 seconds and about 5 minutes, at a
pressure of between about 0.1 mT to about 10 T, more generally
between about 0.1 mT to about 760 T. Alternatively, the in-situ
anneal may be performed in an environment containing Ar, He, or
N.sub.2, or a forming gas containing H.sub.2 and N.sub.2, at a flow
rate of between about 1000 to about 8000 sccm, more generally
between about 1000-20000 sccm. If degas in vacuum step is used
instead of in-situ annealing, the degas is performed at a pressure
between about 0.1 mT to about 50 mT, and at a temperature between
about room temperature to about 450.degree. C.
[0104] As illustrated in FIG. 5E, after the in-situ anneal, a
dielectric sidewall liner 54 is deposited above and between pillars
132, as described above in connection with FIG. 4G. With reference
to FIG. 5F, an anisotropic etch is used to remove lateral portions
of liner 54, leaving only sidewall portions of liner 54 on the
sides of pillars 132, such as described above in connection with
FIG. 4H.
[0105] After pillars 132 have been formed, a dielectric layer 58b
is deposited over pillars 132 to gapfill between pillars 132. For
example, approximately 2000-7000 angstroms of silicon dioxide may
be deposited and planarized using CMP or an etchback process to
remove excess dielectric layer material 58b to form a planar
surface 134, resulting in the structure illustrated in FIG. 5G.
During the planarization process, metal layer 35 may be used as a
CMP stop. Planar surface 134 includes exposed top surfaces of
pillars 132 separated by dielectric material 58b (as shown). Other
dielectric materials may be used for the dielectric layer 58b such
as silicon nitride, silicon oxynitride, low K dielectrics, etc.,
and/or other dielectric layer thicknesses may be used. Exemplary
low K dielectrics include carbon doped oxides, silicon carbon
layers, or the like.
[0106] Next, second conductors 22 are formed above pillars 132, as
described above in connection with FIG. 4J. The resulting structure
is illustrated in FIG. 5H.
[0107] Persons of ordinary skill in the art will understand that
alternative memory cells in accordance with this invention may be
fabricated in other similar techniques. For example, memory cells
may be formed that include reversible resistance switching element
12 below diode 14.
[0108] The foregoing description discloses only exemplary
embodiments of the invention. Modifications of the above disclosed
apparatus and methods which fall within the scope of the invention
will be readily apparent to those of ordinary skill in the art. For
instance, in any of the above embodiments, the carbon material may
be located below the diodes 14. As stated, although the invention
has been described primarily with reference to amorphous carbon,
other carbon materials may be similarly used. Further, each
carbon-based layer is preferably formed between two conducting
layers such as titanium nitride or other barrier/adhesion layers to
form a MIM stack in series with a steering element.
[0109] Accordingly, although the present invention has been
disclosed in connection with exemplary embodiments thereof, it
should be understood that other embodiments may fall within the
spirit and scope of the invention, as defined by the following
claims.
* * * * *