U.S. patent application number 12/215778 was filed with the patent office on 2009-12-31 for substrate fins with different heights.
Invention is credited to Michael K. Harper, Willy Rachmady, Justin S. Sandford.
Application Number | 20090321834 12/215778 |
Document ID | / |
Family ID | 41446344 |
Filed Date | 2009-12-31 |
United States Patent
Application |
20090321834 |
Kind Code |
A1 |
Rachmady; Willy ; et
al. |
December 31, 2009 |
Substrate fins with different heights
Abstract
A device includes a number of fins. Some of the fins have
greater heights than other fins. This allows the selection of
different drive currents and/or transistor areas.
Inventors: |
Rachmady; Willy; (Beaverton,
OR) ; Sandford; Justin S.; (Tigard, OR) ;
Harper; Michael K.; (Hillsboro, OR) |
Correspondence
Address: |
INTEL CORPORATION;c/o CPA Global
P.O. BOX 52050
MINNEAPOLIS
MN
55402
US
|
Family ID: |
41446344 |
Appl. No.: |
12/215778 |
Filed: |
June 30, 2008 |
Current U.S.
Class: |
257/365 ;
257/E21.546; 257/E29.264; 438/424 |
Current CPC
Class: |
H01L 21/76232 20130101;
H01L 21/76 20130101; H01L 21/823431 20130101; H01L 29/785 20130101;
H01L 29/66795 20130101 |
Class at
Publication: |
257/365 ;
438/424; 257/E21.546; 257/E29.264 |
International
Class: |
H01L 21/762 20060101
H01L021/762; H01L 27/088 20060101 H01L027/088 |
Claims
1-12. (canceled)
13. A semiconductor device, comprising: a substrate; a first
multi-gate transistor on a first portion of the substrate, the
first multi-gate transistor comprising a first fin, the first fin
having a first height above a first isolation region; and a second
multi-gate transistor on a second portion of the substrate, the
second multi-gate transistor comprising a second fin, the second
fin having a second height above a second isolation region, the
second height being greater than the first height.
14. The device of claim 13, wherein the first multi-gate transistor
is an N-type transistor and the second multi-gate transistor is a
P-type transistor.
15. The device of claim 14, further comprising a memory cell,
wherein both the first and second multi-gate transistors are
transistors of the memory cell.
16. The device of claim 14, further comprising a ring oscillator,
wherein both the first and second multi-gate transistors are
transistors of the ring oscillator.
17. The device of claim 14 wherein the second height is greater
than the first height in an amount great enough that the drive
current of the first transistor is within 10% of the drive current
of the second transistor.
18. The device of claim 17 wherein first multi-gate transistor has
a first area, the second multi-gate transistor has a second area,
and the first area is within about 15% of the second area.
19. The device of claim 13 wherein the second height is at least
25% greater than the first height.
20. The device of claim 13, further comprising a third multi-gate
transistor on a third portion of the substrate, the third
multi-gate transistor comprising a third fin, the third fin having
a third height above a third isolation region, the third height
being greater than the second height.
Description
BACKGROUND
Background of the Invention
[0001] Multi-gate devices such as transistors may be formed on fin
structures. The gate channel "width" of such a multi-gate device
may depend at least in part on the height of the fin.
BRIEF DESCRIPTION OF THE DRAWINGS
[0002] FIG. 1 is a cross sectional side view that illustrates a
plurality of fins of different heights on the same substrate.
[0003] FIG. 2 is a cross sectional side view that illustrates the
substrate.
[0004] FIG. 3 is a cross sectional side view that illustrates the
substrate after isolation regions have been formed.
[0005] FIG. 4 is a cross sectional side view that illustrates a
mask.
[0006] FIG. 5 is a cross-sectional side view that illustrates the
patterned mask layer.
[0007] FIG. 6 is a cross-sectional side view that illustrates a
time part way through an etching process that is used to form the
fins.
[0008] FIG. 7 is a cross-sectional side view that illustrates
another time part way through an etching process that is used to
form the fins.
[0009] FIG. 8 is a cross-sectional side view that illustrates
patterned mask layers that may be used to form fins having three
different heights.
[0010] FIG. 9 is a cross-sectional side view that illustrates the
fins resulting from the two different patterned mask layers
illustrated in FIG. 8.
[0011] FIG. 10 is a cross-sectional side view that illustrates one
application to which fins may be put: a multi-gate transistor.
[0012] FIG. 11 is an isometric view that illustrates the
transistor.
[0013] FIGS. 12 and 13 are block diagrams that illustrate
applications in which the above-mentioned NMOS and PMOS transistors
may be used.
DETAILED DESCRIPTION
[0014] Various embodiments of a substrate having fins of different
heights are discussed in the following description. One skilled in
the relevant art will recognize that the various embodiments may be
practiced without one or more of the specific details, or with
other replacement and/or additional methods, materials, or
components. In other instances, well-known structures, materials,
or operations are not shown or described in detail to avoid
obscuring aspects of various embodiments of the invention.
Similarly, for purposes of explanation, specific numbers,
materials, and configurations are set forth in order to provide a
thorough understanding of the invention. Nevertheless, the
invention may be practiced without specific details. Furthermore,
it is understood that the various embodiments shown in the figures
are illustrative example representations and are not necessarily
drawn to scale.
[0015] Reference throughout this specification to "one embodiment"
or "an embodiment" means that a particular feature, structure,
material, or characteristic described in connection with the
embodiment is included in at least one embodiment of the invention,
but do not denote that they are present in every embodiment. Thus,
the appearances of the phrases "in one embodiment" or "in an
embodiment" in various places throughout this specification are not
necessarily referring to the same embodiment of the invention.
Furthermore, the particular features, structures, materials, or
characteristics may be combined in any suitable manner in one or
more embodiments. Various additional layers and/or structures may
be included and/or described features may be omitted in other
embodiments.
[0016] Various operations will be described as multiple discrete
operations in turn, in a manner that is most helpful in
understanding the invention. However, the order of description
should not be construed as to imply that these operations are
necessarily order dependent. In particular, these operations need
not be performed in the order of presentation. Operations described
may be performed in a different order, in series or in parallel,
than the described embodiment. Various additional operations may be
performed and/or described operations may be omitted in additional
embodiments.
[0017] FIG. 1 is a cross sectional side view that illustrates a
plurality of fins 124 of different heights on the same substrate
102, according to one embodiment of the described invention. This
substrate 102 may comprise any material that may serve as a
foundation upon which a semiconductor device may be built. In one
example, substrate 102 comprises silicon, although another material
or other materials may be used in other examples. The substrate 102
may be a portion of a bulk substrate, such as a wafer of single
crystal silicon, a silicon-on-insulator (SOI) substrate 102 such as
a layer of silicon on a layer of insulating material on another
layer of silicon, a germanium substrate 102, a group III-V material
(such as GaAs, InSb, InAl, etc.) substrate 102, may be a substrate
102 comprising multiple layers, or another type of substrate 102
comprising other material or materials.
[0018] Fins 124 have been formed on the substrate 102. Rather than
all fins 124 having the same height, the fins 124 have differing
heights above isolation regions 104. Fins 124A through 124C have a
smaller height 120 while fins 124D through 124G have a larger
height 122. This difference between heights 120 and 122 is
selectable by choosing materials and etchants. In an embodiment,
the greater height 122 is selected to be between a height roughly
equal to the lower height 120 and a height about twice as great as
the lower height 120 (i.e. height 120 is between 99% and 50% of
height 122). In another embodiment, the greater height 122 may be
more than twice the lower height 120. In an embodiment, the lower
height 120 may be between 15-20 nanometers, and the greater height
122 30-40 nanometers, although the invention is not limited to fins
124 within those height ranges.
[0019] Such an ability to have fins 124 of different height allows
multi-gate transistors to be made on the fins 124 with different
desired properties. As the drive current of a transistor is
dependent on the gate channel "width" of a multi-gate transistor,
and the "width" may be made greater by use of a taller fin 124
without increasing the area of the transistor, selectable
multi-height fins 124 allow the transistors with the same area to
have selected drive currents based on the fin heights. In other
embodiments, different areas of transistors may be selected without
changing drive currents by selecting the fin heights. Rather than
having one selectable parameter, transistor area, with which to
affect drive currents, designers may independently select
transistor height and area to achieve desired device
characteristics.
[0020] FIGS. 2 through 9 are cross sectional side views that
illustrate how fins 124 of different heights on the same substrate
102 may be formed according to one embodiment.
[0021] FIG. 2 is a cross sectional side view that illustrates the
substrate 102. As discussed above, the substrate 102 may comprise
any material that may serve as a foundation upon which a
semiconductor device may be built.
[0022] FIG. 3 is a cross sectional side view that illustrates the
substrate 102 after isolation regions 104 have been formed. These
isolation regions 104 may be, for example, shallow trench isolation
regions. Any suitable method for forming isolation regions 104 may
be used, and the isolation regions 104 may comprise any suitable
material. A suitable isolation region 104 material is one that may
be selectively etched while leaving the substrate 102 material
substantially intact. In one embodiment, the isolation regions 104
comprise a silicon oxide material and the substrate 102 comprises
silicon. Other suitable isolation region materials include, for
example, silicon dioxide (which may be deposited in a variety of
processes), and spin-on glass (SOG), among others.
[0023] The formation of the isolation regions 104 also results in
pre-fin regions 106 of the substrate 102. These pre-fin regions 106
are between the isolation regions 104.
[0024] FIG. 4 is a cross sectional side view that illustrates a
mask layer 108 formed on the substrate 102, isolation regions 104,
and pre-fin regions 106. The mask layer 108 may be formed from a
material that has an etch rate in a selected etchant within an
order of magnitude of the etch rate of the isolation regions 104 in
the selected etchant in one embodiment. In some embodiments, the
mask layer 108 has an etch rate faster than the isolation regions
104 in the selected etchant. In some embodiments, the mask layer
108 has an etch rate that is twice the etch rate of the isolation
regions 104 or less in the selected etchant. In some embodiments,
the mask layer 108 has an etch rate that is one half the etch rate
of the isolation regions 104 or more in the selected etchant. In
one embodiment, the mask layer 108 comprises a silicon nitride
material substantially free from oxygen and carbon. In other
embodiments, the mask layer 108 may comprise a silicon nitride
material with various amounts of oxygen and/or carbon present to
modulate the etch rate, a SiC material, or other materials may also
be used.
[0025] FIG. 5 is a cross-sectional side view that illustrates the
patterned mask layer 110. Any suitable method may be used to
pattern the mask layer 108 of FIG. 4 to result in the patterned
mask layer 110. The patterned mask layer 110 remains over pre-fin
regions 106A-106C, to protect them from part of the etching to
come. Pre-fin regions 106D-106G are unprotected by the patterned
mask layer 110. This will result in pre-fin regions 106A-106C
becoming fins 124A-124C having a smaller height 120 than the height
of fins 124D-124G that stem from pre-fin regions 106D-106G.
[0026] FIG. 6 is a cross-sectional side view that illustrates the
patterned mask layer 110, the pre-fin regions 106, the isolation
regions 104, and the substrate 102 part way through an etching
process that is used to form the fins 124. In FIG. 6, part of the
patterned mask layer 110 has been removed, leaving remaining
partial mask layer 114. Thickness 116 of the patterned mask layer
110 has been removed. Also, a thickness 112 of the isolation
regions 104 has been removed at this point in the etching process.
The difference between thickness 112 and thickness 116 will depend
upon the difference between the etch rates of mask layer 108 and
isolation regions 104. In an embodiment where the mask layer 108
comprises a silicon nitride material, the isolation regions 104
comprise a silicon oxide material, and the substrate 102 and
pre-fin regions 106 comprise silicon, the etchant chosen may be a
hydrofluoric acid (HF). Different etchants and/or different
materials may be used, selected based on the desired etchant rate
difference between the mask layer 108 and the isolation regions
104, and the etch selectivity to etch the mask layer 108 and
isolation regions 104 while leaving the substrate 102 and pre-fin
regions 106 substantially intact. For example, spin-on dielectric
films such as silicate or siloxane can be used as the mask layer
108 or the isolation regions 104, with HF or buffered HF as the
etchant. Other combinations may also be used.
[0027] FIG. 7 is a cross-sectional side view that illustrates the
pre-fin regions 106, the isolation regions 104, and the substrate
102 at another time part way through an etching process that is
used to form the fins 124. At the point illustrated in FIG. 7, all
of the patterned mask layer 110 has been removed, and the isolation
regions 104A-104C formerly protected by the patterned mask layer
110 are about to be etched. At this point, a thickness 118 of
isolation regions 104E-104G, plus the portion of isolation region
104D adjacent pre-fin region 106D, have been removed. This
thickness 118 sets the height differential (height 122 minus height
120) between the taller fins 124D-124G of FIG. 1, and the shorter
fins 124A-124C of FIG. 1 (subject to small variations of the
etching process). Thus, the thickness and etch rate of the material
of the patterned mask layer 110 is chosen to provide the desired
thickness 118, and the desired height differential between the fins
124 of FIG. 1. The etching process will continue after the point
illustrated in FIG. 7 to remove portions of isolation regions
104A-104C and more of isolation regions 104D-104G and result in the
fins 124 of FIG. 1.
[0028] FIG. 1, as mentioned above, is a cross sectional side view
that illustrates differently-heighted fins 124 resulting from the
masking and etching has continued past the point illustrated in
FIG. 7 to remove portions of isolation regions 104A-104C, plus the
left side of isolation region 104D, to form fins 124A-124C with a
desired height 120. This continued etching has also removed more of
isolation regions 104E-104G, plus the right side of isolation
region 104D, to form fins 124D-124G with desired height 122. The
mask layer 108 thickness is chosen based on the desired height
differential 118 and the etch rate difference between the material
of the mask layer 108 and the material of the isolation regions
104. The etch time is selected to etch through the patterned mask
layer 110 and remove portions of isolation regions 104A-104C, plus
the left side of isolation region 104D, to result in desired height
120 of fins 124A-124C.
[0029] FIG. 8 is a cross-sectional side view that illustrates
patterned mask layers 126, 128 that may be used to form fins 124
having three different heights. Isolation regions 104F, 104G, and
the right side of isolation region 104E are not covered by a mask
layer. Patterned mask layer 126 has been patterned to cover
isolation regions 104A-104D, plus the left side of isolation region
104E. Patterned mask layer 128 has been patterned to cover
isolation regions 104A-104C, plus the left side of isolation region
104D. When an etching process is performed, isolation regions 104F,
104G, and the right side of isolation region 104E will be etched
from the start of the process. The right side of isolation region
104D and the left side of isolation region 104E will be etched
after a delay caused by time it takes to remove patterned mask
layer 126. Finally, the left side of isolation region 104D and
isolation regions 104A-104C will be etched after a longer delay
caused by the time it takes to remove both patterned mask layer 128
and patterned mask layer 126.
[0030] FIG. 9 is a cross-sectional side view that illustrates the
fins 124 resulting from the two different patterned mask layers
126, 128 illustrated in FIG. 8. Because they were not covered by a
mask layer, pre-fin regions 106E-106G became the fins 124E-124G
with the greatest height 134. Because it was covered by only one
patterned layer 126, pre-fin region 106D became fin 124D with a
middle height 132. Because they were covered by two patterned mask
layers 126, 128, pre-fin regions 106A-106C became fins 124A-124C
with the shortest height 130.
[0031] The thickness of patterned mask layer 126 is selected based
on the desired height differential between fin 124D and fins
124E-124G (i.e. height 134 minus height 132) and the etch rate
difference between the material of the mask layer 126 and the
material of the isolation regions 104. Similarly, the thickness of
patterned mask layer 128 is selected based on the desired height
differential between fins 124A-124C and fin 124D (i.e. height 132
minus height 130) and the etch rate difference between the material
of the mask layer 128 and the material of the isolation regions
104.
[0032] Additional mask layers may be used to make yet other
differences in the heights of fins 124 on a substrate. More than
three different heights may be created. Rather than multiple
stacked patterned mask layers 126, 128, there may be a first
patterned mask layer with a first thickness covering some pre-fin
regions 106, and a second patterned mask layer with a second
thickness greater than the first thickness covering different
pre-fin regions 106 than those covered by the first patterned mask
layer. Alternatively, mask layers with different etch rates in an
etchant may be used in place of, or in addition to, different
thicknesses. No matter how many different heights are present in
the final set of fins 124, the resulting fins 124 may be used in
any application calling for such structures.
[0033] FIG. 10 is a cross-sectional side view that illustrates one
application to which fins 124 may be put: a multi-gate transistor
135. The illustrated embodiment of the multi-gate transistor 135 is
a tri-gate transistor 135 that includes the fin 124 adjacent the
isolation regions 104. There is a gate dielectric layer 136
adjacent the fin 124, and a gate electrode 138 adjacent the gate
dielectric layer 136. As the gate electrode 138 is adjacent three
sides of the fin 124, the gate channel "width" of the transistor
135 includes the fin 124 width 140 plus twice the fin 124 height
142 (this is why the term channel "width" as used herein has
quotations; the "width" is not merely the width of the channel, but
also includes other dimensions). As the drive current of the
transistor 124 is at least partially dependent on the gate channel
"width" of the transistor 135, the drive current may be increased
by increasing the height 142 while leaving the other dimensions of
the transistor 135 the same.
[0034] FIG. 11 is an isometric view that illustrates the transistor
135. As mentioned above, because the gate channel "width" is
dependent on the height 142 of the fin 124, the drive current of
the transistor 135 may be increased without increasing the fin 124
width 140 or the gate depth 144. This means that by increasing the
height 142 of the fin 124, the drive current may be increased
without the transistor 135 taking up more area. "Area" referring to
area within the X-Y plane; note that in FIGS. 1-10, the X-axis goes
from left to right in the plane of the picture, the Z-axis is up
and down in the plane of the picture, and the Y-axis is normal to
the plane of the picture. Thus, using the embodiment illustrated in
FIG. 1, fins 124A-124C may be used to make multi-gate transistors
135 with lower drive current and fins 124D-124G used to make
multi-gate transistors 135 with higher drive current, with the
areas of each of the multi-gate transistors (in the X-Y plane)
being substantially the same.
[0035] One application is to make NMOS (n-type metal oxide
semiconductor transistors) and PMOS (p-type metal oxide
semiconductor transistors) having substantially the same drive
current while being closer in area compared to NMOS and PMOS
transistors made on fins having equal heights. A PMOS transistor
having the same gate channel "width" as an NMOS transistor will
typically have a lower drive current. By increasing the fin 124
height 142 of the PMOS transistor compared to the NMOS transistor
on the same substrate 102, the PMOS gate "width" can be increased,
and the drive current increased, without increasing the area taken
up by the PMOS transistor. Thus, the PMOS and NMOS transistors 135
on a substrate 102 may have substantially the same area and
substantially the same drive current.
[0036] In other embodiments, the PMOS transistor 135 may have
substantially the same area as the NMOS transistor 135 and the
drive current of the PMOS transistor may be more or less than that
of the NMOS transistor by selecting the fin heights of the
respective transistor types. Alternatively, both the area and fin
height 142 of the PMOS transistor may be selected to each be
greater or less than the NMOS transistor based on the desired drive
current for some specific circuit requirement and acceptable use of
area on the substrate 102.
[0037] In yet other embodiments, the drive current of multiple
instances of a single transistor type (either N- or P-type) may be
varied across a single substrate 102 without changing their area by
having different fin 124 heights 142. This may be useful, for
example, when transistors 135 of the same area are desired (e.g.
when design rules that dictate spacing of transistors are based on
transistor area) yet different drive currents are desired. The area
and height of the fin 124 may each be separately chosen by the
device designer to result in a device such as a transistor having
the desired drive current and area.
[0038] FIGS. 12 and 13 are block diagrams that illustrate
applications in which the above-mentioned NMOS and PMOS transistors
135 may be used. FIG. 12 includes a die 150 and a memory cell 148
that is part of the die 150. The memory cell 148, which may be, for
example, a SRAM cell 148, includes a number of both NMOS and PMOS
multi-gate transistors 135. The PMOS transistors 135 have a taller
fin 124 than the NMOS transistors 135 so that transistors 135 of
both types have substantially the same area and substantially the
same drive current. FIG. 13 includes a die 150 and a ring
oscillator 152 that is part of the die 150. The ring oscillator 152
includes a number of both NMOS and PMOS multi-gate transistors 135.
The PMOS transistors 135 have a taller fin 124 than the NMOS
transistors 135 so that transistors 135 of both types have
substantially the same area and substantially the same drive
current. Numerous other examples of devices and circuits that would
benefit from transistors 135 with different height 142 fins 124 are
also possible.
[0039] The foregoing description of the embodiments of the
invention has been presented for the purposes of illustration and
description. It is not intended to be exhaustive or to limit the
invention to the precise forms disclosed. This description and the
claims following include terms, such as left, right, top, bottom,
over, under, upper, lower, first, second, etc. that are used for
descriptive purposes only and are not to be construed as limiting.
For example, terms designating relative vertical position refer to
a situation where a device side (or active surface) of a substrate
or integrated circuit is the "top" surface of that substrate; the
substrate may actually be in any orientation so that a "top" side
of a substrate may be lower than the "bottom" side in a standard
terrestrial frame of reference and still fall within the meaning of
the term "top." The term "on" as used herein (including in the
claims) does not indicate that a first layer "on" a second layer is
directly on and in immediate contact with the second layer unless
such is specifically stated; there may be a third layer or other
structure between the first layer and the second layer on the first
layer. The embodiments of a device or article described herein can
be manufactured, used, or shipped in a number of positions and
orientations. Persons skilled in the relevant art can appreciate
that many modifications and variations are possible in light of the
above teaching. Persons skilled in the art will recognize various
equivalent combinations and substitutions for various components
shown in the Figures. It is therefore intended that the scope of
the invention be limited not by this detailed description, but
rather by the claims appended hereto.
* * * * *